1 /**************************************************************************//** 2 * @file pdma.h 3 * @version V3.00 4 * @brief M2354 series PDMA driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_H__ 10 #define __PDMA_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup PDMA_Driver PDMA Driver 23 @{ 24 */ 25 26 /** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants 27 @{ 28 */ 29 #define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* Operation Mode Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */ 35 #define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */ 36 #define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */ 37 38 /*---------------------------------------------------------------------------------------------------------*/ 39 /* Data Width Constant Definitions */ 40 /*---------------------------------------------------------------------------------------------------------*/ 41 #define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */ 42 #define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */ 43 #define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */ 44 45 /*---------------------------------------------------------------------------------------------------------*/ 46 /* Address Attribute Constant Definitions */ 47 /*---------------------------------------------------------------------------------------------------------*/ 48 #define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */ 49 #define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */ 50 #define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */ 51 #define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */ 52 53 /*---------------------------------------------------------------------------------------------------------*/ 54 /* Burst Mode Constant Definitions */ 55 /*---------------------------------------------------------------------------------------------------------*/ 56 #define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */ 57 #define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */ 58 59 #define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */ 60 #define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */ 61 #define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */ 62 #define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */ 63 #define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */ 64 #define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */ 65 #define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */ 66 #define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */ 67 68 /*---------------------------------------------------------------------------------------------------------*/ 69 /* Table Interrupt Disable Constant Definitions */ 70 /*---------------------------------------------------------------------------------------------------------*/ 71 #define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */ 72 #define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */ 73 74 /*---------------------------------------------------------------------------------------------------------*/ 75 /* Peripheral Transfer Mode Constant Definitions */ 76 /*---------------------------------------------------------------------------------------------------------*/ 77 #define PDMA_MEM 0UL /*!<DMA Connect to Memory \hideinitializer */ 78 #define PDMA_USB_TX 2UL /*!<DMA Connect to USB TX \hideinitializer */ 79 #define PDMA_USB_RX 3UL /*!<DMA Connect to USB RX \hideinitializer */ 80 #define PDMA_UART0_TX 4UL /*!<DMA Connect to UART0 TX \hideinitializer */ 81 #define PDMA_UART0_RX 5UL /*!<DMA Connect to UART0 RX \hideinitializer */ 82 #define PDMA_UART1_TX 6UL /*!<DMA Connect to UART1 TX \hideinitializer */ 83 #define PDMA_UART1_RX 7UL /*!<DMA Connect to UART1 RX \hideinitializer */ 84 #define PDMA_UART2_TX 8UL /*!<DMA Connect to UART2 TX \hideinitializer */ 85 #define PDMA_UART2_RX 9UL /*!<DMA Connect to UART2 RX \hideinitializer */ 86 #define PDMA_UART3_TX 10UL /*!<DMA Connect to UART3 TX \hideinitializer */ 87 #define PDMA_UART3_RX 11UL /*!<DMA Connect to UART3 RX \hideinitializer */ 88 #define PDMA_UART4_TX 12UL /*!<DMA Connect to UART4 TX \hideinitializer */ 89 #define PDMA_UART4_RX 13UL /*!<DMA Connect to UART4 RX \hideinitializer */ 90 #define PDMA_UART5_TX 14UL /*!<DMA Connect to UART5 TX \hideinitializer */ 91 #define PDMA_UART5_RX 15UL /*!<DMA Connect to UART5 RX \hideinitializer */ 92 #define PDMA_USCI0_TX 16UL /*!<DMA Connect to USCI0 TX \hideinitializer */ 93 #define PDMA_USCI0_RX 17UL /*!<DMA Connect to USCI0 RX \hideinitializer */ 94 #define PDMA_USCI1_TX 18UL /*!<DMA Connect to USCI1 TX \hideinitializer */ 95 #define PDMA_USCI1_RX 19UL /*!<DMA Connect to USCI1 RX \hideinitializer */ 96 #define PDMA_QSPI0_TX 20UL /*!<DMA Connect to QSPI0 TX \hideinitializer */ 97 #define PDMA_QSPI0_RX 21UL /*!<DMA Connect to QSPI0 RX \hideinitializer */ 98 #define PDMA_SPI0_TX 22UL /*!<DMA Connect to SPI0 TX \hideinitializer */ 99 #define PDMA_SPI0_RX 23UL /*!<DMA Connect to SPI0 RX \hideinitializer */ 100 #define PDMA_SPI1_TX 24UL /*!<DMA Connect to SPI1 TX \hideinitializer */ 101 #define PDMA_SPI1_RX 25UL /*!<DMA Connect to SPI1 RX \hideinitializer */ 102 #define PDMA_SPI2_TX 26UL /*!<DMA Connect to SPI2 TX \hideinitializer */ 103 #define PDMA_SPI2_RX 27UL /*!<DMA Connect to SPI2 RX \hideinitializer */ 104 #define PDMA_SPI3_TX 28UL /*!<DMA Connect to SPI3 TX \hideinitializer */ 105 #define PDMA_SPI3_RX 29UL /*!<DMA Connect to SPI3 RX \hideinitializer */ 106 #define PDMA_ADC_RX 30UL /*!<DMA Connect to ADC RX \hideinitializer */ 107 #define PDMA_EPWM0_P1_RX 32UL /*!<DMA Connect to EPWM0 P1 RX \hideinitializer */ 108 #define PDMA_EPWM0_P2_RX 33UL /*!<DMA Connect to EPWM0 P2 RX \hideinitializer */ 109 #define PDMA_EPWM0_P3_RX 34UL /*!<DMA Connect to EPWM0 P3 RX \hideinitializer */ 110 #define PDMA_EPWM1_P1_RX 35UL /*!<DMA Connect to EPWM1 P1 RX \hideinitializer */ 111 #define PDMA_EPWM1_P2_RX 36UL /*!<DMA Connect to EPWM1 P2 RX \hideinitializer */ 112 #define PDMA_EPWM1_P3_RX 37UL /*!<DMA Connect to EPWM1 P3 RX \hideinitializer */ 113 #define PDMA_I2C0_TX 38UL /*!<DMA Connect to I2C0 TX \hideinitializer */ 114 #define PDMA_I2C0_RX 39UL /*!<DMA Connect to I2C0 RX \hideinitializer */ 115 #define PDMA_I2C1_TX 40UL /*!<DMA Connect to I2C1 TX \hideinitializer */ 116 #define PDMA_I2C1_RX 41UL /*!<DMA Connect to I2C1 RX \hideinitializer */ 117 #define PDMA_I2C2_TX 42UL /*!<DMA Connect to I2C2 TX \hideinitializer */ 118 #define PDMA_I2C2_RX 43UL /*!<DMA Connect to I2C2 RX \hideinitializer */ 119 #define PDMA_I2S0_TX 44UL /*!<DMA Connect to I2S0 TX \hideinitializer */ 120 #define PDMA_I2S0_RX 45UL /*!<DMA Connect to I2S0 RX \hideinitializer */ 121 #define PDMA_TMR0 46UL /*!<DMA Connect to TMR0 \hideinitializer */ 122 #define PDMA_TMR1 47UL /*!<DMA Connect to TMR1 \hideinitializer */ 123 #define PDMA_TMR2 48UL /*!<DMA Connect to TMR2 \hideinitializer */ 124 #define PDMA_TMR3 49UL /*!<DMA Connect to TMR3 \hideinitializer */ 125 #define PDMA_TMR4 50UL /*!<DMA Connect to TMR4 \hideinitializer */ 126 #define PDMA_TMR5 51UL /*!<DMA Connect to TMR5 \hideinitializer */ 127 #define PDMA_DAC0_TX 52UL /*!<DMA Connect to DAC0 TX \hideinitializer */ 128 #define PDMA_DAC1_TX 53UL /*!<DMA Connect to DAC1 TX \hideinitializer */ 129 #define PDMA_EPWM0_CH0_TX 54UL /*!<DMA Connect to EPWM0 CH0 TX \hideinitializer */ 130 #define PDMA_EPWM0_CH1_TX 55UL /*!<DMA Connect to EPWM0 CH1 TX \hideinitializer */ 131 #define PDMA_EPWM0_CH2_TX 56UL /*!<DMA Connect to EPWM0 CH2 TX \hideinitializer */ 132 #define PDMA_EPWM0_CH3_TX 57UL /*!<DMA Connect to EPWM0 CH3 TX \hideinitializer */ 133 #define PDMA_EPWM0_CH4_TX 58UL /*!<DMA Connect to EPWM0 CH4 TX \hideinitializer */ 134 #define PDMA_EPWM0_CH5_TX 59UL /*!<DMA Connect to EPWM0 CH5 TX \hideinitializer */ 135 #define PDMA_EPWM1_CH0_TX 60UL /*!<DMA Connect to EPWM1 CH0 TX \hideinitializer */ 136 #define PDMA_EPWM1_CH1_TX 61UL /*!<DMA Connect to EPWM1 CH1 TX \hideinitializer */ 137 #define PDMA_EPWM1_CH2_TX 62UL /*!<DMA Connect to EPWM1 CH2 TX \hideinitializer */ 138 #define PDMA_EPWM1_CH3_TX 63UL /*!<DMA Connect to EPWM1 CH3 TX \hideinitializer */ 139 #define PDMA_EPWM1_CH4_TX 64UL /*!<DMA Connect to EPWM1 CH4 TX \hideinitializer */ 140 #define PDMA_EPWM1_CH5_TX 65UL /*!<DMA Connect to EPWM1 CH5 TX \hideinitializer */ 141 142 /*---------------------------------------------------------------------------------------------------------*/ 143 /* Interrupt Type Constant Definitions */ 144 /*---------------------------------------------------------------------------------------------------------*/ 145 #define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */ 146 #define PDMA_INT_TABLE 0x00000001UL /*!<Table Interrupt \hideinitializer */ 147 #define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */ 148 #define PDMA_INT_ALIGN 0x00000003UL /*!<Transfer Alignment Interrupt \hideinitializer */ 149 150 151 /**@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */ 152 153 /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions 154 @{ 155 */ 156 157 /** 158 * @brief Get PDMA Interrupt Status 159 * 160 * @param[in] pdma The pointer of the specified PDMA module 161 * 162 * @return None 163 * 164 * @details This macro gets the interrupt status. 165 */ 166 #define PDMA_GET_INT_STATUS(pdma) ((uint32_t)((pdma)->INTSTS)) 167 168 /** 169 * @brief Get Transfer Done Interrupt Status 170 * 171 * @param[in] pdma The pointer of the specified PDMA module 172 * 173 * @return None 174 * 175 * @details Get the transfer done Interrupt status. 176 */ 177 #define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) 178 179 /** 180 * @brief Clear Transfer Done Interrupt Status 181 * 182 * @param[in] pdma The pointer of the specified PDMA module 183 * @param[in] u32Mask The channel mask 184 * 185 * @return None 186 * 187 * @details Clear the transfer done Interrupt status. 188 */ 189 #define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) 190 191 /** 192 * @brief Get Target Abort Interrupt Status 193 * 194 * @param[in] pdma The pointer of the specified PDMA module 195 * 196 * @return None 197 * 198 * @details Get the target abort Interrupt status. 199 */ 200 #define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) 201 202 /** 203 * @brief Clear Target Abort Interrupt Status 204 * 205 * @param[in] pdma The pointer of the specified PDMA module 206 * @param[in] u32Mask The channel mask 207 * 208 * @return None 209 * 210 * @details Clear the target abort Interrupt status. 211 */ 212 #define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) 213 214 /** 215 * @brief Get PDMA Transfer Alignment Status 216 * 217 * @param[in] pdma The pointer of the specified PDMA module 218 * 219 * @return None 220 * 221 * @details Get the PDMA transfer alignment status. 222 */ 223 #define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) 224 225 /** 226 * @brief Clear PDMA Transfer Alignment Interrupt Status 227 * 228 * @param[in] pdma The pointer of the specified PDMA module 229 * @param[in] u32Mask The channel mask 230 * 231 * @return None 232 * 233 * @details Clear the PDMA transfer alignment Interrupt status. 234 */ 235 #define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) 236 237 /** 238 * @brief Clear Timeout Interrupt Status 239 * 240 * @param[in] pdma The pointer of the specified PDMA module 241 * @param[in] u32Ch The selected channel 242 * 243 * @return None 244 * 245 * @details Clear the selected channel timeout interrupt status. 246 * @note This function is only supported in channel 0 and channel 1. 247 */ 248 #define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) 249 250 /** 251 * @brief Check Channel Status 252 * 253 * @param[in] pdma The pointer of the specified PDMA module 254 * @param[in] u32Ch The selected channel 255 * 256 * @retval 0 Idle state 257 * @retval 1 Busy state 258 * 259 * @details Check the selected channel is busy or not. 260 */ 261 #define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) 262 263 /** 264 * @brief Set Source Address 265 * 266 * @param[in] pdma The pointer of the specified PDMA module 267 * @param[in] u32Ch The selected channel 268 * @param[in] u32Addr The selected address 269 * 270 * @return None 271 * 272 * @details This macro set the selected channel source address. 273 */ 274 #define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) 275 276 /** 277 * @brief Set Destination Address 278 * 279 * @param[in] pdma The pointer of the specified PDMA module 280 * @param[in] u32Ch The selected channel 281 * @param[in] u32Addr The selected address 282 * 283 * @return None 284 * 285 * @details This macro set the selected channel destination address. 286 */ 287 #define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) 288 289 /** 290 * @brief Set Transfer Count 291 * 292 * @param[in] pdma The pointer of the specified PDMA module 293 * @param[in] u32Ch The selected channel 294 * @param[in] u32TransCount Transfer Count 295 * 296 * @return None 297 * 298 * @details This macro set the selected channel transfer count. 299 */ 300 #define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) 301 302 /** 303 * @brief Set Scatter-gather descriptor Address 304 * 305 * @param[in] pdma The pointer of the specified PDMA module 306 * @param[in] u32Ch The selected channel 307 * @param[in] u32Addr The descriptor address 308 * 309 * @return None 310 * 311 * @details This macro set the selected channel scatter-gather descriptor address. 312 */ 313 #define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) 314 315 /** 316 * @brief Stop the channel 317 * 318 * @param[in] pdma The pointer of the specified PDMA module 319 * @param[in] u32Ch The selected channel 320 * 321 * @return None 322 * 323 * @details This macro stop the selected channel. 324 */ 325 #define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) 326 327 /** 328 * @brief Pause the channel 329 * 330 * @param[in] pdma The pointer of the specified PDMA module 331 * @param[in] u32Ch The selected channel 332 * 333 * @return None 334 * 335 * @details This macro pause the selected channel. 336 */ 337 #define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) 338 339 /** 340 * @brief Reset the channel 341 * 342 * @param[in] pdma The pointer of the specified PDMA module 343 * @param[in] u32Ch The selected channel 344 * 345 * @return None 346 * 347 * @details This macro reset the selected channel. 348 */ 349 #define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) 350 351 /*---------------------------------------------------------------------------------------------------------*/ 352 /* Define PWM functions prototype */ 353 /*---------------------------------------------------------------------------------------------------------*/ 354 void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); 355 void PDMA_Close(PDMA_T *pdma); 356 void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); 357 void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); 358 void PDMA_SetRepeat(PDMA_T * pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); 359 void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); 360 void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); 361 void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); 362 void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); 363 void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); 364 void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); 365 void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); 366 void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); 367 void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); 368 369 370 /**@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ 371 372 /**@}*/ /* end of group PDMA_Driver */ 373 374 /**@}*/ /* end of group Standard_Driver */ 375 376 #ifdef __cplusplus 377 } 378 #endif 379 380 #endif /* __PDMA_H__ */ 381
