1 /******************************************************************************
2 * @file spi.h
3 * @version V3.00
4 * @brief SPI driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __SPI_H__
10 #define __SPI_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup SPI_Driver SPI Driver
23 @{
24 */
25
26 /** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
27 @{
28 */
29
30 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
31 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
32 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
33 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
34
35 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
36 #define SPI_MASTER (0x0UL) /*!< Set as master */
37
38 #define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */
39 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
40 #define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */
41
42 /* SPI Interrupt Mask */
43 #define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */
44 #define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */
45 #define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */
46 #define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */
47 #define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */
48 #define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */
49 #define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */
50 #define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */
51 #define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */
52 #define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */
53
54 /* SPI Status Mask */
55 #define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask */
56 #define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */
57 #define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */
58 #define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */
59 #define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */
60 #define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */
61 #define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */
62 #define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask */
63
64 /* SPI Status2 Mask */
65 #define SPI_SLVBENUM_MASK (0x01UL) /*!< Effective bit number of uncompleted RX data status mask */
66
67
68 /* I2S Data Width */
69 #define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */
70 #define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */
71 #define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */
72 #define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */
73
74 /* I2S Audio Format */
75 #define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */
76 #define SPII2S_STEREO (0UL) /*!< Stereo channel */
77
78 /* I2S Data Format */
79 #define SPII2S_FORMAT_I2S (0UL << SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */
80 #define SPII2S_FORMAT_MSB (1UL << SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */
81 #define SPII2S_FORMAT_PCMA (2UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */
82 #define SPII2S_FORMAT_PCMB (3UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */
83
84 /* I2S Operation mode */
85 #define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */
86 #define SPII2S_MODE_MASTER (0UL) /*!< As master mode */
87
88 /* I2S TX FIFO Threshold */
89 #define SPII2S_FIFO_TX_LEVEL_WORD_0 (0UL) /*!< TX threshold is 0 word */
90 #define SPII2S_FIFO_TX_LEVEL_WORD_1 (1UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */
91 #define SPII2S_FIFO_TX_LEVEL_WORD_2 (2UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */
92 #define SPII2S_FIFO_TX_LEVEL_WORD_3 (3UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */
93 /* I2S RX FIFO Threshold */
94 #define SPII2S_FIFO_RX_LEVEL_WORD_1 (0UL) /*!< RX threshold is 1 word */
95 #define SPII2S_FIFO_RX_LEVEL_WORD_2 (1UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */
96 #define SPII2S_FIFO_RX_LEVEL_WORD_3 (2UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */
97 #define SPII2S_FIFO_RX_LEVEL_WORD_4 (3UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */
98
99 /* I2S Record Channel */
100 #define SPII2S_MONO_RIGHT (0UL) /*!< Record mono right channel */
101 #define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */
102
103 /* I2S Channel */
104 #define SPII2S_RIGHT (0UL) /*!< Select right channel */
105 #define SPII2S_LEFT (1UL) /*!< Select left channel */
106
107 /* I2S Interrupt Mask */
108 #define SPII2S_FIFO_TXTH_INT_MASK (0x01UL) /*!< TX FIFO threshold interrupt mask */
109 #define SPII2S_FIFO_RXTH_INT_MASK (0x02UL) /*!< RX FIFO threshold interrupt mask */
110 #define SPII2S_FIFO_RXOV_INT_MASK (0x04UL) /*!< RX FIFO overrun interrupt mask */
111 #define SPII2S_FIFO_RXTO_INT_MASK (0x08UL) /*!< RX FIFO time-out interrupt mask */
112 #define SPII2S_TXUF_INT_MASK (0x10UL) /*!< TX FIFO underflow interrupt mask */
113 #define SPII2S_RIGHT_ZC_INT_MASK (0x20UL) /*!< Right channel zero cross interrupt mask */
114 #define SPII2S_LEFT_ZC_INT_MASK (0x40UL) /*!< Left channel zero cross interrupt mask */
115 #define SPII2S_SLAVE_ERR_INT_MASK (0x80UL) /*!< Bit clock loss interrupt mask */
116
117 /**@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
118
119
120 /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
121 @{
122 */
123
124 /**
125 * @brief Clear the unit transfer interrupt flag.
126 * @param[in] spi The pointer of the specified SPI module.
127 * @return None.
128 * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
129 */
130 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
131
132 /**
133 * @brief Disable Slave 3-wire mode.
134 * @param[in] spi The pointer of the specified SPI module.
135 * @return None.
136 * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
137 */
138 #define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk )
139
140 /**
141 * @brief Enable Slave 3-wire mode.
142 * @param[in] spi The pointer of the specified SPI module.
143 * @return None.
144 * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
145 */
146 #define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk )
147
148 /**
149 * @brief Trigger RX PDMA function.
150 * @param[in] spi The pointer of the specified SPI module.
151 * @return None.
152 * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
153 */
154 #define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
155
156 /**
157 * @brief Trigger TX PDMA function.
158 * @param[in] spi The pointer of the specified SPI module.
159 * @return None.
160 * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
161 */
162 #define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
163
164 /**
165 * @brief Trigger TX and RX PDMA function.
166 * @param[in] spi The pointer of the specified SPI module.
167 * @return None.
168 * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
169 */
170 #define SPI_TRIGGER_TX_RX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
171
172 /**
173 * @brief Disable RX PDMA transfer.
174 * @param[in] spi The pointer of the specified SPI module.
175 * @return None.
176 * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
177 */
178 #define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
179
180 /**
181 * @brief Disable TX PDMA transfer.
182 * @param[in] spi The pointer of the specified SPI module.
183 * @return None.
184 * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
185 */
186 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
187
188 /**
189 * @brief Disable TX and RX PDMA transfer.
190 * @param[in] spi The pointer of the specified SPI module.
191 * @return None.
192 * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
193 */
194 #define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
195
196 /**
197 * @brief Get the count of available data in RX FIFO.
198 * @param[in] spi The pointer of the specified SPI module.
199 * @return The count of available data in RX FIFO.
200 * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
201 */
202 #define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos )
203
204 /**
205 * @brief Get the RX FIFO empty flag.
206 * @param[in] spi The pointer of the specified SPI module.
207 * @retval 0 RX FIFO is not empty.
208 * @retval 1 RX FIFO is empty.
209 * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
210 */
211 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos )
212
213 /**
214 * @brief Get the TX FIFO empty flag.
215 * @param[in] spi The pointer of the specified SPI module.
216 * @retval 0 TX FIFO is not empty.
217 * @retval 1 TX FIFO is empty.
218 * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
219 */
220 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos )
221
222 /**
223 * @brief Get the TX FIFO full flag.
224 * @param[in] spi The pointer of the specified SPI module.
225 * @retval 0 TX FIFO is not full.
226 * @retval 1 TX FIFO is full.
227 * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
228 */
229 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos )
230
231 /**
232 * @brief Get the datum read from RX register.
233 * @param[in] spi The pointer of the specified SPI module.
234 * @return Data in RX register.
235 * @details Read SPI_RX register to get the received datum.
236 */
237 #define SPI_READ_RX(spi) ( (spi)->RX )
238
239 /**
240 * @brief Write datum to TX register.
241 * @param[in] spi The pointer of the specified SPI module.
242 * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
243 * @return None.
244 * @details Write u32TxData to SPI_TX register.
245 */
246 #define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) )
247
248 /**
249 * @brief Set SPIx_SS pin to high state.
250 * @param[in] spi The pointer of the specified SPI module.
251 * @return None.
252 * @details Disable automatic slave selection function and set SPIx_SS pin to high state.
253 */
254 #define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) )
255
256 /**
257 * @brief Set SPIx_SS pin to low state.
258 * @param[in] spi The pointer of the specified SPI module.
259 * @return None.
260 * @details Disable automatic slave selection function and set SPIx_SS pin to low state.
261 */
262 #define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk )
263
264 /**
265 * @brief Enable Byte Reorder function.
266 * @param[in] spi The pointer of the specified SPI module.
267 * @return None.
268 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
269 */
270 #define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
271
272 /**
273 * @brief Disable Byte Reorder function.
274 * @param[in] spi The pointer of the specified SPI module.
275 * @return None.
276 * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
277 */
278 #define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
279
280 /**
281 * @brief Set the length of suspend interval.
282 * @param[in] spi The pointer of the specified SPI module.
283 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
284 * @return None.
285 * @details Set the length of suspend interval according to u32SuspCycle.
286 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
287 */
288 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) )
289
290 /**
291 * @brief Set the SPI transfer sequence with LSB first.
292 * @param[in] spi The pointer of the specified SPI module.
293 * @return None.
294 * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
295 */
296 #define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
297
298 /**
299 * @brief Set the SPI transfer sequence with MSB first.
300 * @param[in] spi The pointer of the specified SPI module.
301 * @return None.
302 * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
303 */
304 #define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
305
306 /**
307 * @brief Set the data width of a SPI transaction.
308 * @param[in] spi The pointer of the specified SPI module.
309 * @param[in] u32Width The bit width of one transaction.
310 * @return None.
311 * @details The data width can be 8 ~ 32 bits.
312 */
313 #define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) )
314
315 /**
316 * @brief Get the SPI busy state.
317 * @param[in] spi The pointer of the specified SPI module.
318 * @retval 0 SPI controller is not busy.
319 * @retval 1 SPI controller is busy.
320 * @details This macro will return the busy state of SPI controller.
321 */
322 #define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos )
323
324 /**
325 * @brief Enable SPI controller.
326 * @param[in] spi The pointer of the specified SPI module.
327 * @return None.
328 * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
329 */
330 #define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
331
332 /**
333 * @brief Disable SPI controller.
334 * @param[in] spi The pointer of the specified SPI module.
335 * @return None.
336 * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
337 */
338 #define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
339
340 /**
341 * @brief Enable zero cross detection function.
342 * @param[in] i2s The pointer of the specified I2S module.
343 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
344 * - \ref SPII2S_RIGHT
345 * - \ref SPII2S_LEFT
346 * @return None
347 * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
348 */
SPII2S_ENABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)349 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
350 {
351 if(u32ChMask == SPII2S_RIGHT)
352 {
353 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
354 }
355 else
356 {
357 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
358 }
359 }
360
361 /**
362 * @brief Disable zero cross detection function.
363 * @param[in] i2s The pointer of the specified I2S module.
364 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
365 * - \ref SPII2S_RIGHT
366 * - \ref SPII2S_LEFT
367 * @return None
368 * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
369 */
SPII2S_DISABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)370 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
371 {
372 if(u32ChMask == SPII2S_RIGHT)
373 {
374 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
375 }
376 else
377 {
378 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
379 }
380 }
381
382 /**
383 * @brief Enable I2S TX DMA function.
384 * @param[in] i2s The pointer of the specified I2S module.
385 * @return None
386 * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
387 */
388 #define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
389
390 /**
391 * @brief Disable I2S TX DMA function.
392 * @param[in] i2s The pointer of the specified I2S module.
393 * @return None
394 * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
395 */
396 #define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
397
398 /**
399 * @brief Enable I2S RX DMA function.
400 * @param[in] i2s The pointer of the specified I2S module.
401 * @return None
402 * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
403 */
404 #define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
405
406 /**
407 * @brief Disable I2S RX DMA function.
408 * @param[in] i2s The pointer of the specified I2S module.
409 * @return None
410 * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
411 */
412 #define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
413
414 /**
415 * @brief Enable I2S TX function.
416 * @param[in] i2s The pointer of the specified I2S module.
417 * @return None
418 * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
419 */
420 #define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
421
422 /**
423 * @brief Disable I2S TX function.
424 * @param[in] i2s The pointer of the specified I2S module.
425 * @return None
426 * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
427 */
428 #define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
429
430 /**
431 * @brief Enable I2S RX function.
432 * @param[in] i2s The pointer of the specified I2S module.
433 * @return None
434 * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
435 */
436 #define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
437
438 /**
439 * @brief Disable I2S RX function.
440 * @param[in] i2s The pointer of the specified I2S module.
441 * @return None
442 * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
443 */
444 #define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
445
446 /**
447 * @brief Enable TX Mute function.
448 * @param[in] i2s The pointer of the specified I2S module.
449 * @return None
450 * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
451 */
452 #define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
453
454 /**
455 * @brief Disable TX Mute function.
456 * @param[in] i2s The pointer of the specified I2S module.
457 * @return None
458 * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
459 */
460 #define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
461
462 /**
463 * @brief Clear TX FIFO.
464 * @param[in] i2s The pointer of the specified I2S module.
465 * @return None
466 * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
467 */
468 #define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
469
470 /**
471 * @brief Clear RX FIFO.
472 * @param[in] i2s The pointer of the specified I2S module.
473 * @return None
474 * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
475 */
476 #define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
477
478 /**
479 * @brief This function sets the recording source channel when mono mode is used.
480 * @param[in] i2s The pointer of the specified I2S module.
481 * @param[in] u32Ch left or right channel. Valid values are:
482 * - \ref SPII2S_MONO_LEFT
483 * - \ref SPII2S_MONO_RIGHT
484 * @return None
485 * @details This function selects the recording source channel of monaural mode.
486 */
SPII2S_SET_MONO_RX_CHANNEL(SPI_T * i2s,uint32_t u32Ch)487 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
488 {
489 u32Ch == SPII2S_MONO_LEFT ?
490 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
491 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
492 }
493
494 /**
495 * @brief Write data to I2S TX FIFO.
496 * @param[in] i2s The pointer of the specified I2S module.
497 * @param[in] u32Data The value written to TX FIFO.
498 * @return None
499 * @details This macro will write a value to TX FIFO.
500 */
501 #define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
502
503 /**
504 * @brief Read RX FIFO.
505 * @param[in] i2s The pointer of the specified I2S module.
506 * @return The value read from RX FIFO.
507 * @details This function will return a value read from RX FIFO.
508 */
509 #define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
510
511 /**
512 * @brief Get the interrupt flag.
513 * @param[in] i2s The pointer of the specified I2S module.
514 * @param[in] u32Mask The mask value for all interrupt flags.
515 * @return The interrupt flags specified by the u32mask parameter.
516 * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
517 */
518 #define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
519
520 /**
521 * @brief Clear the interrupt flag.
522 * @param[in] i2s The pointer of the specified I2S module.
523 * @param[in] u32Mask The mask value for all interrupt flags.
524 * @return None
525 * @details This macro will clear the interrupt flags specified by the u32mask parameter.
526 * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
527 */
528 #define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
529
530 /**
531 * @brief Get transmit FIFO level
532 * @param[in] i2s The pointer of the specified I2S module.
533 * @return TX FIFO level
534 * @details This macro will return the number of available words in TX FIFO.
535 */
536 #define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
537
538 /**
539 * @brief Get receive FIFO level
540 * @param[in] i2s The pointer of the specified I2S module.
541 * @return RX FIFO level
542 * @details This macro will return the number of available words in RX FIFO.
543 */
544 #define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
545
546 /* Function prototype declaration */
547 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
548 void SPI_Close(SPI_T *spi);
549 void SPI_ClearRxFIFO(SPI_T *spi);
550 void SPI_ClearTxFIFO(SPI_T *spi);
551 void SPI_DisableAutoSS(SPI_T *spi);
552 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
553 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
554 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
555 uint32_t SPI_GetBusClock(SPI_T *spi);
556 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
557 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
558 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
559 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
560 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
561 uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask);
562
563 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
564 void SPII2S_Close(SPI_T *i2s);
565 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
566 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
567 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
568 void SPII2S_DisableMCLK(SPI_T *i2s);
569 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
570
571
572 /**@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
573
574 /**@}*/ /* end of group SPI_Driver */
575
576 /**@}*/ /* end of group Standard_Driver */
577
578 #ifdef __cplusplus
579 }
580 #endif
581
582 #endif /* __SPI_H__ */
583
