1 /* 2 * Copyright (c) 2018-2020 ARM Limited 3 * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef __TARGET_CFG_H__ 19 #define __TARGET_CFG_H__ 20 21 #include "uart_stdout.h" 22 #include "tfm_peripherals_def.h" 23 24 #define TFM_DRIVER_STDIO Driver_USART5 25 #define NS_DRIVER_STDIO Driver_USART5 26 27 /* UART pins HSIOM routing */ 28 #define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX 29 #define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX 30 31 /* UART pins configuration */ 32 #define CYBSP_UART_RX_ENABLED 1U 33 #define CYBSP_UART_RX_PORT GPIO_PRT5 34 #define CYBSP_UART_RX_PORT_NUM 5U 35 #define CYBSP_UART_RX_PIN 0U 36 #define CYBSP_UART_RX_NUM 0U 37 #define CYBSP_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ 38 #define CYBSP_UART_RX_INIT_DRIVESTATE 1 39 #ifndef ioss_0_port_5_pin_0_HSIOM 40 #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO 41 #endif 42 #define CYBSP_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM 43 #define CYBSP_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn 44 #define CYBSP_UART_TX_ENABLED 1U 45 #define CYBSP_UART_TX_PORT GPIO_PRT5 46 #define CYBSP_UART_TX_PORT_NUM 5U 47 #define CYBSP_UART_TX_PIN 1U 48 #define CYBSP_UART_TX_NUM 1U 49 #define CYBSP_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF 50 #define CYBSP_UART_TX_INIT_DRIVESTATE 1 51 #ifndef ioss_0_port_5_pin_1_HSIOM 52 #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO 53 #endif 54 #define CYBSP_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM 55 #define CYBSP_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn 56 57 /** 58 * \brief Store the addresses of memory regions 59 */ 60 struct memory_region_limits { 61 uint32_t non_secure_code_start; 62 uint32_t non_secure_partition_base; 63 uint32_t non_secure_partition_limit; 64 }; 65 66 /** 67 * \brief Holds the data necessary to do isolation for a specific peripheral. 68 */ 69 struct platform_data_t 70 { 71 uint32_t periph_start; 72 uint32_t periph_limit; 73 int16_t periph_ppc_bank; 74 int16_t periph_ppc_loc; 75 }; 76 77 /** 78 * \brief Configures the Shared Memory Protection Units. 79 * 80 * \return Returns values as specified by the \ref enum tfm_plat_err_t 81 */ 82 enum tfm_plat_err_t smpu_init_cfg(void); 83 84 /** 85 * \brief Prints out the Shared Memory Protection Units config. 86 */ 87 void smpu_print_config(void); 88 89 /** 90 * \brief Configures the Peripheral Protection Units. 91 * 92 * \return Returns values as specified by the \ref enum tfm_plat_err_t 93 */ 94 enum tfm_plat_err_t ppu_init_cfg(void); 95 96 /** 97 * \brief Configure bus masters/Protectoin Contexts. 98 * 99 * \return Returns values as specified by the \ref enum tfm_plat_err_t 100 */ 101 enum tfm_plat_err_t bus_masters_cfg(void); 102 103 /** 104 * \brief Performs platform specific hw initialization. 105 */ 106 void platform_init(void); 107 108 /** 109 * \brief Configures all external interrupts to target the 110 * NS state, apart for the ones associated to secure 111 * peripherals. 112 * 113 * \return Returns values as specified by the \ref tfm_plat_err_t 114 */ 115 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 116 117 /** 118 * \brief This function enable the interrupts associated 119 * to the secure peripherals (plus the isolation boundary violation 120 * interrupts) 121 * 122 * \return Returns values as specified by the \ref tfm_plat_err_t 123 */ 124 enum tfm_plat_err_t nvic_interrupt_enable(void); 125 126 #endif /* __TARGET_CFG_H__ */ 127
