1 /* 2 * Copyright (c) 2017-2021 Arm Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __TARGET_CFG_H__ 18 #define __TARGET_CFG_H__ 19 20 #include "uart_stdout.h" 21 #include "tfm_peripherals_def.h" 22 #include "tfm_plat_defs.h" 23 #include "arm_uart_drv.h" 24 #include "fih.h" 25 26 #define TFM_DRIVER_STDIO Driver_USART0 27 #define NS_DRIVER_STDIO Driver_USART0 28 #define ERPC_UART Driver_USART1 29 30 /** 31 * \brief Defines the word offsets of Slave Peripheral Protection Controller 32 * Registers 33 */ 34 enum ppc_bank_e 35 { 36 PPC_SP_DO_NOT_CONFIGURE = -1, 37 PPC_SP_AHB_PPC0 = 0, 38 PPC_SP_RES0, 39 PPC_SP_RES1, 40 PPC_SP_RES2, 41 PPC_SP_AHB_PPC_EXP0, 42 PPC_SP_AHB_PPC_EXP1, 43 PPC_SP_AHB_PPC_EXP2, 44 PPC_SP_AHB_PPC_EXP3, 45 PPC_SP_APB_PPC0, 46 PPC_SP_APB_PPC1, 47 PPC_SP_RES3, 48 PPC_SP_RES4, 49 PPC_SP_APB_PPC_EXP0, 50 PPC_SP_APB_PPC_EXP1, 51 PPC_SP_APB_PPC_EXP2, 52 PPC_SP_APB_PPC_EXP3, 53 }; 54 55 /** 56 * \brief Store the addresses of memory regions 57 */ 58 struct memory_region_limits { 59 uint32_t non_secure_code_start; 60 uint32_t non_secure_partition_base; 61 uint32_t non_secure_partition_limit; 62 uint32_t veneer_base; 63 uint32_t veneer_limit; 64 #ifdef BL2 65 uint32_t secondary_partition_base; 66 uint32_t secondary_partition_limit; 67 #endif /* BL2 */ 68 }; 69 70 /** 71 * \brief Holds the data necessary to do isolation for a specific peripheral. 72 */ 73 struct platform_data_t 74 { 75 uint32_t periph_start; 76 uint32_t periph_limit; 77 enum ppc_bank_e periph_ppc_bank; 78 int16_t periph_ppc_loc; 79 }; 80 81 /** 82 * \brief Configures the Memory Protection Controller. 83 * 84 * \return Returns error code. 85 */ 86 FIH_RET_TYPE(int32_t) mpc_init_cfg(void); 87 88 /** 89 * \brief Configures the Peripheral Protection Controller. 90 */ 91 FIH_RET_TYPE(int32_t) ppc_init_cfg(void); 92 93 /** 94 * \brief Restict access to peripheral to secure 95 */ 96 FIH_RET_TYPE(int32_t) ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t loc); 97 98 /** 99 * \brief Allow non-secure access to peripheral 100 */ 101 void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc); 102 103 /** 104 * \brief Enable secure unprivileged access to peripheral 105 */ 106 FIH_RET_TYPE(int32_t) ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos); 107 108 /** 109 * \brief Clear secure unprivileged access to peripheral 110 */ 111 FIH_RET_TYPE(int32_t) ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos); 112 113 /** 114 * \brief Clears PPC interrupt. 115 */ 116 void ppc_clear_irq(void); 117 118 /** 119 * \brief Configures SAU and IDAU. 120 */ 121 FIH_RET_TYPE(int32_t) sau_and_idau_cfg(void); 122 123 /** 124 * \brief Enables the fault handlers and sets priorities. 125 * 126 * \return Returns values as specified by the \ref tfm_plat_err_t 127 */ 128 enum tfm_plat_err_t enable_fault_handlers(void); 129 130 /** 131 * \brief Configures the system reset request properties 132 * 133 * \return Returns values as specified by the \ref tfm_plat_err_t 134 */ 135 enum tfm_plat_err_t system_reset_cfg(void); 136 137 /** 138 * \brief Configures the system debug properties. 139 * 140 * \return Returns values as specified by the \ref tfm_plat_err_t 141 */ 142 FIH_RET_TYPE(enum tfm_plat_err_t) init_debug(void); 143 144 /** 145 * \brief Configures all external interrupts to target the 146 * NS state, apart for the ones associated to secure 147 * peripherals (plus MPC and PPC) 148 * 149 * \return Returns values as specified by the \ref tfm_plat_err_t 150 */ 151 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 152 153 /** 154 * \brief This function enable the interrupts associated 155 * to the secure peripherals (plus the isolation boundary violation 156 * interrupts) 157 * 158 * \return Returns values as specified by the \ref tfm_plat_err_t 159 */ 160 enum tfm_plat_err_t nvic_interrupt_enable(void); 161 162 /* Function for FIH to verify that SAU & IDAU are correctly configured. */ 163 fih_int fih_verify_sau_and_idau_cfg(void); 164 165 /* Function for FIH to verify that MPC is correctly configured. */ 166 fih_int fih_verify_mpc_cfg(void); 167 168 /* Function for FIH to verify that PPC is correctly configured. */ 169 fih_int fih_verify_ppc_cfg(void); 170 171 #endif /* __TARGET_CFG_H__ */ 172
