1<table align="center" frame="border" rules="cols" border="1"> 2 <tr> 3 <td valign="top"> created by : </td> 4 </tr> 5 <tr> 6 <td valign="top"> generated by : yoesha01</td> 7 </tr> 8 <tr> 9 <td valign="top"> generated from : /home/hw/yoesha01/P4/cc_7/cc312_cerberus/env/src/regs/XL/regdb_iot.xlsx</td> 10 </tr> 11 <tr> 12 <td valign="top"> IDesignSpec rev : idsbatch v 4.12.19.1 </td> 13 </tr> 14 <tr> 15 <td valign="top"> XML Revision : </td> 16 </tr> 17</table> 18<center> 19 <h1>chip : CryptoCell</h1> 20</center> 21<table border="0"> 22 <tr> 23 <td width="40"></td> 24 <td> 25 <table frame="border"> 26 <tr> 27 <td align="center" colspan="3"><b>LEGEND</b></td> 28 </tr> 29 <tr> 30 <td colspan="3"><b>RO : Read Only </b></td> 31 </tr> 32 <tr> 33 <td colspan="3"><b>WO : Write Only </b></td> 34 </tr> 35 <tr> 36 <td colspan="3"><b>RW : Read/Write </b></td> 37 </tr> 38 <tr> 39 <td colspan="3"><b>RW1: Read/Write once </b></td> 40 </tr> 41 <tr> 42 <td colspan="3"><b>W1 : Write once </b></td> 43 </tr> 44 <tr> 45 <td colspan="3"><b>RWC: Read/Write change (Register value changes internally) </b></td> 46 </tr> 47 <tr> 48 <td colspan="3"><b>RC : Read Change (Readable, register valus changes) </b></td> 49 </tr> 50 <tr> 51 <td colspan="3"><b>WM : Write Modify (Write triggers an internal FSM) </b></td> 52 </tr> 53 </table> 54 </td> 55 </tr> 56</table> 57<table border="0"> 58 <tr> 59 <td width="40"></td> 60 <td> 61 <table frame="border"> 62 <tr> 63 <td align="center" colspan="3"><b>INDEX</b></td> 64 </tr> 65 <tr> 66 <td width="100">1.1</td> 67 <td>block: <a href="#1.1">PKA</a></td> 68 <td width="60"></td> 69 <td>0x000000000</td> 70 </tr> 71 <tr> 72 <td width="100">1.1.1</td> 73 <td>reg: <a href="#1.1.1">MEMORY_MAP0</a></td> 74 <td width="60"></td> 75 <td>0x000000000</td> 76 </tr> 77 <tr> 78 <td width="100">1.1.2</td> 79 <td>reg: <a href="#1.1.2">MEMORY_MAP1</a></td> 80 <td width="60"></td> 81 <td>0x000000004</td> 82 </tr> 83 <tr> 84 <td width="100">1.1.3</td> 85 <td>reg: <a href="#1.1.3">MEMORY_MAP2</a></td> 86 <td width="60"></td> 87 <td>0x000000008</td> 88 </tr> 89 <tr> 90 <td width="100">1.1.4</td> 91 <td>reg: <a href="#1.1.4">MEMORY_MAP3</a></td> 92 <td width="60"></td> 93 <td>0x00000000C</td> 94 </tr> 95 <tr> 96 <td width="100">1.1.5</td> 97 <td>reg: <a href="#1.1.5">MEMORY_MAP4</a></td> 98 <td width="60"></td> 99 <td>0x000000010</td> 100 </tr> 101 <tr> 102 <td width="100">1.1.6</td> 103 <td>reg: <a href="#1.1.6">MEMORY_MAP5</a></td> 104 <td width="60"></td> 105 <td>0x000000014</td> 106 </tr> 107 <tr> 108 <td width="100">1.1.7</td> 109 <td>reg: <a href="#1.1.7">MEMORY_MAP6</a></td> 110 <td width="60"></td> 111 <td>0x000000018</td> 112 </tr> 113 <tr> 114 <td width="100">1.1.8</td> 115 <td>reg: <a href="#1.1.8">MEMORY_MAP7</a></td> 116 <td width="60"></td> 117 <td>0x00000001C</td> 118 </tr> 119 <tr> 120 <td width="100">1.1.9</td> 121 <td>reg: <a href="#1.1.9">MEMORY_MAP8</a></td> 122 <td width="60"></td> 123 <td>0x000000020</td> 124 </tr> 125 <tr> 126 <td width="100">1.1.10</td> 127 <td>reg: <a href="#1.1.10">MEMORY_MAP9</a></td> 128 <td width="60"></td> 129 <td>0x000000024</td> 130 </tr> 131 <tr> 132 <td width="100">1.1.11</td> 133 <td>reg: <a href="#1.1.11">MEMORY_MAP10</a></td> 134 <td width="60"></td> 135 <td>0x000000028</td> 136 </tr> 137 <tr> 138 <td width="100">1.1.12</td> 139 <td>reg: <a href="#1.1.12">MEMORY_MAP11</a></td> 140 <td width="60"></td> 141 <td>0x00000002C</td> 142 </tr> 143 <tr> 144 <td width="100">1.1.13</td> 145 <td>reg: <a href="#1.1.13">MEMORY_MAP12</a></td> 146 <td width="60"></td> 147 <td>0x000000030</td> 148 </tr> 149 <tr> 150 <td width="100">1.1.14</td> 151 <td>reg: <a href="#1.1.14">MEMORY_MAP13</a></td> 152 <td width="60"></td> 153 <td>0x000000034</td> 154 </tr> 155 <tr> 156 <td width="100">1.1.15</td> 157 <td>reg: <a href="#1.1.15">MEMORY_MAP14</a></td> 158 <td width="60"></td> 159 <td>0x000000038</td> 160 </tr> 161 <tr> 162 <td width="100">1.1.16</td> 163 <td>reg: <a href="#1.1.16">MEMORY_MAP15</a></td> 164 <td width="60"></td> 165 <td>0x00000003C</td> 166 </tr> 167 <tr> 168 <td width="100">1.1.17</td> 169 <td>reg: <a href="#1.1.17">MEMORY_MAP16</a></td> 170 <td width="60"></td> 171 <td>0x000000040</td> 172 </tr> 173 <tr> 174 <td width="100">1.1.18</td> 175 <td>reg: <a href="#1.1.18">MEMORY_MAP17</a></td> 176 <td width="60"></td> 177 <td>0x000000044</td> 178 </tr> 179 <tr> 180 <td width="100">1.1.19</td> 181 <td>reg: <a href="#1.1.19">MEMORY_MAP18</a></td> 182 <td width="60"></td> 183 <td>0x000000048</td> 184 </tr> 185 <tr> 186 <td width="100">1.1.20</td> 187 <td>reg: <a href="#1.1.20">MEMORY_MAP19</a></td> 188 <td width="60"></td> 189 <td>0x00000004C</td> 190 </tr> 191 <tr> 192 <td width="100">1.1.21</td> 193 <td>reg: <a href="#1.1.21">MEMORY_MAP20</a></td> 194 <td width="60"></td> 195 <td>0x000000050</td> 196 </tr> 197 <tr> 198 <td width="100">1.1.22</td> 199 <td>reg: <a href="#1.1.22">MEMORY_MAP21</a></td> 200 <td width="60"></td> 201 <td>0x000000054</td> 202 </tr> 203 <tr> 204 <td width="100">1.1.23</td> 205 <td>reg: <a href="#1.1.23">MEMORY_MAP22</a></td> 206 <td width="60"></td> 207 <td>0x000000058</td> 208 </tr> 209 <tr> 210 <td width="100">1.1.24</td> 211 <td>reg: <a href="#1.1.24">MEMORY_MAP23</a></td> 212 <td width="60"></td> 213 <td>0x00000005C</td> 214 </tr> 215 <tr> 216 <td width="100">1.1.25</td> 217 <td>reg: <a href="#1.1.25">MEMORY_MAP24</a></td> 218 <td width="60"></td> 219 <td>0x000000060</td> 220 </tr> 221 <tr> 222 <td width="100">1.1.26</td> 223 <td>reg: <a href="#1.1.26">MEMORY_MAP25</a></td> 224 <td width="60"></td> 225 <td>0x000000064</td> 226 </tr> 227 <tr> 228 <td width="100">1.1.27</td> 229 <td>reg: <a href="#1.1.27">MEMORY_MAP26</a></td> 230 <td width="60"></td> 231 <td>0x000000068</td> 232 </tr> 233 <tr> 234 <td width="100">1.1.28</td> 235 <td>reg: <a href="#1.1.28">MEMORY_MAP27</a></td> 236 <td width="60"></td> 237 <td>0x00000006C</td> 238 </tr> 239 <tr> 240 <td width="100">1.1.29</td> 241 <td>reg: <a href="#1.1.29">MEMORY_MAP28</a></td> 242 <td width="60"></td> 243 <td>0x000000070</td> 244 </tr> 245 <tr> 246 <td width="100">1.1.30</td> 247 <td>reg: <a href="#1.1.30">MEMORY_MAP29</a></td> 248 <td width="60"></td> 249 <td>0x000000074</td> 250 </tr> 251 <tr> 252 <td width="100">1.1.31</td> 253 <td>reg: <a href="#1.1.31">MEMORY_MAP30</a></td> 254 <td width="60"></td> 255 <td>0x000000078</td> 256 </tr> 257 <tr> 258 <td width="100">1.1.32</td> 259 <td>reg: <a href="#1.1.32">MEMORY_MAP31</a></td> 260 <td width="60"></td> 261 <td>0x00000007C</td> 262 </tr> 263 <tr> 264 <td width="100">1.1.33</td> 265 <td>reg: <a href="#1.1.33">OPCODE</a></td> 266 <td width="60"></td> 267 <td>0x000000080</td> 268 </tr> 269 <tr> 270 <td width="100">1.1.34</td> 271 <td>reg: <a href="#1.1.34">N_NP_T0_T1_ADDR</a></td> 272 <td width="60"></td> 273 <td>0x000000084</td> 274 </tr> 275 <tr> 276 <td width="100">1.1.35</td> 277 <td>reg: <a href="#1.1.35">PKA_STATUS</a></td> 278 <td width="60"></td> 279 <td>0x000000088</td> 280 </tr> 281 <tr> 282 <td width="100">1.1.36</td> 283 <td>reg: <a href="#1.1.36">PKA_SW_RESET</a></td> 284 <td width="60"></td> 285 <td>0x00000008C</td> 286 </tr> 287 <tr> 288 <td width="100">1.1.37</td> 289 <td>reg: <a href="#1.1.37">PKA_L0</a></td> 290 <td width="60"></td> 291 <td>0x000000090</td> 292 </tr> 293 <tr> 294 <td width="100">1.1.38</td> 295 <td>reg: <a href="#1.1.38">PKA_L1</a></td> 296 <td width="60"></td> 297 <td>0x000000094</td> 298 </tr> 299 <tr> 300 <td width="100">1.1.39</td> 301 <td>reg: <a href="#1.1.39">PKA_L2</a></td> 302 <td width="60"></td> 303 <td>0x000000098</td> 304 </tr> 305 <tr> 306 <td width="100">1.1.40</td> 307 <td>reg: <a href="#1.1.40">PKA_L3</a></td> 308 <td width="60"></td> 309 <td>0x00000009C</td> 310 </tr> 311 <tr> 312 <td width="100">1.1.41</td> 313 <td>reg: <a href="#1.1.41">PKA_L4</a></td> 314 <td width="60"></td> 315 <td>0x0000000A0</td> 316 </tr> 317 <tr> 318 <td width="100">1.1.42</td> 319 <td>reg: <a href="#1.1.42">PKA_L5</a></td> 320 <td width="60"></td> 321 <td>0x0000000A4</td> 322 </tr> 323 <tr> 324 <td width="100">1.1.43</td> 325 <td>reg: <a href="#1.1.43">PKA_L6</a></td> 326 <td width="60"></td> 327 <td>0x0000000A8</td> 328 </tr> 329 <tr> 330 <td width="100">1.1.44</td> 331 <td>reg: <a href="#1.1.44">PKA_L7</a></td> 332 <td width="60"></td> 333 <td>0x0000000AC</td> 334 </tr> 335 <tr> 336 <td width="100">1.1.45</td> 337 <td>reg: <a href="#1.1.45">PKA_PIPE_RDY</a></td> 338 <td width="60"></td> 339 <td>0x0000000B0</td> 340 </tr> 341 <tr> 342 <td width="100">1.1.46</td> 343 <td>reg: <a href="#1.1.46">PKA_DONE</a></td> 344 <td width="60"></td> 345 <td>0x0000000B4</td> 346 </tr> 347 <tr> 348 <td width="100">1.1.47</td> 349 <td>reg: <a href="#1.1.47">PKA_MON_SELECT</a></td> 350 <td width="60"></td> 351 <td>0x0000000B8</td> 352 </tr> 353 <tr> 354 <td width="100">1.1.48</td> 355 <td>reg: <a href="#1.1.48">PKA_VERSION</a></td> 356 <td width="60"></td> 357 <td>0x0000000C4</td> 358 </tr> 359 <tr> 360 <td width="100">1.1.49</td> 361 <td>reg: <a href="#1.1.49">PKA_MON_READ</a></td> 362 <td width="60"></td> 363 <td>0x0000000D0</td> 364 </tr> 365 <tr> 366 <td width="100">1.1.50</td> 367 <td>reg: <a href="#1.1.50">PKA_SRAM_ADDR</a></td> 368 <td width="60"></td> 369 <td>0x0000000D4</td> 370 </tr> 371 <tr> 372 <td width="100">1.1.51</td> 373 <td>reg: <a href="#1.1.51">PKA_SRAM_WDATA</a></td> 374 <td width="60"></td> 375 <td>0x0000000D8</td> 376 </tr> 377 <tr> 378 <td width="100">1.1.52</td> 379 <td>reg: <a href="#1.1.52">PKA_SRAM_RDATA</a></td> 380 <td width="60"></td> 381 <td>0x0000000DC</td> 382 </tr> 383 <tr> 384 <td width="100">1.1.53</td> 385 <td>reg: <a href="#1.1.53">PKA_SRAM_WR_CLR</a></td> 386 <td width="60"></td> 387 <td>0x0000000E0</td> 388 </tr> 389 <tr> 390 <td width="100">1.1.54</td> 391 <td>reg: <a href="#1.1.54">PKA_SRAM_RADDR</a></td> 392 <td width="60"></td> 393 <td>0x0000000E4</td> 394 </tr> 395 <tr> 396 <td width="100">1.1.55</td> 397 <td>reg: <a href="#1.1.55">PKA_WORD_ACCESS</a></td> 398 <td width="60"></td> 399 <td>0x0000000F0</td> 400 </tr> 401 <tr> 402 <td width="100">1.1.56</td> 403 <td>reg: <a href="#1.1.56">PKA_BUFF_ADDR</a></td> 404 <td width="60"></td> 405 <td>0x0000000F8</td> 406 </tr> 407 <tr> 408 <td width="100">1.2</td> 409 <td>block: <a href="#1.2">RNG</a></td> 410 <td width="60"></td> 411 <td>0x000000100</td> 412 </tr> 413 <tr> 414 <td width="100">1.2.1</td> 415 <td>reg: <a href="#1.2.1">RNG_IMR</a></td> 416 <td width="60"></td> 417 <td>0x000000100</td> 418 </tr> 419 <tr> 420 <td width="100">1.2.2</td> 421 <td>reg: <a href="#1.2.2">RNG_ISR</a></td> 422 <td width="60"></td> 423 <td>0x000000104</td> 424 </tr> 425 <tr> 426 <td width="100">1.2.3</td> 427 <td>reg: <a href="#1.2.3">RNG_ICR</a></td> 428 <td width="60"></td> 429 <td>0x000000108</td> 430 </tr> 431 <tr> 432 <td width="100">1.2.4</td> 433 <td>reg: <a href="#1.2.4">TRNG_CONFIG</a></td> 434 <td width="60"></td> 435 <td>0x00000010C</td> 436 </tr> 437 <tr> 438 <td width="100">1.2.5</td> 439 <td>reg: <a href="#1.2.5">TRNG_VALID</a></td> 440 <td width="60"></td> 441 <td>0x000000110</td> 442 </tr> 443 <tr> 444 <td width="100">1.2.6</td> 445 <td>reg: <a href="#1.2.6">EHR_DATA_0</a></td> 446 <td width="60"></td> 447 <td>0x000000114</td> 448 </tr> 449 <tr> 450 <td width="100">1.2.7</td> 451 <td>reg: <a href="#1.2.7">EHR_DATA_1</a></td> 452 <td width="60"></td> 453 <td>0x000000118</td> 454 </tr> 455 <tr> 456 <td width="100">1.2.8</td> 457 <td>reg: <a href="#1.2.8">EHR_DATA_2</a></td> 458 <td width="60"></td> 459 <td>0x00000011C</td> 460 </tr> 461 <tr> 462 <td width="100">1.2.9</td> 463 <td>reg: <a href="#1.2.9">EHR_DATA_3</a></td> 464 <td width="60"></td> 465 <td>0x000000120</td> 466 </tr> 467 <tr> 468 <td width="100">1.2.10</td> 469 <td>reg: <a href="#1.2.10">EHR_DATA_4</a></td> 470 <td width="60"></td> 471 <td>0x000000124</td> 472 </tr> 473 <tr> 474 <td width="100">1.2.11</td> 475 <td>reg: <a href="#1.2.11">EHR_DATA_5</a></td> 476 <td width="60"></td> 477 <td>0x000000128</td> 478 </tr> 479 <tr> 480 <td width="100">1.2.12</td> 481 <td>reg: <a href="#1.2.12">RND_SOURCE_ENABLE</a></td> 482 <td width="60"></td> 483 <td>0x00000012C</td> 484 </tr> 485 <tr> 486 <td width="100">1.2.13</td> 487 <td>reg: <a href="#1.2.13">SAMPLE_CNT1</a></td> 488 <td width="60"></td> 489 <td>0x000000130</td> 490 </tr> 491 <tr> 492 <td width="100">1.2.14</td> 493 <td>reg: <a href="#1.2.14">AUTOCORR_STATISTIC</a></td> 494 <td width="60"></td> 495 <td>0x000000134</td> 496 </tr> 497 <tr> 498 <td width="100">1.2.15</td> 499 <td>reg: <a href="#1.2.15">TRNG_DEBUG_CONTROL</a></td> 500 <td width="60"></td> 501 <td>0x000000138</td> 502 </tr> 503 <tr> 504 <td width="100">1.2.16</td> 505 <td>reg: <a href="#1.2.16">RNG_SW_RESET</a></td> 506 <td width="60"></td> 507 <td>0x000000140</td> 508 </tr> 509 <tr> 510 <td width="100">1.2.17</td> 511 <td>reg: <a href="#1.2.17">RNG_DEBUG_EN_INPUT</a></td> 512 <td width="60"></td> 513 <td>0x0000001B4</td> 514 </tr> 515 <tr> 516 <td width="100">1.2.18</td> 517 <td>reg: <a href="#1.2.18">RNG_BUSY</a></td> 518 <td width="60"></td> 519 <td>0x0000001B8</td> 520 </tr> 521 <tr> 522 <td width="100">1.2.19</td> 523 <td>reg: <a href="#1.2.19">RST_BITS_COUNTER</a></td> 524 <td width="60"></td> 525 <td>0x0000001BC</td> 526 </tr> 527 <tr> 528 <td width="100">1.2.20</td> 529 <td>reg: <a href="#1.2.20">RNG_VERSION</a></td> 530 <td width="60"></td> 531 <td>0x0000001C0</td> 532 </tr> 533 <tr> 534 <td width="100">1.2.21</td> 535 <td>reg: <a href="#1.2.21">RNG_CLK_ENABLE</a></td> 536 <td width="60"></td> 537 <td>0x0000001C4</td> 538 </tr> 539 <tr> 540 <td width="100">1.2.22</td> 541 <td>reg: <a href="#1.2.22">RNG_DMA_ENABLE</a></td> 542 <td width="60"></td> 543 <td>0x0000001C8</td> 544 </tr> 545 <tr> 546 <td width="100">1.2.23</td> 547 <td>reg: <a href="#1.2.23">RNG_DMA_SRC_MASK</a></td> 548 <td width="60"></td> 549 <td>0x0000001CC</td> 550 </tr> 551 <tr> 552 <td width="100">1.2.24</td> 553 <td>reg: <a href="#1.2.24">RNG_DMA_SRAM_ADDR</a></td> 554 <td width="60"></td> 555 <td>0x0000001D0</td> 556 </tr> 557 <tr> 558 <td width="100">1.2.25</td> 559 <td>reg: <a href="#1.2.25">RNG_DMA_SAMPLES_NUM</a></td> 560 <td width="60"></td> 561 <td>0x0000001D4</td> 562 </tr> 563 <tr> 564 <td width="100">1.2.26</td> 565 <td>reg: <a href="#1.2.26">RNG_WATCHDOG_VAL</a></td> 566 <td width="60"></td> 567 <td>0x0000001D8</td> 568 </tr> 569 <tr> 570 <td width="100">1.2.27</td> 571 <td>reg: <a href="#1.2.27">RNG_DMA_STATUS</a></td> 572 <td width="60"></td> 573 <td>0x0000001DC</td> 574 </tr> 575 <tr> 576 <td width="100">1.3</td> 577 <td>block: <a href="#1.3">CHACHA</a></td> 578 <td width="60"></td> 579 <td>0x000000380</td> 580 </tr> 581 <tr> 582 <td width="100">1.3.1</td> 583 <td>reg: <a href="#1.3.1">CHACHA_CONTROL_REG</a></td> 584 <td width="60"></td> 585 <td>0x000000380</td> 586 </tr> 587 <tr> 588 <td width="100">1.3.2</td> 589 <td>reg: <a href="#1.3.2">CHACHA_VERSION</a></td> 590 <td width="60"></td> 591 <td>0x000000384</td> 592 </tr> 593 <tr> 594 <td width="100">1.3.3</td> 595 <td>reg: <a href="#1.3.3">CHACHA_KEY0</a></td> 596 <td width="60"></td> 597 <td>0x000000388</td> 598 </tr> 599 <tr> 600 <td width="100">1.3.4</td> 601 <td>reg: <a href="#1.3.4">CHACHA_KEY1</a></td> 602 <td width="60"></td> 603 <td>0x00000038C</td> 604 </tr> 605 <tr> 606 <td width="100">1.3.5</td> 607 <td>reg: <a href="#1.3.5">CHACHA_KEY2</a></td> 608 <td width="60"></td> 609 <td>0x000000390</td> 610 </tr> 611 <tr> 612 <td width="100">1.3.6</td> 613 <td>reg: <a href="#1.3.6">CHACHA_KEY3</a></td> 614 <td width="60"></td> 615 <td>0x000000394</td> 616 </tr> 617 <tr> 618 <td width="100">1.3.7</td> 619 <td>reg: <a href="#1.3.7">CHACHA_KEY4</a></td> 620 <td width="60"></td> 621 <td>0x000000398</td> 622 </tr> 623 <tr> 624 <td width="100">1.3.8</td> 625 <td>reg: <a href="#1.3.8">CHACHA_KEY5</a></td> 626 <td width="60"></td> 627 <td>0x00000039C</td> 628 </tr> 629 <tr> 630 <td width="100">1.3.9</td> 631 <td>reg: <a href="#1.3.9">CHACHA_KEY6</a></td> 632 <td width="60"></td> 633 <td>0x0000003A0</td> 634 </tr> 635 <tr> 636 <td width="100">1.3.10</td> 637 <td>reg: <a href="#1.3.10">CHACHA_KEY7</a></td> 638 <td width="60"></td> 639 <td>0x0000003A4</td> 640 </tr> 641 <tr> 642 <td width="100">1.3.11</td> 643 <td>reg: <a href="#1.3.11">CHACHA_IV_0</a></td> 644 <td width="60"></td> 645 <td>0x0000003A8</td> 646 </tr> 647 <tr> 648 <td width="100">1.3.12</td> 649 <td>reg: <a href="#1.3.12">CHACHA_IV_1</a></td> 650 <td width="60"></td> 651 <td>0x0000003AC</td> 652 </tr> 653 <tr> 654 <td width="100">1.3.13</td> 655 <td>reg: <a href="#1.3.13">CHACHA_BUSY</a></td> 656 <td width="60"></td> 657 <td>0x0000003B0</td> 658 </tr> 659 <tr> 660 <td width="100">1.3.14</td> 661 <td>reg: <a href="#1.3.14">CHACHA_HW_FLAGS</a></td> 662 <td width="60"></td> 663 <td>0x0000003B4</td> 664 </tr> 665 <tr> 666 <td width="100">1.3.15</td> 667 <td>reg: <a href="#1.3.15">CHACHA_BLOCK_CNT_LSB</a></td> 668 <td width="60"></td> 669 <td>0x0000003B8</td> 670 </tr> 671 <tr> 672 <td width="100">1.3.16</td> 673 <td>reg: <a href="#1.3.16">CHACHA_BLOCK_CNT_MSB</a></td> 674 <td width="60"></td> 675 <td>0x0000003BC</td> 676 </tr> 677 <tr> 678 <td width="100">1.3.17</td> 679 <td>reg: <a href="#1.3.17">CHACHA_SW_RESET</a></td> 680 <td width="60"></td> 681 <td>0x0000003C0</td> 682 </tr> 683 <tr> 684 <td width="100">1.3.18</td> 685 <td>reg: <a href="#1.3.18">CHACHA_FOR_POLY_KEY0</a></td> 686 <td width="60"></td> 687 <td>0x0000003C4</td> 688 </tr> 689 <tr> 690 <td width="100">1.3.19</td> 691 <td>reg: <a href="#1.3.19">CHACHA_FOR_POLY_KEY1</a></td> 692 <td width="60"></td> 693 <td>0x0000003C8</td> 694 </tr> 695 <tr> 696 <td width="100">1.3.20</td> 697 <td>reg: <a href="#1.3.20">CHACHA_FOR_POLY_KEY2</a></td> 698 <td width="60"></td> 699 <td>0x0000003CC</td> 700 </tr> 701 <tr> 702 <td width="100">1.3.21</td> 703 <td>reg: <a href="#1.3.21">CHACHA_FOR_POLY_KEY3</a></td> 704 <td width="60"></td> 705 <td>0x0000003D0</td> 706 </tr> 707 <tr> 708 <td width="100">1.3.22</td> 709 <td>reg: <a href="#1.3.22">CHACHA_FOR_POLY_KEY4</a></td> 710 <td width="60"></td> 711 <td>0x0000003D4</td> 712 </tr> 713 <tr> 714 <td width="100">1.3.23</td> 715 <td>reg: <a href="#1.3.23">CHACHA_FOR_POLY_KEY5</a></td> 716 <td width="60"></td> 717 <td>0x0000003D8</td> 718 </tr> 719 <tr> 720 <td width="100">1.3.24</td> 721 <td>reg: <a href="#1.3.24">CHACHA_FOR_POLY_KEY6</a></td> 722 <td width="60"></td> 723 <td>0x0000003DC</td> 724 </tr> 725 <tr> 726 <td width="100">1.3.25</td> 727 <td>reg: <a href="#1.3.25">CHACHA_FOR_POLY_KEY7</a></td> 728 <td width="60"></td> 729 <td>0x0000003E0</td> 730 </tr> 731 <tr> 732 <td width="100">1.3.26</td> 733 <td>reg: <a href="#1.3.26">CHACHA_BYTE_WORD_ORDER_CNTL_REG</a></td> 734 <td width="60"></td> 735 <td>0x0000003E4</td> 736 </tr> 737 <tr> 738 <td width="100">1.3.27</td> 739 <td>reg: <a href="#1.3.27">CHACHA_DEBUG_REG</a></td> 740 <td width="60"></td> 741 <td>0x0000003E8</td> 742 </tr> 743 <tr> 744 <td width="100">1.4</td> 745 <td>block: <a href="#1.4">AES</a></td> 746 <td width="60"></td> 747 <td>0x000000400</td> 748 </tr> 749 <tr> 750 <td width="100">1.4.1</td> 751 <td>reg: <a href="#1.4.1">AES_KEY_0_0</a></td> 752 <td width="60"></td> 753 <td>0x000000400</td> 754 </tr> 755 <tr> 756 <td width="100">1.4.2</td> 757 <td>reg: <a href="#1.4.2">AES_KEY_0_1</a></td> 758 <td width="60"></td> 759 <td>0x000000404</td> 760 </tr> 761 <tr> 762 <td width="100">1.4.3</td> 763 <td>reg: <a href="#1.4.3">AES_KEY_0_2</a></td> 764 <td width="60"></td> 765 <td>0x000000408</td> 766 </tr> 767 <tr> 768 <td width="100">1.4.4</td> 769 <td>reg: <a href="#1.4.4">AES_KEY_0_3</a></td> 770 <td width="60"></td> 771 <td>0x00000040C</td> 772 </tr> 773 <tr> 774 <td width="100">1.4.5</td> 775 <td>reg: <a href="#1.4.5">AES_KEY_0_4</a></td> 776 <td width="60"></td> 777 <td>0x000000410</td> 778 </tr> 779 <tr> 780 <td width="100">1.4.6</td> 781 <td>reg: <a href="#1.4.6">AES_KEY_0_5</a></td> 782 <td width="60"></td> 783 <td>0x000000414</td> 784 </tr> 785 <tr> 786 <td width="100">1.4.7</td> 787 <td>reg: <a href="#1.4.7">AES_KEY_0_6</a></td> 788 <td width="60"></td> 789 <td>0x000000418</td> 790 </tr> 791 <tr> 792 <td width="100">1.4.8</td> 793 <td>reg: <a href="#1.4.8">AES_KEY_0_7</a></td> 794 <td width="60"></td> 795 <td>0x00000041C</td> 796 </tr> 797 <tr> 798 <td width="100">1.4.9</td> 799 <td>reg: <a href="#1.4.9">AES_KEY_1_0</a></td> 800 <td width="60"></td> 801 <td>0x000000420</td> 802 </tr> 803 <tr> 804 <td width="100">1.4.10</td> 805 <td>reg: <a href="#1.4.10">AES_KEY_1_1</a></td> 806 <td width="60"></td> 807 <td>0x000000424</td> 808 </tr> 809 <tr> 810 <td width="100">1.4.11</td> 811 <td>reg: <a href="#1.4.11">AES_KEY_1_2</a></td> 812 <td width="60"></td> 813 <td>0x000000428</td> 814 </tr> 815 <tr> 816 <td width="100">1.4.12</td> 817 <td>reg: <a href="#1.4.12">AES_KEY_1_3</a></td> 818 <td width="60"></td> 819 <td>0x00000042C</td> 820 </tr> 821 <tr> 822 <td width="100">1.4.13</td> 823 <td>reg: <a href="#1.4.13">AES_KEY_1_4</a></td> 824 <td width="60"></td> 825 <td>0x000000430</td> 826 </tr> 827 <tr> 828 <td width="100">1.4.14</td> 829 <td>reg: <a href="#1.4.14">AES_KEY_1_5</a></td> 830 <td width="60"></td> 831 <td>0x000000434</td> 832 </tr> 833 <tr> 834 <td width="100">1.4.15</td> 835 <td>reg: <a href="#1.4.15">AES_KEY_1_6</a></td> 836 <td width="60"></td> 837 <td>0x000000438</td> 838 </tr> 839 <tr> 840 <td width="100">1.4.16</td> 841 <td>reg: <a href="#1.4.16">AES_KEY_1_7</a></td> 842 <td width="60"></td> 843 <td>0x00000043C</td> 844 </tr> 845 <tr> 846 <td width="100">1.4.17</td> 847 <td>reg: <a href="#1.4.17">AES_IV_0_0</a></td> 848 <td width="60"></td> 849 <td>0x000000440</td> 850 </tr> 851 <tr> 852 <td width="100">1.4.18</td> 853 <td>reg: <a href="#1.4.18">AES_IV_0_1</a></td> 854 <td width="60"></td> 855 <td>0x000000444</td> 856 </tr> 857 <tr> 858 <td width="100">1.4.19</td> 859 <td>reg: <a href="#1.4.19">AES_IV_0_2</a></td> 860 <td width="60"></td> 861 <td>0x000000448</td> 862 </tr> 863 <tr> 864 <td width="100">1.4.20</td> 865 <td>reg: <a href="#1.4.20">AES_IV_0_3</a></td> 866 <td width="60"></td> 867 <td>0x00000044C</td> 868 </tr> 869 <tr> 870 <td width="100">1.4.21</td> 871 <td>reg: <a href="#1.4.21">AES_IV_1_0</a></td> 872 <td width="60"></td> 873 <td>0x000000450</td> 874 </tr> 875 <tr> 876 <td width="100">1.4.22</td> 877 <td>reg: <a href="#1.4.22">AES_IV_1_1</a></td> 878 <td width="60"></td> 879 <td>0x000000454</td> 880 </tr> 881 <tr> 882 <td width="100">1.4.23</td> 883 <td>reg: <a href="#1.4.23">AES_IV_1_2</a></td> 884 <td width="60"></td> 885 <td>0x000000458</td> 886 </tr> 887 <tr> 888 <td width="100">1.4.24</td> 889 <td>reg: <a href="#1.4.24">AES_IV_1_3</a></td> 890 <td width="60"></td> 891 <td>0x00000045C</td> 892 </tr> 893 <tr> 894 <td width="100">1.4.25</td> 895 <td>reg: <a href="#1.4.25">AES_CTR_0_0</a></td> 896 <td width="60"></td> 897 <td>0x000000460</td> 898 </tr> 899 <tr> 900 <td width="100">1.4.26</td> 901 <td>reg: <a href="#1.4.26">AES_CTR_0_1</a></td> 902 <td width="60"></td> 903 <td>0x000000464</td> 904 </tr> 905 <tr> 906 <td width="100">1.4.27</td> 907 <td>reg: <a href="#1.4.27">AES_CTR_0_2</a></td> 908 <td width="60"></td> 909 <td>0x000000468</td> 910 </tr> 911 <tr> 912 <td width="100">1.4.28</td> 913 <td>reg: <a href="#1.4.28">AES_CTR_0_3</a></td> 914 <td width="60"></td> 915 <td>0x00000046C</td> 916 </tr> 917 <tr> 918 <td width="100">1.4.29</td> 919 <td>reg: <a href="#1.4.29">AES_BUSY</a></td> 920 <td width="60"></td> 921 <td>0x000000470</td> 922 </tr> 923 <tr> 924 <td width="100">1.4.30</td> 925 <td>reg: <a href="#1.4.30">AES_SK</a></td> 926 <td width="60"></td> 927 <td>0x000000478</td> 928 </tr> 929 <tr> 930 <td width="100">1.4.31</td> 931 <td>reg: <a href="#1.4.31">AES_CMAC_INIT</a></td> 932 <td width="60"></td> 933 <td>0x00000047C</td> 934 </tr> 935 <tr> 936 <td width="100">1.4.32</td> 937 <td>reg: <a href="#1.4.32">AES_SK1</a></td> 938 <td width="60"></td> 939 <td>0x0000004B4</td> 940 </tr> 941 <tr> 942 <td width="100">1.4.33</td> 943 <td>reg: <a href="#1.4.33">AES_REMAINING_BYTES</a></td> 944 <td width="60"></td> 945 <td>0x0000004BC</td> 946 </tr> 947 <tr> 948 <td width="100">1.4.34</td> 949 <td>reg: <a href="#1.4.34">AES_CONTROL</a></td> 950 <td width="60"></td> 951 <td>0x0000004C0</td> 952 </tr> 953 <tr> 954 <td width="100">1.4.35</td> 955 <td>reg: <a href="#1.4.35">AES_HW_FLAGS</a></td> 956 <td width="60"></td> 957 <td>0x0000004C8</td> 958 </tr> 959 <tr> 960 <td width="100">1.4.36</td> 961 <td>reg: <a href="#1.4.36">AES_CTR_NO_INCREMENT</a></td> 962 <td width="60"></td> 963 <td>0x0000004D8</td> 964 </tr> 965 <tr> 966 <td width="100">1.4.37</td> 967 <td>reg: <a href="#1.4.37">AES_DFA_IS_ON</a></td> 968 <td width="60"></td> 969 <td>0x0000004F0</td> 970 </tr> 971 <tr> 972 <td width="100">1.4.38</td> 973 <td>reg: <a href="#1.4.38">AES_DFA_ERR_STATUS</a></td> 974 <td width="60"></td> 975 <td>0x0000004F8</td> 976 </tr> 977 <tr> 978 <td width="100">1.4.39</td> 979 <td>reg: <a href="#1.4.39">AES_CMAC_SIZE0_KICK</a></td> 980 <td width="60"></td> 981 <td>0x000000524</td> 982 </tr> 983 <tr> 984 <td width="100">1.5</td> 985 <td>block: <a href="#1.5">HASH</a></td> 986 <td width="60"></td> 987 <td>0x000000640</td> 988 </tr> 989 <tr> 990 <td width="100">1.5.1</td> 991 <td>reg: <a href="#1.5.1">HASH_H0</a></td> 992 <td width="60"></td> 993 <td>0x000000640</td> 994 </tr> 995 <tr> 996 <td width="100">1.5.2</td> 997 <td>reg: <a href="#1.5.2">HASH_H1</a></td> 998 <td width="60"></td> 999 <td>0x000000644</td> 1000 </tr> 1001 <tr> 1002 <td width="100">1.5.3</td> 1003 <td>reg: <a href="#1.5.3">HASH_H2</a></td> 1004 <td width="60"></td> 1005 <td>0x000000648</td> 1006 </tr> 1007 <tr> 1008 <td width="100">1.5.4</td> 1009 <td>reg: <a href="#1.5.4">HASH_H3</a></td> 1010 <td width="60"></td> 1011 <td>0x00000064C</td> 1012 </tr> 1013 <tr> 1014 <td width="100">1.5.5</td> 1015 <td>reg: <a href="#1.5.5">HASH_H4</a></td> 1016 <td width="60"></td> 1017 <td>0x000000650</td> 1018 </tr> 1019 <tr> 1020 <td width="100">1.5.6</td> 1021 <td>reg: <a href="#1.5.6">HASH_H5</a></td> 1022 <td width="60"></td> 1023 <td>0x000000654</td> 1024 </tr> 1025 <tr> 1026 <td width="100">1.5.7</td> 1027 <td>reg: <a href="#1.5.7">HASH_H6</a></td> 1028 <td width="60"></td> 1029 <td>0x000000658</td> 1030 </tr> 1031 <tr> 1032 <td width="100">1.5.8</td> 1033 <td>reg: <a href="#1.5.8">HASH_H7</a></td> 1034 <td width="60"></td> 1035 <td>0x00000065C</td> 1036 </tr> 1037 <tr> 1038 <td width="100">1.5.9</td> 1039 <td>reg: <a href="#1.5.9">HASH_H8</a></td> 1040 <td width="60"></td> 1041 <td>0x000000660</td> 1042 </tr> 1043 <tr> 1044 <td width="100">1.5.10</td> 1045 <td>reg: <a href="#1.5.10">AUTO_HW_PADDING</a></td> 1046 <td width="60"></td> 1047 <td>0x000000684</td> 1048 </tr> 1049 <tr> 1050 <td width="100">1.5.11</td> 1051 <td>reg: <a href="#1.5.11">HASH_XOR_DIN</a></td> 1052 <td width="60"></td> 1053 <td>0x000000688</td> 1054 </tr> 1055 <tr> 1056 <td width="100">1.5.12</td> 1057 <td>reg: <a href="#1.5.12">LOAD_INIT_STATE</a></td> 1058 <td width="60"></td> 1059 <td>0x000000694</td> 1060 </tr> 1061 <tr> 1062 <td width="100">1.5.13</td> 1063 <td>reg: <a href="#1.5.13">HASH_SEL_AES_MAC</a></td> 1064 <td width="60"></td> 1065 <td>0x0000006A4</td> 1066 </tr> 1067 <tr> 1068 <td width="100">1.5.14</td> 1069 <td>reg: <a href="#1.5.14">HASH_VERSION</a></td> 1070 <td width="60"></td> 1071 <td>0x0000007B0</td> 1072 </tr> 1073 <tr> 1074 <td width="100">1.5.15</td> 1075 <td>reg: <a href="#1.5.15">HASH_CONTROL</a></td> 1076 <td width="60"></td> 1077 <td>0x0000007C0</td> 1078 </tr> 1079 <tr> 1080 <td width="100">1.5.16</td> 1081 <td>reg: <a href="#1.5.16">HASH_PAD_EN</a></td> 1082 <td width="60"></td> 1083 <td>0x0000007C4</td> 1084 </tr> 1085 <tr> 1086 <td width="100">1.5.17</td> 1087 <td>reg: <a href="#1.5.17">HASH_PAD_CFG</a></td> 1088 <td width="60"></td> 1089 <td>0x0000007C8</td> 1090 </tr> 1091 <tr> 1092 <td width="100">1.5.18</td> 1093 <td>reg: <a href="#1.5.18">HASH_CUR_LEN_0</a></td> 1094 <td width="60"></td> 1095 <td>0x0000007CC</td> 1096 </tr> 1097 <tr> 1098 <td width="100">1.5.19</td> 1099 <td>reg: <a href="#1.5.19">HASH_CUR_LEN_1</a></td> 1100 <td width="60"></td> 1101 <td>0x0000007D0</td> 1102 </tr> 1103 <tr> 1104 <td width="100">1.5.20</td> 1105 <td>reg: <a href="#1.5.20">HASH_PARAM</a></td> 1106 <td width="60"></td> 1107 <td>0x0000007DC</td> 1108 </tr> 1109 <tr> 1110 <td width="100">1.5.21</td> 1111 <td>reg: <a href="#1.5.21">HASH_AES_SW_RESET</a></td> 1112 <td width="60"></td> 1113 <td>0x0000007E4</td> 1114 </tr> 1115 <tr> 1116 <td width="100">1.5.22</td> 1117 <td>reg: <a href="#1.5.22">HASH_ENDIANESS</a></td> 1118 <td width="60"></td> 1119 <td>0x0000007E8</td> 1120 </tr> 1121 <tr> 1122 <td width="100">1.6</td> 1123 <td>block: <a href="#1.6">MISC</a></td> 1124 <td width="60"></td> 1125 <td>0x000000800</td> 1126 </tr> 1127 <tr> 1128 <td width="100">1.6.1</td> 1129 <td>reg: <a href="#1.6.1">AES_CLK_ENABLE</a></td> 1130 <td width="60"></td> 1131 <td>0x000000810</td> 1132 </tr> 1133 <tr> 1134 <td width="100">1.6.2</td> 1135 <td>reg: <a href="#1.6.2">HASH_CLK_ENABLE</a></td> 1136 <td width="60"></td> 1137 <td>0x000000818</td> 1138 </tr> 1139 <tr> 1140 <td width="100">1.6.3</td> 1141 <td>reg: <a href="#1.6.3">PKA_CLK_ENABLE</a></td> 1142 <td width="60"></td> 1143 <td>0x00000081C</td> 1144 </tr> 1145 <tr> 1146 <td width="100">1.6.4</td> 1147 <td>reg: <a href="#1.6.4">DMA_CLK_ENABLE</a></td> 1148 <td width="60"></td> 1149 <td>0x000000820</td> 1150 </tr> 1151 <tr> 1152 <td width="100">1.6.5</td> 1153 <td>reg: <a href="#1.6.5">CLK_STATUS</a></td> 1154 <td width="60"></td> 1155 <td>0x000000824</td> 1156 </tr> 1157 <tr> 1158 <td width="100">1.6.6</td> 1159 <td>reg: <a href="#1.6.6">CHACHA_CLK_ENABLE</a></td> 1160 <td width="60"></td> 1161 <td>0x000000858</td> 1162 </tr> 1163 <tr> 1164 <td width="100">1.7</td> 1165 <td>block: <a href="#1.7">CC_CTL</a></td> 1166 <td width="60"></td> 1167 <td>0x000000900</td> 1168 </tr> 1169 <tr> 1170 <td width="100">1.7.1</td> 1171 <td>reg: <a href="#1.7.1">CRYPTO_CTL</a></td> 1172 <td width="60"></td> 1173 <td>0x000000900</td> 1174 </tr> 1175 <tr> 1176 <td width="100">1.7.2</td> 1177 <td>reg: <a href="#1.7.2">CRYPTO_BUSY</a></td> 1178 <td width="60"></td> 1179 <td>0x000000910</td> 1180 </tr> 1181 <tr> 1182 <td width="100">1.7.3</td> 1183 <td>reg: <a href="#1.7.3">HASH_BUSY</a></td> 1184 <td width="60"></td> 1185 <td>0x00000091C</td> 1186 </tr> 1187 <tr> 1188 <td width="100">1.7.4</td> 1189 <td>reg: <a href="#1.7.4">CONTEXT_ID</a></td> 1190 <td width="60"></td> 1191 <td>0x000000930</td> 1192 </tr> 1193 <tr> 1194 <td width="100">1.8</td> 1195 <td>block: <a href="#1.8">GHASH</a></td> 1196 <td width="60"></td> 1197 <td>0x000000960</td> 1198 </tr> 1199 <tr> 1200 <td width="100">1.8.1</td> 1201 <td>reg: <a href="#1.8.1">GHASH_SUBKEY_0_0</a></td> 1202 <td width="60"></td> 1203 <td>0x000000960</td> 1204 </tr> 1205 <tr> 1206 <td width="100">1.8.2</td> 1207 <td>reg: <a href="#1.8.2">GHASH_SUBKEY_0_1</a></td> 1208 <td width="60"></td> 1209 <td>0x000000964</td> 1210 </tr> 1211 <tr> 1212 <td width="100">1.8.3</td> 1213 <td>reg: <a href="#1.8.3">GHASH_SUBKEY_0_2</a></td> 1214 <td width="60"></td> 1215 <td>0x000000968</td> 1216 </tr> 1217 <tr> 1218 <td width="100">1.8.4</td> 1219 <td>reg: <a href="#1.8.4">GHASH_SUBKEY_0_3</a></td> 1220 <td width="60"></td> 1221 <td>0x00000096C</td> 1222 </tr> 1223 <tr> 1224 <td width="100">1.8.5</td> 1225 <td>reg: <a href="#1.8.5">GHASH_IV_0_0</a></td> 1226 <td width="60"></td> 1227 <td>0x000000970</td> 1228 </tr> 1229 <tr> 1230 <td width="100">1.8.6</td> 1231 <td>reg: <a href="#1.8.6">GHASH_IV_0_1</a></td> 1232 <td width="60"></td> 1233 <td>0x000000974</td> 1234 </tr> 1235 <tr> 1236 <td width="100">1.8.7</td> 1237 <td>reg: <a href="#1.8.7">GHASH_IV_0_2</a></td> 1238 <td width="60"></td> 1239 <td>0x000000978</td> 1240 </tr> 1241 <tr> 1242 <td width="100">1.8.8</td> 1243 <td>reg: <a href="#1.8.8">GHASH_IV_0_3</a></td> 1244 <td width="60"></td> 1245 <td>0x00000097C</td> 1246 </tr> 1247 <tr> 1248 <td width="100">1.8.9</td> 1249 <td>reg: <a href="#1.8.9">GHASH_BUSY</a></td> 1250 <td width="60"></td> 1251 <td>0x000000980</td> 1252 </tr> 1253 <tr> 1254 <td width="100">1.8.10</td> 1255 <td>reg: <a href="#1.8.10">GHASH_INIT</a></td> 1256 <td width="60"></td> 1257 <td>0x000000984</td> 1258 </tr> 1259 <tr> 1260 <td width="100">1.9</td> 1261 <td>block: <a href="#1.9">HOST_RGF</a></td> 1262 <td width="60"></td> 1263 <td>0x000000A00</td> 1264 </tr> 1265 <tr> 1266 <td width="100">1.9.1</td> 1267 <td>reg: <a href="#1.9.1">HOST_RGF_IRR</a></td> 1268 <td width="60"></td> 1269 <td>0x000000A00</td> 1270 </tr> 1271 <tr> 1272 <td width="100">1.9.2</td> 1273 <td>reg: <a href="#1.9.2">HOST_RGF_IMR</a></td> 1274 <td width="60"></td> 1275 <td>0x000000A04</td> 1276 </tr> 1277 <tr> 1278 <td width="100">1.9.3</td> 1279 <td>reg: <a href="#1.9.3">HOST_RGF_ICR</a></td> 1280 <td width="60"></td> 1281 <td>0x000000A08</td> 1282 </tr> 1283 <tr> 1284 <td width="100">1.9.4</td> 1285 <td>reg: <a href="#1.9.4">HOST_RGF_ENDIAN</a></td> 1286 <td width="60"></td> 1287 <td>0x000000A0C</td> 1288 </tr> 1289 <tr> 1290 <td width="100">1.9.5</td> 1291 <td>reg: <a href="#1.9.5">HOST_RGF_SIGNATURE</a></td> 1292 <td width="60"></td> 1293 <td>0x000000A24</td> 1294 </tr> 1295 <tr> 1296 <td width="100">1.9.6</td> 1297 <td>reg: <a href="#1.9.6">HOST_BOOT</a></td> 1298 <td width="60"></td> 1299 <td>0x000000A28</td> 1300 </tr> 1301 <tr> 1302 <td width="100">1.9.7</td> 1303 <td>reg: <a href="#1.9.7">HOST_CRYPTOKEY_SEL</a></td> 1304 <td width="60"></td> 1305 <td>0x000000A38</td> 1306 </tr> 1307 <tr> 1308 <td width="100">1.9.8</td> 1309 <td>reg: <a href="#1.9.8">HOST_CORE_CLK_GATING_ENABLE</a></td> 1310 <td width="60"></td> 1311 <td>0x000000A78</td> 1312 </tr> 1313 <tr> 1314 <td width="100">1.9.9</td> 1315 <td>reg: <a href="#1.9.9">HOST_CC_IS_IDLE</a></td> 1316 <td width="60"></td> 1317 <td>0x000000A7C</td> 1318 </tr> 1319 <tr> 1320 <td width="100">1.9.10</td> 1321 <td>reg: <a href="#1.9.10">HOST_POWERDOWN</a></td> 1322 <td width="60"></td> 1323 <td>0x000000A80</td> 1324 </tr> 1325 <tr> 1326 <td width="100">1.9.11</td> 1327 <td>reg: <a href="#1.9.11">HOST_REMOVE_GHASH_ENGINE</a></td> 1328 <td width="60"></td> 1329 <td>0x000000A84</td> 1330 </tr> 1331 <tr> 1332 <td width="100">1.9.12</td> 1333 <td>reg: <a href="#1.9.12">HOST_REMOVE_CHACHA_ENGINE</a></td> 1334 <td width="60"></td> 1335 <td>0x000000A88</td> 1336 </tr> 1337 <tr> 1338 <td width="100">1.10</td> 1339 <td>block: <a href="#1.10">AHB</a></td> 1340 <td width="60"></td> 1341 <td>0x000000B00</td> 1342 </tr> 1343 <tr> 1344 <td width="100">1.10.1</td> 1345 <td>reg: <a href="#1.10.1">AHBM_SINGLES</a></td> 1346 <td width="60"></td> 1347 <td>0x000000B00</td> 1348 </tr> 1349 <tr> 1350 <td width="100">1.10.2</td> 1351 <td>reg: <a href="#1.10.2">AHBM_HPROT</a></td> 1352 <td width="60"></td> 1353 <td>0x000000B04</td> 1354 </tr> 1355 <tr> 1356 <td width="100">1.10.3</td> 1357 <td>reg: <a href="#1.10.3">AHBM_HMASTLOCK</a></td> 1358 <td width="60"></td> 1359 <td>0x000000B08</td> 1360 </tr> 1361 <tr> 1362 <td width="100">1.10.4</td> 1363 <td>reg: <a href="#1.10.4">AHBM_HNONSEC</a></td> 1364 <td width="60"></td> 1365 <td>0x000000B0C</td> 1366 </tr> 1367 <tr> 1368 <td width="100">1.11</td> 1369 <td>block: <a href="#1.11">DIN</a></td> 1370 <td width="60"></td> 1371 <td>0x000000C00</td> 1372 </tr> 1373 <tr> 1374 <td width="100">1.11.1</td> 1375 <td>reg: <a href="#1.11.1">DIN_BUFFER</a></td> 1376 <td width="60"></td> 1377 <td>0x000000C00</td> 1378 </tr> 1379 <tr> 1380 <td width="100">1.11.2</td> 1381 <td>reg: <a href="#1.11.2">DIN_MEM_DMA_BUSY</a></td> 1382 <td width="60"></td> 1383 <td>0x000000C20</td> 1384 </tr> 1385 <tr> 1386 <td width="100">1.11.3</td> 1387 <td>reg: <a href="#1.11.3">SRC_LLI_WORD0</a></td> 1388 <td width="60"></td> 1389 <td>0x000000C28</td> 1390 </tr> 1391 <tr> 1392 <td width="100">1.11.4</td> 1393 <td>reg: <a href="#1.11.4">SRC_LLI_WORD1</a></td> 1394 <td width="60"></td> 1395 <td>0x000000C2C</td> 1396 </tr> 1397 <tr> 1398 <td width="100">1.11.5</td> 1399 <td>reg: <a href="#1.11.5">SRAM_SRC_ADDR</a></td> 1400 <td width="60"></td> 1401 <td>0x000000C30</td> 1402 </tr> 1403 <tr> 1404 <td width="100">1.11.6</td> 1405 <td>reg: <a href="#1.11.6">DIN_SRAM_BYTES_LEN</a></td> 1406 <td width="60"></td> 1407 <td>0x000000C34</td> 1408 </tr> 1409 <tr> 1410 <td width="100">1.11.7</td> 1411 <td>reg: <a href="#1.11.7">DIN_SRAM_DMA_BUSY</a></td> 1412 <td width="60"></td> 1413 <td>0x000000C38</td> 1414 </tr> 1415 <tr> 1416 <td width="100">1.11.8</td> 1417 <td>reg: <a href="#1.11.8">DIN_SRAM_ENDIANNESS</a></td> 1418 <td width="60"></td> 1419 <td>0x000000C3C</td> 1420 </tr> 1421 <tr> 1422 <td width="100">1.11.9</td> 1423 <td>reg: <a href="#1.11.9">DIN_CPU_DATA_SIZE</a></td> 1424 <td width="60"></td> 1425 <td>0x000000C48</td> 1426 </tr> 1427 <tr> 1428 <td width="100">1.11.10</td> 1429 <td>reg: <a href="#1.11.10">FIFO_IN_EMPTY</a></td> 1430 <td width="60"></td> 1431 <td>0x000000C50</td> 1432 </tr> 1433 <tr> 1434 <td width="100">1.11.11</td> 1435 <td>reg: <a href="#1.11.11">DIN_FIFO_RST_PNTR</a></td> 1436 <td width="60"></td> 1437 <td>0x000000C58</td> 1438 </tr> 1439 <tr> 1440 <td width="100">1.12</td> 1441 <td>block: <a href="#1.12">DOUT</a></td> 1442 <td width="60"></td> 1443 <td>0x000000D00</td> 1444 </tr> 1445 <tr> 1446 <td width="100">1.12.1</td> 1447 <td>reg: <a href="#1.12.1">DOUT_BUFFER</a></td> 1448 <td width="60"></td> 1449 <td>0x000000D00</td> 1450 </tr> 1451 <tr> 1452 <td width="100">1.12.2</td> 1453 <td>reg: <a href="#1.12.2">DOUT_MEM_DMA_BUSY</a></td> 1454 <td width="60"></td> 1455 <td>0x000000D20</td> 1456 </tr> 1457 <tr> 1458 <td width="100">1.12.3</td> 1459 <td>reg: <a href="#1.12.3">DST_LLI_WORD0</a></td> 1460 <td width="60"></td> 1461 <td>0x000000D28</td> 1462 </tr> 1463 <tr> 1464 <td width="100">1.12.4</td> 1465 <td>reg: <a href="#1.12.4">DST_LLI_WORD1</a></td> 1466 <td width="60"></td> 1467 <td>0x000000D2C</td> 1468 </tr> 1469 <tr> 1470 <td width="100">1.12.5</td> 1471 <td>reg: <a href="#1.12.5">SRAM_DEST_ADDR</a></td> 1472 <td width="60"></td> 1473 <td>0x000000D30</td> 1474 </tr> 1475 <tr> 1476 <td width="100">1.12.6</td> 1477 <td>reg: <a href="#1.12.6">DOUT_SRAM_BYTES_LEN</a></td> 1478 <td width="60"></td> 1479 <td>0x000000D34</td> 1480 </tr> 1481 <tr> 1482 <td width="100">1.12.7</td> 1483 <td>reg: <a href="#1.12.7">DOUT_SRAM_DMA_BUSY</a></td> 1484 <td width="60"></td> 1485 <td>0x000000D38</td> 1486 </tr> 1487 <tr> 1488 <td width="100">1.12.8</td> 1489 <td>reg: <a href="#1.12.8">DOUT_SRAM_ENDIANNESS</a></td> 1490 <td width="60"></td> 1491 <td>0x000000D3C</td> 1492 </tr> 1493 <tr> 1494 <td width="100">1.12.9</td> 1495 <td>reg: <a href="#1.12.9">READ_ALIGN_LAST</a></td> 1496 <td width="60"></td> 1497 <td>0x000000D44</td> 1498 </tr> 1499 <tr> 1500 <td width="100">1.12.10</td> 1501 <td>reg: <a href="#1.12.10">DOUT_FIFO_EMPTY</a></td> 1502 <td width="60"></td> 1503 <td>0x000000D50</td> 1504 </tr> 1505 <tr> 1506 <td width="100">1.13</td> 1507 <td>block: <a href="#1.13">HOST_SRAM</a></td> 1508 <td width="60"></td> 1509 <td>0x000000F00</td> 1510 </tr> 1511 <tr> 1512 <td width="100">1.13.1</td> 1513 <td>reg: <a href="#1.13.1">SRAM_DATA</a></td> 1514 <td width="60"></td> 1515 <td>0x000000F00</td> 1516 </tr> 1517 <tr> 1518 <td width="100">1.13.2</td> 1519 <td>reg: <a href="#1.13.2">SRAM_ADDR</a></td> 1520 <td width="60"></td> 1521 <td>0x000000F04</td> 1522 </tr> 1523 <tr> 1524 <td width="100">1.13.3</td> 1525 <td>reg: <a href="#1.13.3">SRAM_DATA_READY</a></td> 1526 <td width="60"></td> 1527 <td>0x000000F08</td> 1528 </tr> 1529 <tr> 1530 <td width="100">1.14</td> 1531 <td>block: <a href="#1.14">ID_REGISTERS</a></td> 1532 <td width="60"></td> 1533 <td>0x000000F10</td> 1534 </tr> 1535 <tr> 1536 <td width="100">1.14.1</td> 1537 <td>reg: <a href="#1.14.1">PERIPHERAL_ID_4</a></td> 1538 <td width="60"></td> 1539 <td>0x000000FD0</td> 1540 </tr> 1541 <tr> 1542 <td width="100">1.14.2</td> 1543 <td>reg: <a href="#1.14.2">PIDRESERVED0</a></td> 1544 <td width="60"></td> 1545 <td>0x000000FD4</td> 1546 </tr> 1547 <tr> 1548 <td width="100">1.14.3</td> 1549 <td>reg: <a href="#1.14.3">PIDRESERVED1</a></td> 1550 <td width="60"></td> 1551 <td>0x000000FD8</td> 1552 </tr> 1553 <tr> 1554 <td width="100">1.14.4</td> 1555 <td>reg: <a href="#1.14.4">PIDRESERVED2</a></td> 1556 <td width="60"></td> 1557 <td>0x000000FDC</td> 1558 </tr> 1559 <tr> 1560 <td width="100">1.14.5</td> 1561 <td>reg: <a href="#1.14.5">PERIPHERAL_ID_0</a></td> 1562 <td width="60"></td> 1563 <td>0x000000FE0</td> 1564 </tr> 1565 <tr> 1566 <td width="100">1.14.6</td> 1567 <td>reg: <a href="#1.14.6">PERIPHERAL_ID_1</a></td> 1568 <td width="60"></td> 1569 <td>0x000000FE4</td> 1570 </tr> 1571 <tr> 1572 <td width="100">1.14.7</td> 1573 <td>reg: <a href="#1.14.7">PERIPHERAL_ID_2</a></td> 1574 <td width="60"></td> 1575 <td>0x000000FE8</td> 1576 </tr> 1577 <tr> 1578 <td width="100">1.14.8</td> 1579 <td>reg: <a href="#1.14.8">PERIPHERAL_ID_3</a></td> 1580 <td width="60"></td> 1581 <td>0x000000FEC</td> 1582 </tr> 1583 <tr> 1584 <td width="100">1.14.9</td> 1585 <td>reg: <a href="#1.14.9">COMPONENT_ID_0</a></td> 1586 <td width="60"></td> 1587 <td>0x000000FF0</td> 1588 </tr> 1589 <tr> 1590 <td width="100">1.14.10</td> 1591 <td>reg: <a href="#1.14.10">COMPONENT_ID_1</a></td> 1592 <td width="60"></td> 1593 <td>0x000000FF4</td> 1594 </tr> 1595 <tr> 1596 <td width="100">1.14.11</td> 1597 <td>reg: <a href="#1.14.11">COMPONENT_ID_2</a></td> 1598 <td width="60"></td> 1599 <td>0x000000FF8</td> 1600 </tr> 1601 <tr> 1602 <td width="100">1.14.12</td> 1603 <td>reg: <a href="#1.14.12">COMPONENT_ID_3</a></td> 1604 <td width="60"></td> 1605 <td>0x000000FFC</td> 1606 </tr> 1607 <tr> 1608 <td width="100">1.15</td> 1609 <td>block: <a href="#1.15">AO</a></td> 1610 <td width="60"></td> 1611 <td>0x000001E00</td> 1612 </tr> 1613 <tr> 1614 <td width="100">1.15.1</td> 1615 <td>reg: <a href="#1.15.1">HOST_DCU_EN0</a></td> 1616 <td width="60"></td> 1617 <td>0x000001E00</td> 1618 </tr> 1619 <tr> 1620 <td width="100">1.15.2</td> 1621 <td>reg: <a href="#1.15.2">HOST_DCU_EN1</a></td> 1622 <td width="60"></td> 1623 <td>0x000001E04</td> 1624 </tr> 1625 <tr> 1626 <td width="100">1.15.3</td> 1627 <td>reg: <a href="#1.15.3">HOST_DCU_EN2</a></td> 1628 <td width="60"></td> 1629 <td>0x000001E08</td> 1630 </tr> 1631 <tr> 1632 <td width="100">1.15.4</td> 1633 <td>reg: <a href="#1.15.4">HOST_DCU_EN3</a></td> 1634 <td width="60"></td> 1635 <td>0x000001E0C</td> 1636 </tr> 1637 <tr> 1638 <td width="100">1.15.5</td> 1639 <td>reg: <a href="#1.15.5">HOST_DCU_LOCK0</a></td> 1640 <td width="60"></td> 1641 <td>0x000001E10</td> 1642 </tr> 1643 <tr> 1644 <td width="100">1.15.6</td> 1645 <td>reg: <a href="#1.15.6">HOST_DCU_LOCK1</a></td> 1646 <td width="60"></td> 1647 <td>0x000001E14</td> 1648 </tr> 1649 <tr> 1650 <td width="100">1.15.7</td> 1651 <td>reg: <a href="#1.15.7">HOST_DCU_LOCK2</a></td> 1652 <td width="60"></td> 1653 <td>0x000001E18</td> 1654 </tr> 1655 <tr> 1656 <td width="100">1.15.8</td> 1657 <td>reg: <a href="#1.15.8">HOST_DCU_LOCK3</a></td> 1658 <td width="60"></td> 1659 <td>0x000001E1C</td> 1660 </tr> 1661 <tr> 1662 <td width="100">1.15.9</td> 1663 <td>reg: <a href="#1.15.9">AO_ICV_DCU_RESTRICTION_MASK0</a></td> 1664 <td width="60"></td> 1665 <td>0x000001E20</td> 1666 </tr> 1667 <tr> 1668 <td width="100">1.15.10</td> 1669 <td>reg: <a href="#1.15.10">AO_ICV_DCU_RESTRICTION_MASK1</a></td> 1670 <td width="60"></td> 1671 <td>0x000001E24</td> 1672 </tr> 1673 <tr> 1674 <td width="100">1.15.11</td> 1675 <td>reg: <a href="#1.15.11">AO_ICV_DCU_RESTRICTION_MASK2</a></td> 1676 <td width="60"></td> 1677 <td>0x000001E28</td> 1678 </tr> 1679 <tr> 1680 <td width="100">1.15.12</td> 1681 <td>reg: <a href="#1.15.12">AO_ICV_DCU_RESTRICTION_MASK3</a></td> 1682 <td width="60"></td> 1683 <td>0x000001E2C</td> 1684 </tr> 1685 <tr> 1686 <td width="100">1.15.13</td> 1687 <td>reg: <a href="#1.15.13">AO_CC_SEC_DEBUG_RESET</a></td> 1688 <td width="60"></td> 1689 <td>0x000001E30</td> 1690 </tr> 1691 <tr> 1692 <td width="100">1.15.14</td> 1693 <td>reg: <a href="#1.15.14">HOST_AO_LOCK_BITS</a></td> 1694 <td width="60"></td> 1695 <td>0x000001E34</td> 1696 </tr> 1697 <tr> 1698 <td width="100">1.15.15</td> 1699 <td>reg: <a href="#1.15.15">AO_APB_FILTERING</a></td> 1700 <td width="60"></td> 1701 <td>0x000001E38</td> 1702 </tr> 1703 <tr> 1704 <td width="100">1.15.16</td> 1705 <td>reg: <a href="#1.15.16">AO_CC_GPPC</a></td> 1706 <td width="60"></td> 1707 <td>0x000001E3C</td> 1708 </tr> 1709 <tr> 1710 <td width="100">1.15.17</td> 1711 <td>reg: <a href="#1.15.17">HOST_RGF_CC_SW_RST</a></td> 1712 <td width="60"></td> 1713 <td>0x000001E40</td> 1714 </tr> 1715 <tr> 1716 <td width="100">1.16</td> 1717 <td>block: <a href="#1.16">NVM</a></td> 1718 <td width="60"></td> 1719 <td>0x000001F00</td> 1720 </tr> 1721 <tr> 1722 <td width="100">1.16.1</td> 1723 <td>reg: <a href="#1.16.1">AIB_FUSE_PROG_COMPLETED</a></td> 1724 <td width="60"></td> 1725 <td>0x000001F04</td> 1726 </tr> 1727 <tr> 1728 <td width="100">1.16.2</td> 1729 <td>reg: <a href="#1.16.2">NVM_DEBUG_STATUS</a></td> 1730 <td width="60"></td> 1731 <td>0x000001F08</td> 1732 </tr> 1733 <tr> 1734 <td width="100">1.16.3</td> 1735 <td>reg: <a href="#1.16.3">LCS_IS_VALID</a></td> 1736 <td width="60"></td> 1737 <td>0x000001F0C</td> 1738 </tr> 1739 <tr> 1740 <td width="100">1.16.4</td> 1741 <td>reg: <a href="#1.16.4">NVM_IS_IDLE</a></td> 1742 <td width="60"></td> 1743 <td>0x000001F10</td> 1744 </tr> 1745 <tr> 1746 <td width="100">1.16.5</td> 1747 <td>reg: <a href="#1.16.5">LCS_REG</a></td> 1748 <td width="60"></td> 1749 <td>0x000001F14</td> 1750 </tr> 1751 <tr> 1752 <td width="100">1.16.6</td> 1753 <td>reg: <a href="#1.16.6">HOST_SHADOW_KDR_REG</a></td> 1754 <td width="60"></td> 1755 <td>0x000001F18</td> 1756 </tr> 1757 <tr> 1758 <td width="100">1.16.7</td> 1759 <td>reg: <a href="#1.16.7">HOST_SHADOW_KCP_REG</a></td> 1760 <td width="60"></td> 1761 <td>0x000001F1C</td> 1762 </tr> 1763 <tr> 1764 <td width="100">1.16.8</td> 1765 <td>reg: <a href="#1.16.8">HOST_SHADOW_KCE_REG</a></td> 1766 <td width="60"></td> 1767 <td>0x000001F20</td> 1768 </tr> 1769 <tr> 1770 <td width="100">1.16.9</td> 1771 <td>reg: <a href="#1.16.9">HOST_SHADOW_KPICV_REG</a></td> 1772 <td width="60"></td> 1773 <td>0x000001F24</td> 1774 </tr> 1775 <tr> 1776 <td width="100">1.16.10</td> 1777 <td>reg: <a href="#1.16.10">HOST_SHADOW_KCEICV_REG</a></td> 1778 <td width="60"></td> 1779 <td>0x000001F28</td> 1780 </tr> 1781 <tr> 1782 <td width="100">1.16.11</td> 1783 <td>reg: <a href="#1.16.11">OTP_ADDR_WIDTH_DEF</a></td> 1784 <td width="60"></td> 1785 <td>0x000001F2C</td> 1786 </tr> 1787 <tr> 1788 <td width="100">1.17</td> 1789 <td>block: <a href="#1.17">ENV_CC_MEMORIES</a></td> 1790 <td width="60"></td> 1791 <td>0x060004000</td> 1792 </tr> 1793 <tr> 1794 <td width="100">1.17.1</td> 1795 <td>reg: <a href="#1.17.1">ENV_FUSE_READY</a></td> 1796 <td width="60"></td> 1797 <td>0x060004000</td> 1798 </tr> 1799 <tr> 1800 <td width="100">1.17.2</td> 1801 <td>reg: <a href="#1.17.2">ENV_PERF_RAM_MASTER</a></td> 1802 <td width="60"></td> 1803 <td>0x0600040EC</td> 1804 </tr> 1805 <tr> 1806 <td width="100">1.17.3</td> 1807 <td>reg: <a href="#1.17.3">ENV_PERF_RAM_ADDR_HIGH4</a></td> 1808 <td width="60"></td> 1809 <td>0x0600040F0</td> 1810 </tr> 1811 <tr> 1812 <td width="100">1.17.4</td> 1813 <td>reg: <a href="#1.17.4">ENV_FUSES_RAM</a></td> 1814 <td width="60"></td> 1815 <td>0x0600043EC</td> 1816 </tr> 1817 <tr> 1818 <td width="100">1.18</td> 1819 <td>block: <a href="#1.18">FPGA_ENV_REGS</a></td> 1820 <td width="60"></td> 1821 <td>0x060005000</td> 1822 </tr> 1823 <tr> 1824 <td width="100">1.18.1</td> 1825 <td>reg: <a href="#1.18.1">ENV_FPGA_PKA_DEBUG_MODE</a></td> 1826 <td width="60"></td> 1827 <td>0x060005024</td> 1828 </tr> 1829 <tr> 1830 <td width="100">1.18.2</td> 1831 <td>reg: <a href="#1.18.2">ENV_FPGA_SCAN_MODE</a></td> 1832 <td width="60"></td> 1833 <td>0x060005030</td> 1834 </tr> 1835 <tr> 1836 <td width="100">1.18.3</td> 1837 <td>reg: <a href="#1.18.3">ENV_FPGA_CC_ALLOW_SCAN</a></td> 1838 <td width="60"></td> 1839 <td>0x060005034</td> 1840 </tr> 1841 <tr> 1842 <td width="100">1.18.4</td> 1843 <td>reg: <a href="#1.18.4">ENV_FPGA_CC_HOST_INT</a></td> 1844 <td width="60"></td> 1845 <td>0x0600050A0</td> 1846 </tr> 1847 <tr> 1848 <td width="100">1.18.5</td> 1849 <td>reg: <a href="#1.18.5">ENV_FPGA_CC_PUB_HOST_INT</a></td> 1850 <td width="60"></td> 1851 <td>0x0600050A4</td> 1852 </tr> 1853 <tr> 1854 <td width="100">1.18.6</td> 1855 <td>reg: <a href="#1.18.6">ENV_FPGA_CC_RST_N</a></td> 1856 <td width="60"></td> 1857 <td>0x0600050A8</td> 1858 </tr> 1859 <tr> 1860 <td width="100">1.18.7</td> 1861 <td>reg: <a href="#1.18.7">ENV_FPGA_RST_OVERRIDE</a></td> 1862 <td width="60"></td> 1863 <td>0x0600050AC</td> 1864 </tr> 1865 <tr> 1866 <td width="100">1.18.8</td> 1867 <td>reg: <a href="#1.18.8">ENV_FPGA_CC_POR_N_ADDR</a></td> 1868 <td width="60"></td> 1869 <td>0x0600050E0</td> 1870 </tr> 1871 <tr> 1872 <td width="100">1.18.9</td> 1873 <td>reg: <a href="#1.18.9">ENV_FPGA_CC_COLD_RST</a></td> 1874 <td width="60"></td> 1875 <td>0x0600050FC</td> 1876 </tr> 1877 <tr> 1878 <td width="100">1.18.10</td> 1879 <td>reg: <a href="#1.18.10">ENV_FPGA_DUMMY_ADDR</a></td> 1880 <td width="60"></td> 1881 <td>0x060005108</td> 1882 </tr> 1883 <tr> 1884 <td width="100">1.18.11</td> 1885 <td>reg: <a href="#1.18.11">ENV_FPGA_COUNTER_CLR</a></td> 1886 <td width="60"></td> 1887 <td>0x060005118</td> 1888 </tr> 1889 <tr> 1890 <td width="100">1.18.12</td> 1891 <td>reg: <a href="#1.18.12">ENV_FPGA_COUNTER_RD</a></td> 1892 <td width="60"></td> 1893 <td>0x06000511C</td> 1894 </tr> 1895 <tr> 1896 <td width="100">1.18.13</td> 1897 <td>reg: <a href="#1.18.13">ENV_FPGA_RNG_DEBUG_ENABLE</a></td> 1898 <td width="60"></td> 1899 <td>0x060005430</td> 1900 </tr> 1901 <tr> 1902 <td width="100">1.18.14</td> 1903 <td>reg: <a href="#1.18.14">ENV_FPGA_CC_LCS</a></td> 1904 <td width="60"></td> 1905 <td>0x06000543C</td> 1906 </tr> 1907 <tr> 1908 <td width="100">1.18.15</td> 1909 <td>reg: <a href="#1.18.15">ENV_FPGA_CC_IS_CM_DM_SECURE_RMA</a></td> 1910 <td width="60"></td> 1911 <td>0x060005440</td> 1912 </tr> 1913 <tr> 1914 <td width="100">1.18.16</td> 1915 <td>reg: <a href="#1.18.16">ENV_FPGA_DCU_EN</a></td> 1916 <td width="60"></td> 1917 <td>0x060005444</td> 1918 </tr> 1919 <tr> 1920 <td width="100">1.18.17</td> 1921 <td>reg: <a href="#1.18.17">ENV_FPGA_CC_LCS_IS_VALID</a></td> 1922 <td width="60"></td> 1923 <td>0x060005448</td> 1924 </tr> 1925 <tr> 1926 <td width="100">1.18.18</td> 1927 <td>reg: <a href="#1.18.18">ENV_FPGA_POWER_DOWN</a></td> 1928 <td width="60"></td> 1929 <td>0x060005478</td> 1930 </tr> 1931 <tr> 1932 <td width="100">1.18.19</td> 1933 <td>reg: <a href="#1.18.19">ENV_FPGA_DCU_H_EN</a></td> 1934 <td width="60"></td> 1935 <td>0x060005484</td> 1936 </tr> 1937 <tr> 1938 <td width="100">1.18.20</td> 1939 <td>reg: <a href="#1.18.20">ENV_FPGA_VERSION</a></td> 1940 <td width="60"></td> 1941 <td>0x060005488</td> 1942 </tr> 1943 <tr> 1944 <td width="100">1.18.21</td> 1945 <td>reg: <a href="#1.18.21">ENV_FPGA_ROSC_WRITE</a></td> 1946 <td width="60"></td> 1947 <td>0x06000548C</td> 1948 </tr> 1949 <tr> 1950 <td width="100">1.18.22</td> 1951 <td>reg: <a href="#1.18.22">ENV_FPGA_ROSC_ADDR</a></td> 1952 <td width="60"></td> 1953 <td>0x060005490</td> 1954 </tr> 1955 <tr> 1956 <td width="100">1.18.23</td> 1957 <td>reg: <a href="#1.18.23">ENV_FPGA_RESET_SESSION_KEY</a></td> 1958 <td width="60"></td> 1959 <td>0x060005494</td> 1960 </tr> 1961 <tr> 1962 <td width="100">1.18.24</td> 1963 <td>reg: <a href="#1.18.24">ENV_FPGA_SESSION_KEY_0</a></td> 1964 <td width="60"></td> 1965 <td>0x0600054A0</td> 1966 </tr> 1967 <tr> 1968 <td width="100">1.18.25</td> 1969 <td>reg: <a href="#1.18.25">ENV_FPGA_SESSION_KEY_1</a></td> 1970 <td width="60"></td> 1971 <td>0x0600054A4</td> 1972 </tr> 1973 <tr> 1974 <td width="100">1.18.26</td> 1975 <td>reg: <a href="#1.18.26">ENV_FPGA_SESSION_KEY_2</a></td> 1976 <td width="60"></td> 1977 <td>0x0600054A8</td> 1978 </tr> 1979 <tr> 1980 <td width="100">1.18.27</td> 1981 <td>reg: <a href="#1.18.27">ENV_FPGA_SESSION_KEY_3</a></td> 1982 <td width="60"></td> 1983 <td>0x0600054AC</td> 1984 </tr> 1985 <tr> 1986 <td width="100">1.18.28</td> 1987 <td>reg: <a href="#1.18.28">ENV_FPGA_SESSION_KEY_VALID</a></td> 1988 <td width="60"></td> 1989 <td>0x0600054B0</td> 1990 </tr> 1991 <tr> 1992 <td width="100">1.18.29</td> 1993 <td>reg: <a href="#1.18.29">ENV_FPGA_SPIDEN</a></td> 1994 <td width="60"></td> 1995 <td>0x0600054D0</td> 1996 </tr> 1997 <tr> 1998 <td width="100">1.18.30</td> 1999 <td>reg: <a href="#1.18.30">ENV_FPGA_AXIM_USER_PARAMS</a></td> 2000 <td width="60"></td> 2001 <td>0x060005600</td> 2002 </tr> 2003 <tr> 2004 <td width="100">1.18.31</td> 2005 <td>reg: <a href="#1.18.31">ENV_FPGA_SECURITY_MODE_OVERRIDE</a></td> 2006 <td width="60"></td> 2007 <td>0x060005604</td> 2008 </tr> 2009 <tr> 2010 <td width="100">1.18.32</td> 2011 <td>reg: <a href="#1.18.32">ENV_FPGA_SRAM_ENABLE</a></td> 2012 <td width="60"></td> 2013 <td>0x060005608</td> 2014 </tr> 2015 <tr> 2016 <td width="100">1.18.33</td> 2017 <td>reg: <a href="#1.18.33">ENV_FPGA_APB_FIPS_ADDR</a></td> 2018 <td width="60"></td> 2019 <td>0x060005650</td> 2020 </tr> 2021 <tr> 2022 <td width="100">1.18.34</td> 2023 <td>reg: <a href="#1.18.34">ENV_FPGA_APB_FIPS_VAL</a></td> 2024 <td width="60"></td> 2025 <td>0x060005654</td> 2026 </tr> 2027 <tr> 2028 <td width="100">1.18.35</td> 2029 <td>reg: <a href="#1.18.35">ENV_FPGA_APB_FIPS_MASK</a></td> 2030 <td width="60"></td> 2031 <td>0x060005658</td> 2032 </tr> 2033 <tr> 2034 <td width="100">1.18.36</td> 2035 <td>reg: <a href="#1.18.36">ENV_FPGA_APB_FIPS_CNT</a></td> 2036 <td width="60"></td> 2037 <td>0x06000565C</td> 2038 </tr> 2039 <tr> 2040 <td width="100">1.18.37</td> 2041 <td>reg: <a href="#1.18.37">ENV_FPGA_APB_FIPS_NEW_ADDR</a></td> 2042 <td width="60"></td> 2043 <td>0x060005660</td> 2044 </tr> 2045 <tr> 2046 <td width="100">1.18.38</td> 2047 <td>reg: <a href="#1.18.38">ENV_FPGA_APB_FIPS_NEW_VAL</a></td> 2048 <td width="60"></td> 2049 <td>0x060005664</td> 2050 </tr> 2051 <tr> 2052 <td width="100">1.18.39</td> 2053 <td>reg: <a href="#1.18.39">ENV_FPGA_APB_PPROT_OVERRIDE</a></td> 2054 <td width="60"></td> 2055 <td>0x060005668</td> 2056 </tr> 2057 <tr> 2058 <td width="100">1.18.40</td> 2059 <td>reg: <a href="#1.18.40">ENV_FPGA_APBP_FIPS_ADDR</a></td> 2060 <td width="60"></td> 2061 <td>0x060005670</td> 2062 </tr> 2063 <tr> 2064 <td width="100">1.18.41</td> 2065 <td>reg: <a href="#1.18.41">ENV_FPGA_APBP_FIPS_VAL</a></td> 2066 <td width="60"></td> 2067 <td>0x060005674</td> 2068 </tr> 2069 <tr> 2070 <td width="100">1.18.42</td> 2071 <td>reg: <a href="#1.18.42">ENV_FPGA_APBP_FIPS_MASK</a></td> 2072 <td width="60"></td> 2073 <td>0x060005678</td> 2074 </tr> 2075 <tr> 2076 <td width="100">1.18.43</td> 2077 <td>reg: <a href="#1.18.43">ENV_FPGA_APBP_FIPS_CNT</a></td> 2078 <td width="60"></td> 2079 <td>0x06000567C</td> 2080 </tr> 2081 <tr> 2082 <td width="100">1.18.44</td> 2083 <td>reg: <a href="#1.18.44">ENV_FPGA_APBP_FIPS_NEW_ADDR</a></td> 2084 <td width="60"></td> 2085 <td>0x060005680</td> 2086 </tr> 2087 <tr> 2088 <td width="100">1.18.45</td> 2089 <td>reg: <a href="#1.18.45">ENV_FPGA_APBP_FIPS_NEW_VAL</a></td> 2090 <td width="60"></td> 2091 <td>0x060005684</td> 2092 </tr> 2093 <tr> 2094 <td width="100">1.18.46</td> 2095 <td>reg: <a href="#1.18.46">ENV_FPGA_AO_CC_GPPC</a></td> 2096 <td width="60"></td> 2097 <td>0x060005700</td> 2098 </tr> 2099 <tr> 2100 <td width="100">1.19</td> 2101 <td>block: <a href="#1.19">ENV_PERF_RAM_BASE</a></td> 2102 <td width="60"></td> 2103 <td>0x060006000</td> 2104 </tr> 2105 <tr> 2106 <td width="100">1.19.1</td> 2107 <td>reg: <a href="#1.19.1">ENV_PERF_RAM_BASE</a></td> 2108 <td width="60"></td> 2109 <td>0x060006000</td> 2110 </tr> 2111 </table> 2112 </td> 2113 </tr> 2114</table><br><a name="1"></a><table border="0" width="95%" bgcolor="#993333"> 2115 <td><b><font color="#FFFF00" size="+2">1 : Chip: CryptoCell</font></b></td> 2116 <td align="right"><font color="#FFFF00" size="+2">0x000000000</font></td> 2117</table><br><br> 2118Blocks: 2119<br><a href="#1.1">PKA</a><br><a href="#1.2">RNG</a><br><a href="#1.3">CHACHA</a><br><a href="#1.4">AES</a><br><a href="#1.5">HASH</a><br><a href="#1.6">MISC</a><br><a href="#1.7">CC_CTL</a><br><a href="#1.8">GHASH</a><br><a href="#1.9">HOST_RGF</a><br><a href="#1.10">AHB</a><br><a href="#1.11">DIN</a><br><a href="#1.12">DOUT</a><br><a href="#1.13">HOST_SRAM</a><br><a href="#1.14">ID_REGISTERS</a><br><a href="#1.15">AO</a><br><a href="#1.16">NVM</a><br><a href="#1.17">ENV_CC_MEMORIES</a><br><a href="#1.18">FPGA_ENV_REGS</a><br><a href="#1.19">ENV_PERF_RAM_BASE</a><br><a name="1.1"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 2120 <td><b><font color="#000000">1.1 : Block: PKA</font></b></td> 2121 <td align="right"><font color="#000000">0x000000000</font></td> 2122</table><br><a name="1.1.1"></a><br>1.1.1 : <b>Reg : MEMORY_MAP0</b> : 0x000000000<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R0 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2123 <tr> 2124 <td colspan="32" align="center">MEMORY_MAP0</td> 2125 </tr> 2126 <tr></tr> 2127</table> 2128<table border="1" width="800"> 2129 <tr> 2130 <td width="40"><b>bits</b></td> 2131 <td width="100"><b>Field name</b></td> 2132 <td width="20"><b>permission</b></td> 2133 <td width="40"><b>default</b></td> 2134 <td width="600"><b>Description</b></td> 2135 </tr> 2136 <tr> 2137 <td valign="top" align="center"><a name="1.1.1.1"></a>0:0 2138 </td> 2139 <td valign="top">RESERVED0</td> 2140 <td valign="top" align="center">rw</td> 2141 <td valign="top" align="center">0x0</td> 2142 <td valign="top">Reserved</td> 2143 </tr> 2144 <tr> 2145 <td valign="top" align="center"><a name="1.1.1.2"></a>10:1 2146 </td> 2147 <td valign="top">MEMORY_MAP0</td> 2148 <td valign="top" align="center">rw</td> 2149 <td valign="top" align="center">0x0</td> 2150 <td valign="top">Contains the physical address in memory to map the R0 register to.</td> 2151 </tr> 2152 <tr> 2153 <td valign="top" align="center"><a name="1.1.1.3"></a>31:11 2154 </td> 2155 <td valign="top">RESERVED1</td> 2156 <td valign="top" align="center">rw</td> 2157 <td valign="top" align="center">0x0</td> 2158 <td valign="top">Reserved</td> 2159 </tr> 2160</table><a name="1.1.2"></a><br>1.1.2 : <b>Reg : MEMORY_MAP1</b> : 0x000000004<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R1 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2161 <tr> 2162 <td colspan="32" align="center">MEMORY_MAP1</td> 2163 </tr> 2164 <tr></tr> 2165</table> 2166<table border="1" width="800"> 2167 <tr> 2168 <td width="40"><b>bits</b></td> 2169 <td width="100"><b>Field name</b></td> 2170 <td width="20"><b>permission</b></td> 2171 <td width="40"><b>default</b></td> 2172 <td width="600"><b>Description</b></td> 2173 </tr> 2174 <tr> 2175 <td valign="top" align="center"><a name="1.1.2.1"></a>0:0 2176 </td> 2177 <td valign="top">RESERVED0</td> 2178 <td valign="top" align="center">rw</td> 2179 <td valign="top" align="center">0x0</td> 2180 <td valign="top">Reserved</td> 2181 </tr> 2182 <tr> 2183 <td valign="top" align="center"><a name="1.1.2.2"></a>10:1 2184 </td> 2185 <td valign="top">MEMORY_MAP1</td> 2186 <td valign="top" align="center">rw</td> 2187 <td valign="top" align="center">0x0</td> 2188 <td valign="top">Contains the physical address in memory to map the R1 register to.</td> 2189 </tr> 2190 <tr> 2191 <td valign="top" align="center"><a name="1.1.2.3"></a>31:11 2192 </td> 2193 <td valign="top">RESERVED1</td> 2194 <td valign="top" align="center">rw</td> 2195 <td valign="top" align="center">0x0</td> 2196 <td valign="top">Reserved</td> 2197 </tr> 2198</table><a name="1.1.3"></a><br>1.1.3 : <b>Reg : MEMORY_MAP2</b> : 0x000000008<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R2 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2199 <tr> 2200 <td colspan="32" align="center">MEMORY_MAP2</td> 2201 </tr> 2202 <tr></tr> 2203</table> 2204<table border="1" width="800"> 2205 <tr> 2206 <td width="40"><b>bits</b></td> 2207 <td width="100"><b>Field name</b></td> 2208 <td width="20"><b>permission</b></td> 2209 <td width="40"><b>default</b></td> 2210 <td width="600"><b>Description</b></td> 2211 </tr> 2212 <tr> 2213 <td valign="top" align="center"><a name="1.1.3.1"></a>0:0 2214 </td> 2215 <td valign="top">RESERVED0</td> 2216 <td valign="top" align="center">rw</td> 2217 <td valign="top" align="center">0x0</td> 2218 <td valign="top">Reserved</td> 2219 </tr> 2220 <tr> 2221 <td valign="top" align="center"><a name="1.1.3.2"></a>10:1 2222 </td> 2223 <td valign="top">MEMORY_MAP2</td> 2224 <td valign="top" align="center">rw</td> 2225 <td valign="top" align="center">0x0</td> 2226 <td valign="top">Contains the physical address in memory to map the R2 register to.</td> 2227 </tr> 2228 <tr> 2229 <td valign="top" align="center"><a name="1.1.3.3"></a>31:11 2230 </td> 2231 <td valign="top">RESERVED1</td> 2232 <td valign="top" align="center">rw</td> 2233 <td valign="top" align="center">0x0</td> 2234 <td valign="top">Reserved</td> 2235 </tr> 2236</table><a name="1.1.4"></a><br>1.1.4 : <b>Reg : MEMORY_MAP3</b> : 0x00000000C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R3 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2237 <tr> 2238 <td colspan="32" align="center">MEMORY_MAP3</td> 2239 </tr> 2240 <tr></tr> 2241</table> 2242<table border="1" width="800"> 2243 <tr> 2244 <td width="40"><b>bits</b></td> 2245 <td width="100"><b>Field name</b></td> 2246 <td width="20"><b>permission</b></td> 2247 <td width="40"><b>default</b></td> 2248 <td width="600"><b>Description</b></td> 2249 </tr> 2250 <tr> 2251 <td valign="top" align="center"><a name="1.1.4.1"></a>0:0 2252 </td> 2253 <td valign="top">RESERVED0</td> 2254 <td valign="top" align="center">rw</td> 2255 <td valign="top" align="center">0x0</td> 2256 <td valign="top">Reserved</td> 2257 </tr> 2258 <tr> 2259 <td valign="top" align="center"><a name="1.1.4.2"></a>10:1 2260 </td> 2261 <td valign="top">MEMORY_MAP3</td> 2262 <td valign="top" align="center">rw</td> 2263 <td valign="top" align="center">0x0</td> 2264 <td valign="top">Contains the physical address in memory to map the R3 register to.</td> 2265 </tr> 2266 <tr> 2267 <td valign="top" align="center"><a name="1.1.4.3"></a>31:11 2268 </td> 2269 <td valign="top">RESERVED1</td> 2270 <td valign="top" align="center">rw</td> 2271 <td valign="top" align="center">0x0</td> 2272 <td valign="top">Reserved</td> 2273 </tr> 2274</table><a name="1.1.5"></a><br>1.1.5 : <b>Reg : MEMORY_MAP4</b> : 0x000000010<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R4 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2275 <tr> 2276 <td colspan="32" align="center">MEMORY_MAP4</td> 2277 </tr> 2278 <tr></tr> 2279</table> 2280<table border="1" width="800"> 2281 <tr> 2282 <td width="40"><b>bits</b></td> 2283 <td width="100"><b>Field name</b></td> 2284 <td width="20"><b>permission</b></td> 2285 <td width="40"><b>default</b></td> 2286 <td width="600"><b>Description</b></td> 2287 </tr> 2288 <tr> 2289 <td valign="top" align="center"><a name="1.1.5.1"></a>0:0 2290 </td> 2291 <td valign="top">RESERVED0</td> 2292 <td valign="top" align="center">rw</td> 2293 <td valign="top" align="center">0x0</td> 2294 <td valign="top">Reserved</td> 2295 </tr> 2296 <tr> 2297 <td valign="top" align="center"><a name="1.1.5.2"></a>10:1 2298 </td> 2299 <td valign="top">MEMORY_MAP4</td> 2300 <td valign="top" align="center">rw</td> 2301 <td valign="top" align="center">0x0</td> 2302 <td valign="top">Contains the physical address in memory to map the R4 register to.</td> 2303 </tr> 2304 <tr> 2305 <td valign="top" align="center"><a name="1.1.5.3"></a>31:11 2306 </td> 2307 <td valign="top">RESERVED1</td> 2308 <td valign="top" align="center">rw</td> 2309 <td valign="top" align="center">0x0</td> 2310 <td valign="top">Reserved</td> 2311 </tr> 2312</table><a name="1.1.6"></a><br>1.1.6 : <b>Reg : MEMORY_MAP5</b> : 0x000000014<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R5 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2313 <tr> 2314 <td colspan="32" align="center">MEMORY_MAP5</td> 2315 </tr> 2316 <tr></tr> 2317</table> 2318<table border="1" width="800"> 2319 <tr> 2320 <td width="40"><b>bits</b></td> 2321 <td width="100"><b>Field name</b></td> 2322 <td width="20"><b>permission</b></td> 2323 <td width="40"><b>default</b></td> 2324 <td width="600"><b>Description</b></td> 2325 </tr> 2326 <tr> 2327 <td valign="top" align="center"><a name="1.1.6.1"></a>0:0 2328 </td> 2329 <td valign="top">RESERVED0</td> 2330 <td valign="top" align="center">rw</td> 2331 <td valign="top" align="center">0x0</td> 2332 <td valign="top">Reserved</td> 2333 </tr> 2334 <tr> 2335 <td valign="top" align="center"><a name="1.1.6.2"></a>10:1 2336 </td> 2337 <td valign="top">MEMORY_MAP5</td> 2338 <td valign="top" align="center">rw</td> 2339 <td valign="top" align="center">0x0</td> 2340 <td valign="top">Contains the physical address in memory to map the R5 register to.</td> 2341 </tr> 2342 <tr> 2343 <td valign="top" align="center"><a name="1.1.6.3"></a>31:11 2344 </td> 2345 <td valign="top">RESERVED1</td> 2346 <td valign="top" align="center">rw</td> 2347 <td valign="top" align="center">0x0</td> 2348 <td valign="top">Reserved</td> 2349 </tr> 2350</table><a name="1.1.7"></a><br>1.1.7 : <b>Reg : MEMORY_MAP6</b> : 0x000000018<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R6 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2351 <tr> 2352 <td colspan="32" align="center">MEMORY_MAP6</td> 2353 </tr> 2354 <tr></tr> 2355</table> 2356<table border="1" width="800"> 2357 <tr> 2358 <td width="40"><b>bits</b></td> 2359 <td width="100"><b>Field name</b></td> 2360 <td width="20"><b>permission</b></td> 2361 <td width="40"><b>default</b></td> 2362 <td width="600"><b>Description</b></td> 2363 </tr> 2364 <tr> 2365 <td valign="top" align="center"><a name="1.1.7.1"></a>0:0 2366 </td> 2367 <td valign="top">RESERVED0</td> 2368 <td valign="top" align="center">rw</td> 2369 <td valign="top" align="center">0x0</td> 2370 <td valign="top">Reserved</td> 2371 </tr> 2372 <tr> 2373 <td valign="top" align="center"><a name="1.1.7.2"></a>10:1 2374 </td> 2375 <td valign="top">MEMORY_MAP6</td> 2376 <td valign="top" align="center">rw</td> 2377 <td valign="top" align="center">0x0</td> 2378 <td valign="top">Contains the physical address in memory to map the R6 register to.</td> 2379 </tr> 2380 <tr> 2381 <td valign="top" align="center"><a name="1.1.7.3"></a>31:11 2382 </td> 2383 <td valign="top">RESERVED1</td> 2384 <td valign="top" align="center">rw</td> 2385 <td valign="top" align="center">0x0</td> 2386 <td valign="top">Reserved</td> 2387 </tr> 2388</table><a name="1.1.8"></a><br>1.1.8 : <b>Reg : MEMORY_MAP7</b> : 0x00000001C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R7 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2389 <tr> 2390 <td colspan="32" align="center">MEMORY_MAP7</td> 2391 </tr> 2392 <tr></tr> 2393</table> 2394<table border="1" width="800"> 2395 <tr> 2396 <td width="40"><b>bits</b></td> 2397 <td width="100"><b>Field name</b></td> 2398 <td width="20"><b>permission</b></td> 2399 <td width="40"><b>default</b></td> 2400 <td width="600"><b>Description</b></td> 2401 </tr> 2402 <tr> 2403 <td valign="top" align="center"><a name="1.1.8.1"></a>0:0 2404 </td> 2405 <td valign="top">RESERVED0</td> 2406 <td valign="top" align="center">rw</td> 2407 <td valign="top" align="center">0x0</td> 2408 <td valign="top">Reserved</td> 2409 </tr> 2410 <tr> 2411 <td valign="top" align="center"><a name="1.1.8.2"></a>10:1 2412 </td> 2413 <td valign="top">MEMORY_MAP7</td> 2414 <td valign="top" align="center">rw</td> 2415 <td valign="top" align="center">0x0</td> 2416 <td valign="top">Contains the physical address in memory to map the R7 register to.</td> 2417 </tr> 2418 <tr> 2419 <td valign="top" align="center"><a name="1.1.8.3"></a>31:11 2420 </td> 2421 <td valign="top">RESERVED1</td> 2422 <td valign="top" align="center">rw</td> 2423 <td valign="top" align="center">0x0</td> 2424 <td valign="top">Reserved</td> 2425 </tr> 2426</table><a name="1.1.9"></a><br>1.1.9 : <b>Reg : MEMORY_MAP8</b> : 0x000000020<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R8 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2427 <tr> 2428 <td colspan="32" align="center">MEMORY_MAP8</td> 2429 </tr> 2430 <tr></tr> 2431</table> 2432<table border="1" width="800"> 2433 <tr> 2434 <td width="40"><b>bits</b></td> 2435 <td width="100"><b>Field name</b></td> 2436 <td width="20"><b>permission</b></td> 2437 <td width="40"><b>default</b></td> 2438 <td width="600"><b>Description</b></td> 2439 </tr> 2440 <tr> 2441 <td valign="top" align="center"><a name="1.1.9.1"></a>0:0 2442 </td> 2443 <td valign="top">RESERVED0</td> 2444 <td valign="top" align="center">rw</td> 2445 <td valign="top" align="center">0x0</td> 2446 <td valign="top">Reserved</td> 2447 </tr> 2448 <tr> 2449 <td valign="top" align="center"><a name="1.1.9.2"></a>10:1 2450 </td> 2451 <td valign="top">MEMORY_MAP8</td> 2452 <td valign="top" align="center">rw</td> 2453 <td valign="top" align="center">0x0</td> 2454 <td valign="top">Contains the physical address in memory to map the R8 register to.</td> 2455 </tr> 2456 <tr> 2457 <td valign="top" align="center"><a name="1.1.9.3"></a>31:11 2458 </td> 2459 <td valign="top">RESERVED1</td> 2460 <td valign="top" align="center">rw</td> 2461 <td valign="top" align="center">0x0</td> 2462 <td valign="top">Reserved</td> 2463 </tr> 2464</table><a name="1.1.10"></a><br>1.1.10 : <b>Reg : MEMORY_MAP9</b> : 0x000000024<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R9 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2465 <tr> 2466 <td colspan="32" align="center">MEMORY_MAP9</td> 2467 </tr> 2468 <tr></tr> 2469</table> 2470<table border="1" width="800"> 2471 <tr> 2472 <td width="40"><b>bits</b></td> 2473 <td width="100"><b>Field name</b></td> 2474 <td width="20"><b>permission</b></td> 2475 <td width="40"><b>default</b></td> 2476 <td width="600"><b>Description</b></td> 2477 </tr> 2478 <tr> 2479 <td valign="top" align="center"><a name="1.1.10.1"></a>0:0 2480 </td> 2481 <td valign="top">RESERVED0</td> 2482 <td valign="top" align="center">rw</td> 2483 <td valign="top" align="center">0x0</td> 2484 <td valign="top">Reserved</td> 2485 </tr> 2486 <tr> 2487 <td valign="top" align="center"><a name="1.1.10.2"></a>10:1 2488 </td> 2489 <td valign="top">MEMORY_MAP9</td> 2490 <td valign="top" align="center">rw</td> 2491 <td valign="top" align="center">0x0</td> 2492 <td valign="top">Contains the physical address in memory to map the R9 register to.</td> 2493 </tr> 2494 <tr> 2495 <td valign="top" align="center"><a name="1.1.10.3"></a>31:11 2496 </td> 2497 <td valign="top">RESERVED1</td> 2498 <td valign="top" align="center">rw</td> 2499 <td valign="top" align="center">0x0</td> 2500 <td valign="top">Reserved</td> 2501 </tr> 2502</table><a name="1.1.11"></a><br>1.1.11 : <b>Reg : MEMORY_MAP10</b> : 0x000000028<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R10 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2503 <tr> 2504 <td colspan="32" align="center">MEMORY_MAP10</td> 2505 </tr> 2506 <tr></tr> 2507</table> 2508<table border="1" width="800"> 2509 <tr> 2510 <td width="40"><b>bits</b></td> 2511 <td width="100"><b>Field name</b></td> 2512 <td width="20"><b>permission</b></td> 2513 <td width="40"><b>default</b></td> 2514 <td width="600"><b>Description</b></td> 2515 </tr> 2516 <tr> 2517 <td valign="top" align="center"><a name="1.1.11.1"></a>0:0 2518 </td> 2519 <td valign="top">RESERVED0</td> 2520 <td valign="top" align="center">rw</td> 2521 <td valign="top" align="center">0x0</td> 2522 <td valign="top">Reserved</td> 2523 </tr> 2524 <tr> 2525 <td valign="top" align="center"><a name="1.1.11.2"></a>10:1 2526 </td> 2527 <td valign="top">MEMORY_MAP10</td> 2528 <td valign="top" align="center">rw</td> 2529 <td valign="top" align="center">0x0</td> 2530 <td valign="top">Contains the physical address in memory to map the R10 register to.</td> 2531 </tr> 2532 <tr> 2533 <td valign="top" align="center"><a name="1.1.11.3"></a>31:11 2534 </td> 2535 <td valign="top">RESERVED1</td> 2536 <td valign="top" align="center">rw</td> 2537 <td valign="top" align="center">0x0</td> 2538 <td valign="top">Reserved</td> 2539 </tr> 2540</table><a name="1.1.12"></a><br>1.1.12 : <b>Reg : MEMORY_MAP11</b> : 0x00000002C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R11 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2541 <tr> 2542 <td colspan="32" align="center">MEMORY_MAP11</td> 2543 </tr> 2544 <tr></tr> 2545</table> 2546<table border="1" width="800"> 2547 <tr> 2548 <td width="40"><b>bits</b></td> 2549 <td width="100"><b>Field name</b></td> 2550 <td width="20"><b>permission</b></td> 2551 <td width="40"><b>default</b></td> 2552 <td width="600"><b>Description</b></td> 2553 </tr> 2554 <tr> 2555 <td valign="top" align="center"><a name="1.1.12.1"></a>0:0 2556 </td> 2557 <td valign="top">RESERVED0</td> 2558 <td valign="top" align="center">rw</td> 2559 <td valign="top" align="center">0x0</td> 2560 <td valign="top">Reserved</td> 2561 </tr> 2562 <tr> 2563 <td valign="top" align="center"><a name="1.1.12.2"></a>10:1 2564 </td> 2565 <td valign="top">MEMORY_MAP11</td> 2566 <td valign="top" align="center">rw</td> 2567 <td valign="top" align="center">0x0</td> 2568 <td valign="top">Contains the physical address in memory to map the R11 register to.</td> 2569 </tr> 2570 <tr> 2571 <td valign="top" align="center"><a name="1.1.12.3"></a>31:11 2572 </td> 2573 <td valign="top">RESERVED1</td> 2574 <td valign="top" align="center">rw</td> 2575 <td valign="top" align="center">0x0</td> 2576 <td valign="top">Reserved</td> 2577 </tr> 2578</table><a name="1.1.13"></a><br>1.1.13 : <b>Reg : MEMORY_MAP12</b> : 0x000000030<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R12 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2579 <tr> 2580 <td colspan="32" align="center">MEMORY_MAP12</td> 2581 </tr> 2582 <tr></tr> 2583</table> 2584<table border="1" width="800"> 2585 <tr> 2586 <td width="40"><b>bits</b></td> 2587 <td width="100"><b>Field name</b></td> 2588 <td width="20"><b>permission</b></td> 2589 <td width="40"><b>default</b></td> 2590 <td width="600"><b>Description</b></td> 2591 </tr> 2592 <tr> 2593 <td valign="top" align="center"><a name="1.1.13.1"></a>0:0 2594 </td> 2595 <td valign="top">RESERVED0</td> 2596 <td valign="top" align="center">rw</td> 2597 <td valign="top" align="center">0x0</td> 2598 <td valign="top">Reserved</td> 2599 </tr> 2600 <tr> 2601 <td valign="top" align="center"><a name="1.1.13.2"></a>10:1 2602 </td> 2603 <td valign="top">MEMORY_MAP12</td> 2604 <td valign="top" align="center">rw</td> 2605 <td valign="top" align="center">0x0</td> 2606 <td valign="top">Contains the physical address in memory to map the R12 register to.</td> 2607 </tr> 2608 <tr> 2609 <td valign="top" align="center"><a name="1.1.13.3"></a>31:11 2610 </td> 2611 <td valign="top">RESERVED1</td> 2612 <td valign="top" align="center">rw</td> 2613 <td valign="top" align="center">0x0</td> 2614 <td valign="top">Reserved</td> 2615 </tr> 2616</table><a name="1.1.14"></a><br>1.1.14 : <b>Reg : MEMORY_MAP13</b> : 0x000000034<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R13 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2617 <tr> 2618 <td colspan="32" align="center">MEMORY_MAP13</td> 2619 </tr> 2620 <tr></tr> 2621</table> 2622<table border="1" width="800"> 2623 <tr> 2624 <td width="40"><b>bits</b></td> 2625 <td width="100"><b>Field name</b></td> 2626 <td width="20"><b>permission</b></td> 2627 <td width="40"><b>default</b></td> 2628 <td width="600"><b>Description</b></td> 2629 </tr> 2630 <tr> 2631 <td valign="top" align="center"><a name="1.1.14.1"></a>0:0 2632 </td> 2633 <td valign="top">RESERVED0</td> 2634 <td valign="top" align="center">rw</td> 2635 <td valign="top" align="center">0x0</td> 2636 <td valign="top">Reserved</td> 2637 </tr> 2638 <tr> 2639 <td valign="top" align="center"><a name="1.1.14.2"></a>10:1 2640 </td> 2641 <td valign="top">MEMORY_MAP13</td> 2642 <td valign="top" align="center">rw</td> 2643 <td valign="top" align="center">0x0</td> 2644 <td valign="top">Contains the physical address in memory to map the R13 register to.</td> 2645 </tr> 2646 <tr> 2647 <td valign="top" align="center"><a name="1.1.14.3"></a>31:11 2648 </td> 2649 <td valign="top">RESERVED1</td> 2650 <td valign="top" align="center">rw</td> 2651 <td valign="top" align="center">0x0</td> 2652 <td valign="top">Reserved</td> 2653 </tr> 2654</table><a name="1.1.15"></a><br>1.1.15 : <b>Reg : MEMORY_MAP14</b> : 0x000000038<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R14 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2655 <tr> 2656 <td colspan="32" align="center">MEMORY_MAP14</td> 2657 </tr> 2658 <tr></tr> 2659</table> 2660<table border="1" width="800"> 2661 <tr> 2662 <td width="40"><b>bits</b></td> 2663 <td width="100"><b>Field name</b></td> 2664 <td width="20"><b>permission</b></td> 2665 <td width="40"><b>default</b></td> 2666 <td width="600"><b>Description</b></td> 2667 </tr> 2668 <tr> 2669 <td valign="top" align="center"><a name="1.1.15.1"></a>0:0 2670 </td> 2671 <td valign="top">RESERVED0</td> 2672 <td valign="top" align="center">rw</td> 2673 <td valign="top" align="center">0x0</td> 2674 <td valign="top">Reserved</td> 2675 </tr> 2676 <tr> 2677 <td valign="top" align="center"><a name="1.1.15.2"></a>10:1 2678 </td> 2679 <td valign="top">MEMORY_MAP14</td> 2680 <td valign="top" align="center">rw</td> 2681 <td valign="top" align="center">0x0</td> 2682 <td valign="top">Contains the physical address in memory to map the R14 register to.</td> 2683 </tr> 2684 <tr> 2685 <td valign="top" align="center"><a name="1.1.15.3"></a>31:11 2686 </td> 2687 <td valign="top">RESERVED1</td> 2688 <td valign="top" align="center">rw</td> 2689 <td valign="top" align="center">0x0</td> 2690 <td valign="top">Reserved</td> 2691 </tr> 2692</table><a name="1.1.16"></a><br>1.1.16 : <b>Reg : MEMORY_MAP15</b> : 0x00000003C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R15 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2693 <tr> 2694 <td colspan="32" align="center">MEMORY_MAP15</td> 2695 </tr> 2696 <tr></tr> 2697</table> 2698<table border="1" width="800"> 2699 <tr> 2700 <td width="40"><b>bits</b></td> 2701 <td width="100"><b>Field name</b></td> 2702 <td width="20"><b>permission</b></td> 2703 <td width="40"><b>default</b></td> 2704 <td width="600"><b>Description</b></td> 2705 </tr> 2706 <tr> 2707 <td valign="top" align="center"><a name="1.1.16.1"></a>0:0 2708 </td> 2709 <td valign="top">RESERVED0</td> 2710 <td valign="top" align="center">rw</td> 2711 <td valign="top" align="center">0x0</td> 2712 <td valign="top">Reserved</td> 2713 </tr> 2714 <tr> 2715 <td valign="top" align="center"><a name="1.1.16.2"></a>10:1 2716 </td> 2717 <td valign="top">MEMORY_MAP15</td> 2718 <td valign="top" align="center">rw</td> 2719 <td valign="top" align="center">0x0</td> 2720 <td valign="top">Contains the physical address in memory to map the R15 register to.</td> 2721 </tr> 2722 <tr> 2723 <td valign="top" align="center"><a name="1.1.16.3"></a>31:11 2724 </td> 2725 <td valign="top">RESERVED1</td> 2726 <td valign="top" align="center">rw</td> 2727 <td valign="top" align="center">0x0</td> 2728 <td valign="top">Reserved</td> 2729 </tr> 2730</table><a name="1.1.17"></a><br>1.1.17 : <b>Reg : MEMORY_MAP16</b> : 0x000000040<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R16 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2731 <tr> 2732 <td colspan="32" align="center">MEMORY_MAP16</td> 2733 </tr> 2734 <tr></tr> 2735</table> 2736<table border="1" width="800"> 2737 <tr> 2738 <td width="40"><b>bits</b></td> 2739 <td width="100"><b>Field name</b></td> 2740 <td width="20"><b>permission</b></td> 2741 <td width="40"><b>default</b></td> 2742 <td width="600"><b>Description</b></td> 2743 </tr> 2744 <tr> 2745 <td valign="top" align="center"><a name="1.1.17.1"></a>0:0 2746 </td> 2747 <td valign="top">RESERVED0</td> 2748 <td valign="top" align="center">rw</td> 2749 <td valign="top" align="center">0x0</td> 2750 <td valign="top">Reserved</td> 2751 </tr> 2752 <tr> 2753 <td valign="top" align="center"><a name="1.1.17.2"></a>10:1 2754 </td> 2755 <td valign="top">MEMORY_MAP16</td> 2756 <td valign="top" align="center">rw</td> 2757 <td valign="top" align="center">0x0</td> 2758 <td valign="top">Contains the physical address in memory to map the R16 register to.</td> 2759 </tr> 2760 <tr> 2761 <td valign="top" align="center"><a name="1.1.17.3"></a>31:11 2762 </td> 2763 <td valign="top">RESERVED1</td> 2764 <td valign="top" align="center">rw</td> 2765 <td valign="top" align="center">0x0</td> 2766 <td valign="top">Reserved</td> 2767 </tr> 2768</table><a name="1.1.18"></a><br>1.1.18 : <b>Reg : MEMORY_MAP17</b> : 0x000000044<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R17 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2769 <tr> 2770 <td colspan="32" align="center">MEMORY_MAP17</td> 2771 </tr> 2772 <tr></tr> 2773</table> 2774<table border="1" width="800"> 2775 <tr> 2776 <td width="40"><b>bits</b></td> 2777 <td width="100"><b>Field name</b></td> 2778 <td width="20"><b>permission</b></td> 2779 <td width="40"><b>default</b></td> 2780 <td width="600"><b>Description</b></td> 2781 </tr> 2782 <tr> 2783 <td valign="top" align="center"><a name="1.1.18.1"></a>0:0 2784 </td> 2785 <td valign="top">RESERVED0</td> 2786 <td valign="top" align="center">rw</td> 2787 <td valign="top" align="center">0x0</td> 2788 <td valign="top">Reserved</td> 2789 </tr> 2790 <tr> 2791 <td valign="top" align="center"><a name="1.1.18.2"></a>10:1 2792 </td> 2793 <td valign="top">MEMORY_MAP17</td> 2794 <td valign="top" align="center">rw</td> 2795 <td valign="top" align="center">0x0</td> 2796 <td valign="top">Contains the physical address in memory to map the R17 register to.</td> 2797 </tr> 2798 <tr> 2799 <td valign="top" align="center"><a name="1.1.18.3"></a>31:11 2800 </td> 2801 <td valign="top">RESERVED1</td> 2802 <td valign="top" align="center">rw</td> 2803 <td valign="top" align="center">0x0</td> 2804 <td valign="top">Reserved</td> 2805 </tr> 2806</table><a name="1.1.19"></a><br>1.1.19 : <b>Reg : MEMORY_MAP18</b> : 0x000000048<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R18 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2807 <tr> 2808 <td colspan="32" align="center">MEMORY_MAP18</td> 2809 </tr> 2810 <tr></tr> 2811</table> 2812<table border="1" width="800"> 2813 <tr> 2814 <td width="40"><b>bits</b></td> 2815 <td width="100"><b>Field name</b></td> 2816 <td width="20"><b>permission</b></td> 2817 <td width="40"><b>default</b></td> 2818 <td width="600"><b>Description</b></td> 2819 </tr> 2820 <tr> 2821 <td valign="top" align="center"><a name="1.1.19.1"></a>0:0 2822 </td> 2823 <td valign="top">RESERVED0</td> 2824 <td valign="top" align="center">rw</td> 2825 <td valign="top" align="center">0x0</td> 2826 <td valign="top">Reserved</td> 2827 </tr> 2828 <tr> 2829 <td valign="top" align="center"><a name="1.1.19.2"></a>10:1 2830 </td> 2831 <td valign="top">MEMORY_MAP18</td> 2832 <td valign="top" align="center">rw</td> 2833 <td valign="top" align="center">0x0</td> 2834 <td valign="top">Contains the physical address in memory to map the R18 register to.</td> 2835 </tr> 2836 <tr> 2837 <td valign="top" align="center"><a name="1.1.19.3"></a>31:11 2838 </td> 2839 <td valign="top">RESERVED1</td> 2840 <td valign="top" align="center">rw</td> 2841 <td valign="top" align="center">0x0</td> 2842 <td valign="top">Reserved</td> 2843 </tr> 2844</table><a name="1.1.20"></a><br>1.1.20 : <b>Reg : MEMORY_MAP19</b> : 0x00000004C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R19 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2845 <tr> 2846 <td colspan="32" align="center">MEMORY_MAP19</td> 2847 </tr> 2848 <tr></tr> 2849</table> 2850<table border="1" width="800"> 2851 <tr> 2852 <td width="40"><b>bits</b></td> 2853 <td width="100"><b>Field name</b></td> 2854 <td width="20"><b>permission</b></td> 2855 <td width="40"><b>default</b></td> 2856 <td width="600"><b>Description</b></td> 2857 </tr> 2858 <tr> 2859 <td valign="top" align="center"><a name="1.1.20.1"></a>0:0 2860 </td> 2861 <td valign="top">RESERVED0</td> 2862 <td valign="top" align="center">rw</td> 2863 <td valign="top" align="center">0x0</td> 2864 <td valign="top">Reserved</td> 2865 </tr> 2866 <tr> 2867 <td valign="top" align="center"><a name="1.1.20.2"></a>10:1 2868 </td> 2869 <td valign="top">MEMORY_MAP19</td> 2870 <td valign="top" align="center">rw</td> 2871 <td valign="top" align="center">0x0</td> 2872 <td valign="top">Contains the physical address in memory to map the R19 register to.</td> 2873 </tr> 2874 <tr> 2875 <td valign="top" align="center"><a name="1.1.20.3"></a>31:11 2876 </td> 2877 <td valign="top">RESERVED1</td> 2878 <td valign="top" align="center">rw</td> 2879 <td valign="top" align="center">0x0</td> 2880 <td valign="top">Reserved</td> 2881 </tr> 2882</table><a name="1.1.21"></a><br>1.1.21 : <b>Reg : MEMORY_MAP20</b> : 0x000000050<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R20 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2883 <tr> 2884 <td colspan="32" align="center">MEMORY_MAP20</td> 2885 </tr> 2886 <tr></tr> 2887</table> 2888<table border="1" width="800"> 2889 <tr> 2890 <td width="40"><b>bits</b></td> 2891 <td width="100"><b>Field name</b></td> 2892 <td width="20"><b>permission</b></td> 2893 <td width="40"><b>default</b></td> 2894 <td width="600"><b>Description</b></td> 2895 </tr> 2896 <tr> 2897 <td valign="top" align="center"><a name="1.1.21.1"></a>0:0 2898 </td> 2899 <td valign="top">RESERVED0</td> 2900 <td valign="top" align="center">rw</td> 2901 <td valign="top" align="center">0x0</td> 2902 <td valign="top">Reserved</td> 2903 </tr> 2904 <tr> 2905 <td valign="top" align="center"><a name="1.1.21.2"></a>10:1 2906 </td> 2907 <td valign="top">MEMORY_MAP20</td> 2908 <td valign="top" align="center">rw</td> 2909 <td valign="top" align="center">0x0</td> 2910 <td valign="top">Contains the physical address in memory to map the R20 register to.</td> 2911 </tr> 2912 <tr> 2913 <td valign="top" align="center"><a name="1.1.21.3"></a>31:11 2914 </td> 2915 <td valign="top">RESERVED1</td> 2916 <td valign="top" align="center">rw</td> 2917 <td valign="top" align="center">0x0</td> 2918 <td valign="top">Reserved</td> 2919 </tr> 2920</table><a name="1.1.22"></a><br>1.1.22 : <b>Reg : MEMORY_MAP21</b> : 0x000000054<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R21 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2921 <tr> 2922 <td colspan="32" align="center">MEMORY_MAP21</td> 2923 </tr> 2924 <tr></tr> 2925</table> 2926<table border="1" width="800"> 2927 <tr> 2928 <td width="40"><b>bits</b></td> 2929 <td width="100"><b>Field name</b></td> 2930 <td width="20"><b>permission</b></td> 2931 <td width="40"><b>default</b></td> 2932 <td width="600"><b>Description</b></td> 2933 </tr> 2934 <tr> 2935 <td valign="top" align="center"><a name="1.1.22.1"></a>0:0 2936 </td> 2937 <td valign="top">RESERVED0</td> 2938 <td valign="top" align="center">rw</td> 2939 <td valign="top" align="center">0x0</td> 2940 <td valign="top">Reserved</td> 2941 </tr> 2942 <tr> 2943 <td valign="top" align="center"><a name="1.1.22.2"></a>10:1 2944 </td> 2945 <td valign="top">MEMORY_MAP21</td> 2946 <td valign="top" align="center">rw</td> 2947 <td valign="top" align="center">0x0</td> 2948 <td valign="top">Contains the physical address in memory to map the R21 register to.</td> 2949 </tr> 2950 <tr> 2951 <td valign="top" align="center"><a name="1.1.22.3"></a>31:11 2952 </td> 2953 <td valign="top">RESERVED1</td> 2954 <td valign="top" align="center">rw</td> 2955 <td valign="top" align="center">0x0</td> 2956 <td valign="top">Reserved</td> 2957 </tr> 2958</table><a name="1.1.23"></a><br>1.1.23 : <b>Reg : MEMORY_MAP22</b> : 0x000000058<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R22 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2959 <tr> 2960 <td colspan="32" align="center">MEMORY_MAP22</td> 2961 </tr> 2962 <tr></tr> 2963</table> 2964<table border="1" width="800"> 2965 <tr> 2966 <td width="40"><b>bits</b></td> 2967 <td width="100"><b>Field name</b></td> 2968 <td width="20"><b>permission</b></td> 2969 <td width="40"><b>default</b></td> 2970 <td width="600"><b>Description</b></td> 2971 </tr> 2972 <tr> 2973 <td valign="top" align="center"><a name="1.1.23.1"></a>0:0 2974 </td> 2975 <td valign="top">RESERVED0</td> 2976 <td valign="top" align="center">rw</td> 2977 <td valign="top" align="center">0x0</td> 2978 <td valign="top">Reserved</td> 2979 </tr> 2980 <tr> 2981 <td valign="top" align="center"><a name="1.1.23.2"></a>10:1 2982 </td> 2983 <td valign="top">MEMORY_MAP22</td> 2984 <td valign="top" align="center">rw</td> 2985 <td valign="top" align="center">0x0</td> 2986 <td valign="top">Contains the physical address in memory to map the R22 register to.</td> 2987 </tr> 2988 <tr> 2989 <td valign="top" align="center"><a name="1.1.23.3"></a>31:11 2990 </td> 2991 <td valign="top">RESERVED1</td> 2992 <td valign="top" align="center">rw</td> 2993 <td valign="top" align="center">0x0</td> 2994 <td valign="top">Reserved</td> 2995 </tr> 2996</table><a name="1.1.24"></a><br>1.1.24 : <b>Reg : MEMORY_MAP23</b> : 0x00000005C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R23 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 2997 <tr> 2998 <td colspan="32" align="center">MEMORY_MAP23</td> 2999 </tr> 3000 <tr></tr> 3001</table> 3002<table border="1" width="800"> 3003 <tr> 3004 <td width="40"><b>bits</b></td> 3005 <td width="100"><b>Field name</b></td> 3006 <td width="20"><b>permission</b></td> 3007 <td width="40"><b>default</b></td> 3008 <td width="600"><b>Description</b></td> 3009 </tr> 3010 <tr> 3011 <td valign="top" align="center"><a name="1.1.24.1"></a>0:0 3012 </td> 3013 <td valign="top">RESERVED0</td> 3014 <td valign="top" align="center">rw</td> 3015 <td valign="top" align="center">0x0</td> 3016 <td valign="top">Reserved</td> 3017 </tr> 3018 <tr> 3019 <td valign="top" align="center"><a name="1.1.24.2"></a>10:1 3020 </td> 3021 <td valign="top">MEMORY_MAP23</td> 3022 <td valign="top" align="center">rw</td> 3023 <td valign="top" align="center">0x0</td> 3024 <td valign="top">Contains the physical address in memory to map the R23 register to.</td> 3025 </tr> 3026 <tr> 3027 <td valign="top" align="center"><a name="1.1.24.3"></a>31:11 3028 </td> 3029 <td valign="top">RESERVED1</td> 3030 <td valign="top" align="center">rw</td> 3031 <td valign="top" align="center">0x0</td> 3032 <td valign="top">Reserved</td> 3033 </tr> 3034</table><a name="1.1.25"></a><br>1.1.25 : <b>Reg : MEMORY_MAP24</b> : 0x000000060<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R24 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3035 <tr> 3036 <td colspan="32" align="center">MEMORY_MAP24</td> 3037 </tr> 3038 <tr></tr> 3039</table> 3040<table border="1" width="800"> 3041 <tr> 3042 <td width="40"><b>bits</b></td> 3043 <td width="100"><b>Field name</b></td> 3044 <td width="20"><b>permission</b></td> 3045 <td width="40"><b>default</b></td> 3046 <td width="600"><b>Description</b></td> 3047 </tr> 3048 <tr> 3049 <td valign="top" align="center"><a name="1.1.25.1"></a>0:0 3050 </td> 3051 <td valign="top">RESERVED0</td> 3052 <td valign="top" align="center">rw</td> 3053 <td valign="top" align="center">0x0</td> 3054 <td valign="top">Reserved</td> 3055 </tr> 3056 <tr> 3057 <td valign="top" align="center"><a name="1.1.25.2"></a>10:1 3058 </td> 3059 <td valign="top">MEMORY_MAP24</td> 3060 <td valign="top" align="center">rw</td> 3061 <td valign="top" align="center">0x0</td> 3062 <td valign="top">Contains the physical address in memory to map the R24 register to.</td> 3063 </tr> 3064 <tr> 3065 <td valign="top" align="center"><a name="1.1.25.3"></a>31:11 3066 </td> 3067 <td valign="top">RESERVED1</td> 3068 <td valign="top" align="center">rw</td> 3069 <td valign="top" align="center">0x0</td> 3070 <td valign="top">Reserved</td> 3071 </tr> 3072</table><a name="1.1.26"></a><br>1.1.26 : <b>Reg : MEMORY_MAP25</b> : 0x000000064<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R25 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3073 <tr> 3074 <td colspan="32" align="center">MEMORY_MAP25</td> 3075 </tr> 3076 <tr></tr> 3077</table> 3078<table border="1" width="800"> 3079 <tr> 3080 <td width="40"><b>bits</b></td> 3081 <td width="100"><b>Field name</b></td> 3082 <td width="20"><b>permission</b></td> 3083 <td width="40"><b>default</b></td> 3084 <td width="600"><b>Description</b></td> 3085 </tr> 3086 <tr> 3087 <td valign="top" align="center"><a name="1.1.26.1"></a>0:0 3088 </td> 3089 <td valign="top">RESERVED0</td> 3090 <td valign="top" align="center">rw</td> 3091 <td valign="top" align="center">0x0</td> 3092 <td valign="top">Reserved</td> 3093 </tr> 3094 <tr> 3095 <td valign="top" align="center"><a name="1.1.26.2"></a>10:1 3096 </td> 3097 <td valign="top">MEMORY_MAP25</td> 3098 <td valign="top" align="center">rw</td> 3099 <td valign="top" align="center">0x0</td> 3100 <td valign="top">Contains the physical address in memory to map the R25 register to.</td> 3101 </tr> 3102 <tr> 3103 <td valign="top" align="center"><a name="1.1.26.3"></a>31:11 3104 </td> 3105 <td valign="top">RESERVED1</td> 3106 <td valign="top" align="center">rw</td> 3107 <td valign="top" align="center">0x0</td> 3108 <td valign="top">Reserved</td> 3109 </tr> 3110</table><a name="1.1.27"></a><br>1.1.27 : <b>Reg : MEMORY_MAP26</b> : 0x000000068<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R26 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3111 <tr> 3112 <td colspan="32" align="center">MEMORY_MAP26</td> 3113 </tr> 3114 <tr></tr> 3115</table> 3116<table border="1" width="800"> 3117 <tr> 3118 <td width="40"><b>bits</b></td> 3119 <td width="100"><b>Field name</b></td> 3120 <td width="20"><b>permission</b></td> 3121 <td width="40"><b>default</b></td> 3122 <td width="600"><b>Description</b></td> 3123 </tr> 3124 <tr> 3125 <td valign="top" align="center"><a name="1.1.27.1"></a>0:0 3126 </td> 3127 <td valign="top">RESERVED0</td> 3128 <td valign="top" align="center">rw</td> 3129 <td valign="top" align="center">0x0</td> 3130 <td valign="top">Reserved</td> 3131 </tr> 3132 <tr> 3133 <td valign="top" align="center"><a name="1.1.27.2"></a>10:1 3134 </td> 3135 <td valign="top">MEMORY_MAP26</td> 3136 <td valign="top" align="center">rw</td> 3137 <td valign="top" align="center">0x0</td> 3138 <td valign="top">Contains the physical address in memory to map the R26 register to.</td> 3139 </tr> 3140 <tr> 3141 <td valign="top" align="center"><a name="1.1.27.3"></a>31:11 3142 </td> 3143 <td valign="top">RESERVED1</td> 3144 <td valign="top" align="center">rw</td> 3145 <td valign="top" align="center">0x0</td> 3146 <td valign="top">Reserved</td> 3147 </tr> 3148</table><a name="1.1.28"></a><br>1.1.28 : <b>Reg : MEMORY_MAP27</b> : 0x00000006C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R27 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3149 <tr> 3150 <td colspan="32" align="center">MEMORY_MAP27</td> 3151 </tr> 3152 <tr></tr> 3153</table> 3154<table border="1" width="800"> 3155 <tr> 3156 <td width="40"><b>bits</b></td> 3157 <td width="100"><b>Field name</b></td> 3158 <td width="20"><b>permission</b></td> 3159 <td width="40"><b>default</b></td> 3160 <td width="600"><b>Description</b></td> 3161 </tr> 3162 <tr> 3163 <td valign="top" align="center"><a name="1.1.28.1"></a>0:0 3164 </td> 3165 <td valign="top">RESERVED0</td> 3166 <td valign="top" align="center">rw</td> 3167 <td valign="top" align="center">0x0</td> 3168 <td valign="top">Reserved</td> 3169 </tr> 3170 <tr> 3171 <td valign="top" align="center"><a name="1.1.28.2"></a>10:1 3172 </td> 3173 <td valign="top">MEMORY_MAP27</td> 3174 <td valign="top" align="center">rw</td> 3175 <td valign="top" align="center">0x0</td> 3176 <td valign="top">Contains the physical address in memory to map the R27 register to.</td> 3177 </tr> 3178 <tr> 3179 <td valign="top" align="center"><a name="1.1.28.3"></a>31:11 3180 </td> 3181 <td valign="top">RESERVED1</td> 3182 <td valign="top" align="center">rw</td> 3183 <td valign="top" align="center">0x0</td> 3184 <td valign="top">Reserved</td> 3185 </tr> 3186</table><a name="1.1.29"></a><br>1.1.29 : <b>Reg : MEMORY_MAP28</b> : 0x000000070<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R28 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3187 <tr> 3188 <td colspan="32" align="center">MEMORY_MAP28</td> 3189 </tr> 3190 <tr></tr> 3191</table> 3192<table border="1" width="800"> 3193 <tr> 3194 <td width="40"><b>bits</b></td> 3195 <td width="100"><b>Field name</b></td> 3196 <td width="20"><b>permission</b></td> 3197 <td width="40"><b>default</b></td> 3198 <td width="600"><b>Description</b></td> 3199 </tr> 3200 <tr> 3201 <td valign="top" align="center"><a name="1.1.29.1"></a>0:0 3202 </td> 3203 <td valign="top">RESERVED0</td> 3204 <td valign="top" align="center">rw</td> 3205 <td valign="top" align="center">0x0</td> 3206 <td valign="top">Reserved</td> 3207 </tr> 3208 <tr> 3209 <td valign="top" align="center"><a name="1.1.29.2"></a>10:1 3210 </td> 3211 <td valign="top">MEMORY_MAP28</td> 3212 <td valign="top" align="center">rw</td> 3213 <td valign="top" align="center">0x0</td> 3214 <td valign="top">Contains the physical address in memory to map the R28 register to.</td> 3215 </tr> 3216 <tr> 3217 <td valign="top" align="center"><a name="1.1.29.3"></a>31:11 3218 </td> 3219 <td valign="top">RESERVED1</td> 3220 <td valign="top" align="center">rw</td> 3221 <td valign="top" align="center">0x0</td> 3222 <td valign="top">Reserved</td> 3223 </tr> 3224</table><a name="1.1.30"></a><br>1.1.30 : <b>Reg : MEMORY_MAP29</b> : 0x000000074<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R29 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3225 <tr> 3226 <td colspan="32" align="center">MEMORY_MAP29</td> 3227 </tr> 3228 <tr></tr> 3229</table> 3230<table border="1" width="800"> 3231 <tr> 3232 <td width="40"><b>bits</b></td> 3233 <td width="100"><b>Field name</b></td> 3234 <td width="20"><b>permission</b></td> 3235 <td width="40"><b>default</b></td> 3236 <td width="600"><b>Description</b></td> 3237 </tr> 3238 <tr> 3239 <td valign="top" align="center"><a name="1.1.30.1"></a>0:0 3240 </td> 3241 <td valign="top">RESERVED0</td> 3242 <td valign="top" align="center">rw</td> 3243 <td valign="top" align="center">0x0</td> 3244 <td valign="top">Reserved</td> 3245 </tr> 3246 <tr> 3247 <td valign="top" align="center"><a name="1.1.30.2"></a>10:1 3248 </td> 3249 <td valign="top">MEMORY_MAP29</td> 3250 <td valign="top" align="center">rw</td> 3251 <td valign="top" align="center">0x0</td> 3252 <td valign="top">Contains the physical address in memory to map the R29 register to.</td> 3253 </tr> 3254 <tr> 3255 <td valign="top" align="center"><a name="1.1.30.3"></a>31:11 3256 </td> 3257 <td valign="top">RESERVED1</td> 3258 <td valign="top" align="center">rw</td> 3259 <td valign="top" align="center">0x0</td> 3260 <td valign="top">Reserved</td> 3261 </tr> 3262</table><a name="1.1.31"></a><br>1.1.31 : <b>Reg : MEMORY_MAP30</b> : 0x000000078<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R30 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3263 <tr> 3264 <td colspan="32" align="center">MEMORY_MAP30</td> 3265 </tr> 3266 <tr></tr> 3267</table> 3268<table border="1" width="800"> 3269 <tr> 3270 <td width="40"><b>bits</b></td> 3271 <td width="100"><b>Field name</b></td> 3272 <td width="20"><b>permission</b></td> 3273 <td width="40"><b>default</b></td> 3274 <td width="600"><b>Description</b></td> 3275 </tr> 3276 <tr> 3277 <td valign="top" align="center"><a name="1.1.31.1"></a>0:0 3278 </td> 3279 <td valign="top">RESERVED0</td> 3280 <td valign="top" align="center">rw</td> 3281 <td valign="top" align="center">0x0</td> 3282 <td valign="top">Reserved</td> 3283 </tr> 3284 <tr> 3285 <td valign="top" align="center"><a name="1.1.31.2"></a>10:1 3286 </td> 3287 <td valign="top">MEMORY_MAP30</td> 3288 <td valign="top" align="center">rw</td> 3289 <td valign="top" align="center">0x0</td> 3290 <td valign="top">Contains the physical address in memory to map the R30 register to.</td> 3291 </tr> 3292 <tr> 3293 <td valign="top" align="center"><a name="1.1.31.3"></a>31:11 3294 </td> 3295 <td valign="top">RESERVED1</td> 3296 <td valign="top" align="center">rw</td> 3297 <td valign="top" align="center">0x0</td> 3298 <td valign="top">Reserved</td> 3299 </tr> 3300</table><a name="1.1.32"></a><br>1.1.32 : <b>Reg : MEMORY_MAP31</b> : 0x00000007C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual register R31 to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3301 <tr> 3302 <td colspan="32" align="center">MEMORY_MAP31</td> 3303 </tr> 3304 <tr></tr> 3305</table> 3306<table border="1" width="800"> 3307 <tr> 3308 <td width="40"><b>bits</b></td> 3309 <td width="100"><b>Field name</b></td> 3310 <td width="20"><b>permission</b></td> 3311 <td width="40"><b>default</b></td> 3312 <td width="600"><b>Description</b></td> 3313 </tr> 3314 <tr> 3315 <td valign="top" align="center"><a name="1.1.32.1"></a>0:0 3316 </td> 3317 <td valign="top">RESERVED0</td> 3318 <td valign="top" align="center">rw</td> 3319 <td valign="top" align="center">0x0</td> 3320 <td valign="top">Reserved</td> 3321 </tr> 3322 <tr> 3323 <td valign="top" align="center"><a name="1.1.32.2"></a>10:1 3324 </td> 3325 <td valign="top">MEMORY_MAP31</td> 3326 <td valign="top" align="center">rw</td> 3327 <td valign="top" align="center">0x0</td> 3328 <td valign="top">Contains the physical address in memory to map the R31 register to.</td> 3329 </tr> 3330 <tr> 3331 <td valign="top" align="center"><a name="1.1.32.3"></a>31:11 3332 </td> 3333 <td valign="top">RESERVED1</td> 3334 <td valign="top" align="center">rw</td> 3335 <td valign="top" align="center">0x0</td> 3336 <td valign="top">Reserved</td> 3337 </tr> 3338</table><a name="1.1.33"></a><br>1.1.33 : <b>Reg : OPCODE</b> : 0x000000080<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the PKA's OPCODE.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3339 <tr> 3340 <td colspan="32" align="center">OPCODE</td> 3341 </tr> 3342 <tr></tr> 3343</table> 3344<table border="1" width="800"> 3345 <tr> 3346 <td width="40"><b>bits</b></td> 3347 <td width="100"><b>Field name</b></td> 3348 <td width="20"><b>permission</b></td> 3349 <td width="40"><b>default</b></td> 3350 <td width="600"><b>Description</b></td> 3351 </tr> 3352 <tr> 3353 <td valign="top" align="center"><a name="1.1.33.1"></a>5:0 3354 </td> 3355 <td valign="top">TAG</td> 3356 <td valign="top" align="center">rw</td> 3357 <td valign="top" align="center">0x0</td> 3358 <td valign="top">Holds the opreation's tag or the operand C virtual address.</td> 3359 </tr> 3360 <tr> 3361 <td valign="top" align="center"><a name="1.1.33.2"></a>11:6 3362 </td> 3363 <td valign="top">REG_R</td> 3364 <td valign="top" align="center">rw</td> 3365 <td valign="top" align="center">0x0</td> 3366 <td valign="top">Result register virtual address 0-15.</td> 3367 </tr> 3368 <tr> 3369 <td valign="top" align="center"><a name="1.1.33.3"></a>17:12 3370 </td> 3371 <td valign="top">REG_B</td> 3372 <td valign="top" align="center">rw</td> 3373 <td valign="top" align="center">0x0</td> 3374 <td valign="top">Operand B virtual address 0-15.</td> 3375 </tr> 3376 <tr> 3377 <td valign="top" align="center"><a name="1.1.33.4"></a>23:18 3378 </td> 3379 <td valign="top">REG_A</td> 3380 <td valign="top" align="center">rw</td> 3381 <td valign="top" align="center">0x0</td> 3382 <td valign="top">Operand A virtual address 0-15.</td> 3383 </tr> 3384 <tr> 3385 <td valign="top" align="center"><a name="1.1.33.5"></a>26:24 3386 </td> 3387 <td valign="top">LEN</td> 3388 <td valign="top" align="center">rw</td> 3389 <td valign="top" align="center">0x0</td> 3390 <td valign="top">The length of the operation. The value serves as a pointer to PKA length register, for example, if the value is 0, PKA_L0 3391 holds the size of the operation. 3392 </td> 3393 </tr> 3394 <tr> 3395 <td valign="top" align="center"><a name="1.1.33.6"></a>31:27 3396 </td> 3397 <td valign="top">OPCODE</td> 3398 <td valign="top" align="center">rw</td> 3399 <td valign="top" align="center">0x0</td> 3400 <td valign="top">Defines the PKA operation:<br>@0x4 - Add,Inc<br>@0x5 - Sub,Dec,Neg<br>@0x6 - ModAdd,ModInc<br>@0x7 - ModSub,ModDec,ModNeg<br>@0x8 - AND,TST0,CLR0<br>@0x9 - OR,COPY,SET0<br>@0xa - XOR,FLIP0,INVERT,COMPARE<br>@0xc - SHR0<br>@0xd - SHR1<br>@0xe - SHL0<br>@0xf - SHL1<br>@0x10 - MulLow<br>@0x11 - ModMul<br>@0x12 - ModMulN<br>@0x13 - ModExp<br>@0x14 - Division<br>@0x15 - Div<br>@0x16 - ModDiv<br>@0x00 - Terminate 3401 </td> 3402 </tr> 3403</table><a name="1.1.34"></a><br>1.1.34 : <b>Reg : N_NP_T0_T1_ADDR</b> : 0x000000084<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps N_NP_T0_T1 to a virtual address.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3404 <tr> 3405 <td colspan="32" align="center">N_NP_T0_T1_ADDR</td> 3406 </tr> 3407 <tr></tr> 3408</table> 3409<table border="1" width="800"> 3410 <tr> 3411 <td width="40"><b>bits</b></td> 3412 <td width="100"><b>Field name</b></td> 3413 <td width="20"><b>permission</b></td> 3414 <td width="40"><b>default</b></td> 3415 <td width="600"><b>Description</b></td> 3416 </tr> 3417 <tr> 3418 <td valign="top" align="center"><a name="1.1.34.1"></a>4:0 3419 </td> 3420 <td valign="top">N_VIRTUAL_ADDR</td> 3421 <td valign="top" align="center">rw</td> 3422 <td valign="top" align="center">0x0</td> 3423 <td valign="top">Virtual address of register N.</td> 3424 </tr> 3425 <tr> 3426 <td valign="top" align="center"><a name="1.1.34.2"></a>9:5 3427 </td> 3428 <td valign="top">NP_VIRTUAL_ADDR</td> 3429 <td valign="top" align="center">rw</td> 3430 <td valign="top" align="center">0x1</td> 3431 <td valign="top">Virtual address of register NP.</td> 3432 </tr> 3433 <tr> 3434 <td valign="top" align="center"><a name="1.1.34.3"></a>14:10 3435 </td> 3436 <td valign="top">T0_VIRTUAL_ADDR</td> 3437 <td valign="top" align="center">rw</td> 3438 <td valign="top" align="center">0x</td> 3439 <td valign="top">Virtual address of temporary register number 0</td> 3440 </tr> 3441 <tr> 3442 <td valign="top" align="center"><a name="1.1.34.4"></a>19:15 3443 </td> 3444 <td valign="top">T1_VIRTUAL_ADDR</td> 3445 <td valign="top" align="center">rw</td> 3446 <td valign="top" align="center">0x</td> 3447 <td valign="top">Virtual address of temporary register number 1</td> 3448 </tr> 3449 <tr> 3450 <td valign="top" align="center"><a name="1.1.34.5"></a>31:20 3451 </td> 3452 <td valign="top">Reserved</td> 3453 <td valign="top" align="center">rw</td> 3454 <td valign="top" align="center">0x0</td> 3455 <td valign="top">Reserved</td> 3456 </tr> 3457</table><a name="1.1.35"></a><br>1.1.35 : <b>Reg : PKA_STATUS</b> : 0x000000088<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the PKA pipe status.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3458 <tr> 3459 <td colspan="32" align="center">PKA_STATUS</td> 3460 </tr> 3461 <tr></tr> 3462</table> 3463<table border="1" width="800"> 3464 <tr> 3465 <td width="40"><b>bits</b></td> 3466 <td width="100"><b>Field name</b></td> 3467 <td width="20"><b>permission</b></td> 3468 <td width="40"><b>default</b></td> 3469 <td width="600"><b>Description</b></td> 3470 </tr> 3471 <tr> 3472 <td valign="top" align="center"><a name="1.1.35.1"></a>3:0 3473 </td> 3474 <td valign="top">ALU_MSB_4BITS</td> 3475 <td valign="top" align="center">ro</td> 3476 <td valign="top" align="center">0x0</td> 3477 <td valign="top">The most significant 4-bits of the operand updated in shift operation.</td> 3478 </tr> 3479 <tr> 3480 <td valign="top" align="center"><a name="1.1.35.2"></a>7:4 3481 </td> 3482 <td valign="top">ALU_LSB_4BITS</td> 3483 <td valign="top" align="center">ro</td> 3484 <td valign="top" align="center">0x0</td> 3485 <td valign="top">The least significant 4-bits of the operand updated in shift operation.</td> 3486 </tr> 3487 <tr> 3488 <td valign="top" align="center"><a name="1.1.35.3"></a>8:8 3489 </td> 3490 <td valign="top">ALU_SIGN_OUT</td> 3491 <td valign="top" align="center">ro</td> 3492 <td valign="top" align="center">0x0</td> 3493 <td valign="top">Indicates the last operation's sign (MSB).</td> 3494 </tr> 3495 <tr> 3496 <td valign="top" align="center"><a name="1.1.35.4"></a>9:9 3497 </td> 3498 <td valign="top">ALU_CARRY</td> 3499 <td valign="top" align="center">ro</td> 3500 <td valign="top" align="center">0x0</td> 3501 <td valign="top">Holds the carry of the last ALU operation.</td> 3502 </tr> 3503 <tr> 3504 <td valign="top" align="center"><a name="1.1.35.5"></a>10:10 3505 </td> 3506 <td valign="top">ALU_CARRY_MOD</td> 3507 <td valign="top" align="center">ro</td> 3508 <td valign="top" align="center">0x0</td> 3509 <td valign="top">holds the carry of the last Modular operation.</td> 3510 </tr> 3511 <tr> 3512 <td valign="top" align="center"><a name="1.1.35.6"></a>11:11 3513 </td> 3514 <td valign="top">ALU_SUB_IS_ZERO</td> 3515 <td valign="top" align="center">ro</td> 3516 <td valign="top" align="center">0x0</td> 3517 <td valign="top">Indicates the last subtraction operation's sign .</td> 3518 </tr> 3519 <tr> 3520 <td valign="top" align="center"><a name="1.1.35.7"></a>12:12 3521 </td> 3522 <td valign="top">ALU_OUT_ZERO</td> 3523 <td valign="top" align="center">ro</td> 3524 <td valign="top" align="center">0x1</td> 3525 <td valign="top">Indicates if the result of ALU OUT is zero.</td> 3526 </tr> 3527 <tr> 3528 <td valign="top" align="center"><a name="1.1.35.8"></a>13:13 3529 </td> 3530 <td valign="top">ALU_MODOVRFLW</td> 3531 <td valign="top" align="center">ro</td> 3532 <td valign="top" align="center">0x0</td> 3533 <td valign="top">Modular overflow flag.</td> 3534 </tr> 3535 <tr> 3536 <td valign="top" align="center"><a name="1.1.35.9"></a>14:14 3537 </td> 3538 <td valign="top">DIV_BY_ZERO</td> 3539 <td valign="top" align="center">ro</td> 3540 <td valign="top" align="center">0x0</td> 3541 <td valign="top">Indication if the division is done by zero.</td> 3542 </tr> 3543 <tr> 3544 <td valign="top" align="center"><a name="1.1.35.10"></a>15:15 3545 </td> 3546 <td valign="top">MODINV_OF_ZERO</td> 3547 <td valign="top" align="center">ro</td> 3548 <td valign="top" align="center">0x0</td> 3549 <td valign="top">Indicates the Modular inverse of zero.</td> 3550 </tr> 3551 <tr> 3552 <td valign="top" align="center"><a name="1.1.35.11"></a>20:16 3553 </td> 3554 <td valign="top">OPCODE</td> 3555 <td valign="top" align="center">ro</td> 3556 <td valign="top" align="center">0x0</td> 3557 <td valign="top">Opcode of the last operation</td> 3558 </tr> 3559 <tr> 3560 <td valign="top" align="center"><a name="1.1.35.12"></a>31:21 3561 </td> 3562 <td valign="top">RESERVED</td> 3563 <td valign="top" align="center">ro</td> 3564 <td valign="top" align="center">0x0</td> 3565 <td valign="top">Reserved</td> 3566 </tr> 3567</table><a name="1.1.36"></a><br>1.1.36 : <b>Reg : PKA_SW_RESET</b> : 0x00000008C<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this register triggers a software reset of the PKA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3568 <tr> 3569 <td colspan="32" align="center">PKA_SW_RESET</td> 3570 </tr> 3571 <tr></tr> 3572</table> 3573<table border="1" width="800"> 3574 <tr> 3575 <td width="40"><b>bits</b></td> 3576 <td width="100"><b>Field name</b></td> 3577 <td width="20"><b>permission</b></td> 3578 <td width="40"><b>default</b></td> 3579 <td width="600"><b>Description</b></td> 3580 </tr> 3581 <tr> 3582 <td valign="top" align="center"><a name="1.1.36.1"></a>0:0 3583 </td> 3584 <td valign="top">PKA_SW_RESET</td> 3585 <td valign="top" align="center">wo</td> 3586 <td valign="top" align="center">0x0</td> 3587 <td valign="top">The reset mechanism takes about four PKA clock cycles until the reset line is deasserted</td> 3588 </tr> 3589 <tr> 3590 <td valign="top" align="center"><a name="1.1.36.2"></a>31:1 3591 </td> 3592 <td valign="top">RESERVED</td> 3593 <td valign="top" align="center">wo</td> 3594 <td valign="top" align="center">0x0</td> 3595 <td valign="top">Reserved</td> 3596 </tr> 3597</table><a name="1.1.37"></a><br>1.1.37 : <b>Reg : PKA_L0</b> : 0x000000090<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3598 <tr> 3599 <td colspan="32" align="center">PKA_L0</td> 3600 </tr> 3601 <tr></tr> 3602</table> 3603<table border="1" width="800"> 3604 <tr> 3605 <td width="40"><b>bits</b></td> 3606 <td width="100"><b>Field name</b></td> 3607 <td width="20"><b>permission</b></td> 3608 <td width="40"><b>default</b></td> 3609 <td width="600"><b>Description</b></td> 3610 </tr> 3611 <tr> 3612 <td valign="top" align="center"><a name="1.1.37.1"></a>12:0 3613 </td> 3614 <td valign="top">PKA_L0</td> 3615 <td valign="top" align="center">rw</td> 3616 <td valign="top" align="center">0x0</td> 3617 <td valign="top">Size of the operation in bytes.</td> 3618 </tr> 3619 <tr> 3620 <td valign="top" align="center"><a name="1.1.37.2"></a>31:13 3621 </td> 3622 <td valign="top">RESERVED</td> 3623 <td valign="top" align="center">rw</td> 3624 <td valign="top" align="center">0x0</td> 3625 <td valign="top">Reserved</td> 3626 </tr> 3627</table><a name="1.1.38"></a><br>1.1.38 : <b>Reg : PKA_L1</b> : 0x000000094<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3628 <tr> 3629 <td colspan="32" align="center">PKA_L1</td> 3630 </tr> 3631 <tr></tr> 3632</table> 3633<table border="1" width="800"> 3634 <tr> 3635 <td width="40"><b>bits</b></td> 3636 <td width="100"><b>Field name</b></td> 3637 <td width="20"><b>permission</b></td> 3638 <td width="40"><b>default</b></td> 3639 <td width="600"><b>Description</b></td> 3640 </tr> 3641 <tr> 3642 <td valign="top" align="center"><a name="1.1.38.1"></a>12:0 3643 </td> 3644 <td valign="top">PKA_L1</td> 3645 <td valign="top" align="center">rw</td> 3646 <td valign="top" align="center">0x0</td> 3647 <td valign="top">Size of the operation in bytes.</td> 3648 </tr> 3649 <tr> 3650 <td valign="top" align="center"><a name="1.1.38.2"></a>31:13 3651 </td> 3652 <td valign="top">RESERVED</td> 3653 <td valign="top" align="center">rw</td> 3654 <td valign="top" align="center">0x0</td> 3655 <td valign="top">Reserved</td> 3656 </tr> 3657</table><a name="1.1.39"></a><br>1.1.39 : <b>Reg : PKA_L2</b> : 0x000000098<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3658 <tr> 3659 <td colspan="32" align="center">PKA_L2</td> 3660 </tr> 3661 <tr></tr> 3662</table> 3663<table border="1" width="800"> 3664 <tr> 3665 <td width="40"><b>bits</b></td> 3666 <td width="100"><b>Field name</b></td> 3667 <td width="20"><b>permission</b></td> 3668 <td width="40"><b>default</b></td> 3669 <td width="600"><b>Description</b></td> 3670 </tr> 3671 <tr> 3672 <td valign="top" align="center"><a name="1.1.39.1"></a>12:0 3673 </td> 3674 <td valign="top">PKA_L2</td> 3675 <td valign="top" align="center">rw</td> 3676 <td valign="top" align="center">0x0</td> 3677 <td valign="top">Size of the operation in bytes.</td> 3678 </tr> 3679 <tr> 3680 <td valign="top" align="center"><a name="1.1.39.2"></a>31:13 3681 </td> 3682 <td valign="top">RESERVED</td> 3683 <td valign="top" align="center">rw</td> 3684 <td valign="top" align="center">0x0</td> 3685 <td valign="top">Reserved</td> 3686 </tr> 3687</table><a name="1.1.40"></a><br>1.1.40 : <b>Reg : PKA_L3</b> : 0x00000009C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3688 <tr> 3689 <td colspan="32" align="center">PKA_L3</td> 3690 </tr> 3691 <tr></tr> 3692</table> 3693<table border="1" width="800"> 3694 <tr> 3695 <td width="40"><b>bits</b></td> 3696 <td width="100"><b>Field name</b></td> 3697 <td width="20"><b>permission</b></td> 3698 <td width="40"><b>default</b></td> 3699 <td width="600"><b>Description</b></td> 3700 </tr> 3701 <tr> 3702 <td valign="top" align="center"><a name="1.1.40.1"></a>12:0 3703 </td> 3704 <td valign="top">PKA_L3</td> 3705 <td valign="top" align="center">rw</td> 3706 <td valign="top" align="center">0x0</td> 3707 <td valign="top">Size of the operation in bytes.</td> 3708 </tr> 3709 <tr> 3710 <td valign="top" align="center"><a name="1.1.40.2"></a>31:13 3711 </td> 3712 <td valign="top">RESERVED</td> 3713 <td valign="top" align="center">rw</td> 3714 <td valign="top" align="center">0x0</td> 3715 <td valign="top">Reserved</td> 3716 </tr> 3717</table><a name="1.1.41"></a><br>1.1.41 : <b>Reg : PKA_L4</b> : 0x0000000A0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3718 <tr> 3719 <td colspan="32" align="center">PKA_L4</td> 3720 </tr> 3721 <tr></tr> 3722</table> 3723<table border="1" width="800"> 3724 <tr> 3725 <td width="40"><b>bits</b></td> 3726 <td width="100"><b>Field name</b></td> 3727 <td width="20"><b>permission</b></td> 3728 <td width="40"><b>default</b></td> 3729 <td width="600"><b>Description</b></td> 3730 </tr> 3731 <tr> 3732 <td valign="top" align="center"><a name="1.1.41.1"></a>12:0 3733 </td> 3734 <td valign="top">PKA_L4</td> 3735 <td valign="top" align="center">rw</td> 3736 <td valign="top" align="center">0x0</td> 3737 <td valign="top">Size of the operation in bytes.</td> 3738 </tr> 3739 <tr> 3740 <td valign="top" align="center"><a name="1.1.41.2"></a>31:13 3741 </td> 3742 <td valign="top">RESERVED</td> 3743 <td valign="top" align="center">rw</td> 3744 <td valign="top" align="center">0x0</td> 3745 <td valign="top">Reserved</td> 3746 </tr> 3747</table><a name="1.1.42"></a><br>1.1.42 : <b>Reg : PKA_L5</b> : 0x0000000A4<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3748 <tr> 3749 <td colspan="32" align="center">PKA_L5</td> 3750 </tr> 3751 <tr></tr> 3752</table> 3753<table border="1" width="800"> 3754 <tr> 3755 <td width="40"><b>bits</b></td> 3756 <td width="100"><b>Field name</b></td> 3757 <td width="20"><b>permission</b></td> 3758 <td width="40"><b>default</b></td> 3759 <td width="600"><b>Description</b></td> 3760 </tr> 3761 <tr> 3762 <td valign="top" align="center"><a name="1.1.42.1"></a>12:0 3763 </td> 3764 <td valign="top">PKA_L5</td> 3765 <td valign="top" align="center">rw</td> 3766 <td valign="top" align="center">0x0</td> 3767 <td valign="top">Size of the operation in bytes.</td> 3768 </tr> 3769 <tr> 3770 <td valign="top" align="center"><a name="1.1.42.2"></a>31:13 3771 </td> 3772 <td valign="top">RESERVED</td> 3773 <td valign="top" align="center">rw</td> 3774 <td valign="top" align="center">0x0</td> 3775 <td valign="top">Reserved</td> 3776 </tr> 3777</table><a name="1.1.43"></a><br>1.1.43 : <b>Reg : PKA_L6</b> : 0x0000000A8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3778 <tr> 3779 <td colspan="32" align="center">PKA_L6</td> 3780 </tr> 3781 <tr></tr> 3782</table> 3783<table border="1" width="800"> 3784 <tr> 3785 <td width="40"><b>bits</b></td> 3786 <td width="100"><b>Field name</b></td> 3787 <td width="20"><b>permission</b></td> 3788 <td width="40"><b>default</b></td> 3789 <td width="600"><b>Description</b></td> 3790 </tr> 3791 <tr> 3792 <td valign="top" align="center"><a name="1.1.43.1"></a>12:0 3793 </td> 3794 <td valign="top">PKA_L6</td> 3795 <td valign="top" align="center">rw</td> 3796 <td valign="top" align="center">0x0</td> 3797 <td valign="top">Size of the operation in bytes.</td> 3798 </tr> 3799 <tr> 3800 <td valign="top" align="center"><a name="1.1.43.2"></a>31:13 3801 </td> 3802 <td valign="top">RESERVED</td> 3803 <td valign="top" align="center">rw</td> 3804 <td valign="top" align="center">0x0</td> 3805 <td valign="top">Reserved</td> 3806 </tr> 3807</table><a name="1.1.44"></a><br>1.1.44 : <b>Reg : PKA_L7</b> : 0x0000000AC<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds one of the optional size of the operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3808 <tr> 3809 <td colspan="32" align="center">PKA_L7</td> 3810 </tr> 3811 <tr></tr> 3812</table> 3813<table border="1" width="800"> 3814 <tr> 3815 <td width="40"><b>bits</b></td> 3816 <td width="100"><b>Field name</b></td> 3817 <td width="20"><b>permission</b></td> 3818 <td width="40"><b>default</b></td> 3819 <td width="600"><b>Description</b></td> 3820 </tr> 3821 <tr> 3822 <td valign="top" align="center"><a name="1.1.44.1"></a>12:0 3823 </td> 3824 <td valign="top">PKA_L7</td> 3825 <td valign="top" align="center">rw</td> 3826 <td valign="top" align="center">0x0</td> 3827 <td valign="top">Size of the operation in bytes.</td> 3828 </tr> 3829 <tr> 3830 <td valign="top" align="center"><a name="1.1.44.2"></a>31:13 3831 </td> 3832 <td valign="top">RESERVED</td> 3833 <td valign="top" align="center">rw</td> 3834 <td valign="top" align="center">0x0</td> 3835 <td valign="top">Reserved</td> 3836 </tr> 3837</table><a name="1.1.45"></a><br>1.1.45 : <b>Reg : PKA_PIPE_RDY</b> : 0x0000000B0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register indicates whether the PKA pipe is ready to receive a new OPCODE.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3838 <tr> 3839 <td colspan="32" align="center">PKA_PIPE_RDY</td> 3840 </tr> 3841 <tr></tr> 3842</table> 3843<table border="1" width="800"> 3844 <tr> 3845 <td width="40"><b>bits</b></td> 3846 <td width="100"><b>Field name</b></td> 3847 <td width="20"><b>permission</b></td> 3848 <td width="40"><b>default</b></td> 3849 <td width="600"><b>Description</b></td> 3850 </tr> 3851 <tr> 3852 <td valign="top" align="center"><a name="1.1.45.1"></a>0:0 3853 </td> 3854 <td valign="top">PKA_PIPE_RDY</td> 3855 <td valign="top" align="center">ro</td> 3856 <td valign="top" align="center">0x1</td> 3857 <td valign="top">Indication whether PKA pipe is ready for new OPCODE.</td> 3858 </tr> 3859 <tr> 3860 <td valign="top" align="center"><a name="1.1.45.2"></a>31:1 3861 </td> 3862 <td valign="top">RESERVED</td> 3863 <td valign="top" align="center">ro</td> 3864 <td valign="top" align="center">0x0</td> 3865 <td valign="top">Reserved</td> 3866 </tr> 3867</table><a name="1.1.46"></a><br>1.1.46 : <b>Reg : PKA_DONE</b> : 0x0000000B4<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register indicates whether PKA operation is completed.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3868 <tr> 3869 <td colspan="32" align="center">PKA_DONE</td> 3870 </tr> 3871 <tr></tr> 3872</table> 3873<table border="1" width="800"> 3874 <tr> 3875 <td width="40"><b>bits</b></td> 3876 <td width="100"><b>Field name</b></td> 3877 <td width="20"><b>permission</b></td> 3878 <td width="40"><b>default</b></td> 3879 <td width="600"><b>Description</b></td> 3880 </tr> 3881 <tr> 3882 <td valign="top" align="center"><a name="1.1.46.1"></a>0:0 3883 </td> 3884 <td valign="top">PKA_DONE</td> 3885 <td valign="top" align="center">ro</td> 3886 <td valign="top" align="center">0x1</td> 3887 <td valign="top">Indicates if PKA operation is completed, and pipe is empty.</td> 3888 </tr> 3889 <tr> 3890 <td valign="top" align="center"><a name="1.1.46.2"></a>31:1 3891 </td> 3892 <td valign="top">RESERVED</td> 3893 <td valign="top" align="center">ro</td> 3894 <td valign="top" align="center">0x0</td> 3895 <td valign="top">Reserved</td> 3896 </tr> 3897</table><a name="1.1.47"></a><br>1.1.47 : <b>Reg : PKA_MON_SELECT</b> : 0x0000000B8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines which PKA FSM monitor is being output.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3898 <tr> 3899 <td colspan="32" align="center">PKA_MON_SELECT</td> 3900 </tr> 3901 <tr></tr> 3902</table> 3903<table border="1" width="800"> 3904 <tr> 3905 <td width="40"><b>bits</b></td> 3906 <td width="100"><b>Field name</b></td> 3907 <td width="20"><b>permission</b></td> 3908 <td width="40"><b>default</b></td> 3909 <td width="600"><b>Description</b></td> 3910 </tr> 3911 <tr> 3912 <td valign="top" align="center"><a name="1.1.47.1"></a>3:0 3913 </td> 3914 <td valign="top">PKA_MON_SELECT</td> 3915 <td valign="top" align="center">rw</td> 3916 <td valign="top" align="center">0x0</td> 3917 <td valign="top">Defines which PKA FSM monitor is being output.</td> 3918 </tr> 3919 <tr> 3920 <td valign="top" align="center"><a name="1.1.47.2"></a>31:4 3921 </td> 3922 <td valign="top">RESERVED</td> 3923 <td valign="top" align="center">rw</td> 3924 <td valign="top" align="center">0x0</td> 3925 <td valign="top">Reserved</td> 3926 </tr> 3927</table><a name="1.1.48"></a><br>1.1.48 : <b>Reg : PKA_VERSION</b> : 0x0000000C4<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the pka version<br><table border="1" bgcolor="#EEEEEE" width="800"> 3928 <tr> 3929 <td colspan="32" align="center">PKA_VERSION</td> 3930 </tr> 3931 <tr></tr> 3932</table> 3933<table border="1" width="800"> 3934 <tr> 3935 <td width="40"><b>bits</b></td> 3936 <td width="100"><b>Field name</b></td> 3937 <td width="20"><b>permission</b></td> 3938 <td width="40"><b>default</b></td> 3939 <td width="600"><b>Description</b></td> 3940 </tr> 3941 <tr> 3942 <td valign="top" align="center"><a name="1.1.48.1"></a>31:0 3943 </td> 3944 <td valign="top">PKA_VERSION</td> 3945 <td valign="top" align="center">ro</td> 3946 <td valign="top" align="center">0x</td> 3947 <td valign="top">This is the PKA version</td> 3948 </tr> 3949</table><a name="1.1.49"></a><br>1.1.49 : <b>Reg : PKA_MON_READ</b> : 0x0000000D0<br><b>reg sep address</b> : <b> reg host address</b> : <br>The PKA monitor bus register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3950 <tr> 3951 <td colspan="32" align="center">PKA_MON_READ</td> 3952 </tr> 3953 <tr></tr> 3954</table> 3955<table border="1" width="800"> 3956 <tr> 3957 <td width="40"><b>bits</b></td> 3958 <td width="100"><b>Field name</b></td> 3959 <td width="20"><b>permission</b></td> 3960 <td width="40"><b>default</b></td> 3961 <td width="600"><b>Description</b></td> 3962 </tr> 3963 <tr> 3964 <td valign="top" align="center"><a name="1.1.49.1"></a>31:0 3965 </td> 3966 <td valign="top">PKA_MON_READ</td> 3967 <td valign="top" align="center">ro</td> 3968 <td valign="top" align="center">0x0</td> 3969 <td valign="top">This is the PKA monitor bus register output</td> 3970 </tr> 3971</table><a name="1.1.50"></a><br>1.1.50 : <b>Reg : PKA_SRAM_ADDR</b> : 0x0000000D4<br><b>reg sep address</b> : <b> reg host address</b> : <br>first address given to PKA SRAM for write transactions.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3972 <tr> 3973 <td colspan="32" align="center">PKA_SRAM_ADDR</td> 3974 </tr> 3975 <tr></tr> 3976</table> 3977<table border="1" width="800"> 3978 <tr> 3979 <td width="40"><b>bits</b></td> 3980 <td width="100"><b>Field name</b></td> 3981 <td width="20"><b>permission</b></td> 3982 <td width="40"><b>default</b></td> 3983 <td width="600"><b>Description</b></td> 3984 </tr> 3985 <tr> 3986 <td valign="top" align="center"><a name="1.1.50.1"></a>31:0 3987 </td> 3988 <td valign="top">PKA_SRAM_ADDR</td> 3989 <td valign="top" align="center">wo</td> 3990 <td valign="top" align="center">0x0</td> 3991 <td valign="top">PKA SRAM write starting address</td> 3992 </tr> 3993</table><a name="1.1.51"></a><br>1.1.51 : <b>Reg : PKA_SRAM_WDATA</b> : 0x0000000D8<br><b>reg sep address</b> : <b> reg host address</b> : <br>Write data to PKA SRAM.<br><table border="1" bgcolor="#EEEEEE" width="800"> 3994 <tr> 3995 <td colspan="32" align="center">PKA_SRAM_WDATA</td> 3996 </tr> 3997 <tr></tr> 3998</table> 3999<table border="1" width="800"> 4000 <tr> 4001 <td width="40"><b>bits</b></td> 4002 <td width="100"><b>Field name</b></td> 4003 <td width="20"><b>permission</b></td> 4004 <td width="40"><b>default</b></td> 4005 <td width="600"><b>Description</b></td> 4006 </tr> 4007 <tr> 4008 <td valign="top" align="center"><a name="1.1.51.1"></a>31:0 4009 </td> 4010 <td valign="top">PKA_SRAM_WDATA</td> 4011 <td valign="top" align="center">wo</td> 4012 <td valign="top" align="center">0x0</td> 4013 <td valign="top">32 bit write to PKA SRAM: triggers the SRAM write DMA address automatically incremented</td> 4014 </tr> 4015</table><a name="1.1.52"></a><br>1.1.52 : <b>Reg : PKA_SRAM_RDATA</b> : 0x0000000DC<br><b>reg sep address</b> : <b> reg host address</b> : <br>Read data from PKA SRAM.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4016 <tr> 4017 <td colspan="32" align="center">PKA_SRAM_RDATA</td> 4018 </tr> 4019 <tr></tr> 4020</table> 4021<table border="1" width="800"> 4022 <tr> 4023 <td width="40"><b>bits</b></td> 4024 <td width="100"><b>Field name</b></td> 4025 <td width="20"><b>permission</b></td> 4026 <td width="40"><b>default</b></td> 4027 <td width="600"><b>Description</b></td> 4028 </tr> 4029 <tr> 4030 <td valign="top" align="center"><a name="1.1.52.1"></a>31:0 4031 </td> 4032 <td valign="top">PKA_SRAM_RDATA</td> 4033 <td valign="top" align="center">r/wc</td> 4034 <td valign="top" align="center">0x0</td> 4035 <td valign="top">32 bit read from PKA SRAM: read - triggers the SRAM read DMA address automatically incremented</td> 4036 </tr> 4037</table><a name="1.1.53"></a><br>1.1.53 : <b>Reg : PKA_SRAM_WR_CLR</b> : 0x0000000E0<br><b>reg sep address</b> : <b> reg host address</b> : <br>Write buffer clean.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4038 <tr> 4039 <td colspan="32" align="center">PKA_SRAM_WR_CLR</td> 4040 </tr> 4041 <tr></tr> 4042</table> 4043<table border="1" width="800"> 4044 <tr> 4045 <td width="40"><b>bits</b></td> 4046 <td width="100"><b>Field name</b></td> 4047 <td width="20"><b>permission</b></td> 4048 <td width="40"><b>default</b></td> 4049 <td width="600"><b>Description</b></td> 4050 </tr> 4051 <tr> 4052 <td valign="top" align="center"><a name="1.1.53.1"></a>31:0 4053 </td> 4054 <td valign="top">PKA_SRAM_WR_CLR</td> 4055 <td valign="top" align="center">wo</td> 4056 <td valign="top" align="center">0x0</td> 4057 <td valign="top">Clear the write buffer.</td> 4058 </tr> 4059</table><a name="1.1.54"></a><br>1.1.54 : <b>Reg : PKA_SRAM_RADDR</b> : 0x0000000E4<br><b>reg sep address</b> : <b> reg host address</b> : <br>first address given to PKA SRAM for read transactions.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4060 <tr> 4061 <td colspan="32" align="center">PKA_SRAM_RADDR</td> 4062 </tr> 4063 <tr></tr> 4064</table> 4065<table border="1" width="800"> 4066 <tr> 4067 <td width="40"><b>bits</b></td> 4068 <td width="100"><b>Field name</b></td> 4069 <td width="20"><b>permission</b></td> 4070 <td width="40"><b>default</b></td> 4071 <td width="600"><b>Description</b></td> 4072 </tr> 4073 <tr> 4074 <td valign="top" align="center"><a name="1.1.54.1"></a>31:0 4075 </td> 4076 <td valign="top">PKA_SRAM_RADDR</td> 4077 <td valign="top" align="center">wo</td> 4078 <td valign="top" align="center">0x0</td> 4079 <td valign="top">PKA SRAM read starting address</td> 4080 </tr> 4081</table><a name="1.1.55"></a><br>1.1.55 : <b>Reg : PKA_WORD_ACCESS</b> : 0x0000000F0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the data written to PKA memory using the wop opcode.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4082 <tr> 4083 <td colspan="32" align="center">PKA_WORD_ACCESS</td> 4084 </tr> 4085 <tr></tr> 4086</table> 4087<table border="1" width="800"> 4088 <tr> 4089 <td width="40"><b>bits</b></td> 4090 <td width="100"><b>Field name</b></td> 4091 <td width="20"><b>permission</b></td> 4092 <td width="40"><b>default</b></td> 4093 <td width="600"><b>Description</b></td> 4094 </tr> 4095 <tr> 4096 <td valign="top" align="center"><a name="1.1.55.1"></a>31:0 4097 </td> 4098 <td valign="top">PKA_WORD_ACCESS</td> 4099 <td valign="top" align="center">wo</td> 4100 <td valign="top" align="center">0x0</td> 4101 <td valign="top">32 bit read/write data.</td> 4102 </tr> 4103</table><a name="1.1.56"></a><br>1.1.56 : <b>Reg : PKA_BUFF_ADDR</b> : 0x0000000F8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register maps the virtual buffer registers to a physical address in memory.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4104 <tr> 4105 <td colspan="32" align="center">PKA_BUFF_ADDR</td> 4106 </tr> 4107 <tr></tr> 4108</table> 4109<table border="1" width="800"> 4110 <tr> 4111 <td width="40"><b>bits</b></td> 4112 <td width="100"><b>Field name</b></td> 4113 <td width="20"><b>permission</b></td> 4114 <td width="40"><b>default</b></td> 4115 <td width="600"><b>Description</b></td> 4116 </tr> 4117 <tr> 4118 <td valign="top" align="center"><a name="1.1.56.1"></a>11:0 4119 </td> 4120 <td valign="top">PKA_BUF_ADDR</td> 4121 <td valign="top" align="center">wo</td> 4122 <td valign="top" align="center">0x0</td> 4123 <td valign="top">Contains the physical address in memory to map the buffer registers.</td> 4124 </tr> 4125 <tr> 4126 <td valign="top" align="center"><a name="1.1.56.2"></a>31:12 4127 </td> 4128 <td valign="top">RESEREVED1</td> 4129 <td valign="top" align="center">wo</td> 4130 <td valign="top" align="center">0x0</td> 4131 <td valign="top">Reserved</td> 4132 </tr> 4133</table><a href="#1.1">(top of block)</a><a name="1.2"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 4134 <td><b><font color="#000000">1.2 : Block: RNG</font></b></td> 4135 <td align="right"><font color="#000000">0x000000100</font></td> 4136</table><br><a name="1.2.1"></a><br>1.2.1 : <b>Reg : RNG_IMR</b> : 0x000000100<br><b>reg sep address</b> : <b> reg host address</b> : <br>Interrupt masking register.<br>Consists of {prng_imr trng_imr} bit[31-16] - PRNG_IMR bit[15-0] - TRNG_IMR <br>(Ws - PRNG bit exists only if PRNG_EXISTS flag)<br><table border="1" bgcolor="#EEEEEE" width="800"> 4137 <tr> 4138 <td colspan="32" align="center">RNG_IMR</td> 4139 </tr> 4140 <tr></tr> 4141</table> 4142<table border="1" width="800"> 4143 <tr> 4144 <td width="40"><b>bits</b></td> 4145 <td width="100"><b>Field name</b></td> 4146 <td width="20"><b>permission</b></td> 4147 <td width="40"><b>default</b></td> 4148 <td width="600"><b>Description</b></td> 4149 </tr> 4150 <tr> 4151 <td valign="top" align="center"><a name="1.2.1.1"></a>0:0 4152 </td> 4153 <td valign="top">EHR_VALID_INT_MASK</td> 4154 <td valign="top" align="center">rw</td> 4155 <td valign="top" align="center">0x1</td> 4156 <td valign="top">1'b1 - masks the EHR interrupt. No interrupt is generated. <br>See RNG_ISR for explanation on this interrupt. 4157 </td> 4158 </tr> 4159 <tr> 4160 <td valign="top" align="center"><a name="1.2.1.2"></a>1:1 4161 </td> 4162 <td valign="top">AUTOCORR_ERR_INT_MASK</td> 4163 <td valign="top" align="center">rw</td> 4164 <td valign="top" align="center">0x1</td> 4165 <td valign="top">1'b1 - masks the autocorrelation interrupt. No interrupt is generated. <br>See RNG_ISR for explanation on this interrupt. 4166 </td> 4167 </tr> 4168 <tr> 4169 <td valign="top" align="center"><a name="1.2.1.3"></a>2:2 4170 </td> 4171 <td valign="top">CRNGT_ERR_INT_MASK</td> 4172 <td valign="top" align="center">rw</td> 4173 <td valign="top" align="center">0x1</td> 4174 <td valign="top">1'b1 - masks the CRNGT error interrupt. No interrupt is generated. <br>See RNG_ISR for explanation on this interrupt. 4175 </td> 4176 </tr> 4177 <tr> 4178 <td valign="top" align="center"><a name="1.2.1.4"></a>3:3 4179 </td> 4180 <td valign="top">VN_ERR_INT_MASK</td> 4181 <td valign="top" align="center">rw</td> 4182 <td valign="top" align="center">0x1</td> 4183 <td valign="top">1'b1 - masks the Von-Neumann error interrupt. No interrupt is generated. <br>See RNG_ISR for explanation on this interrupt. 4184 </td> 4185 </tr> 4186 <tr> 4187 <td valign="top" align="center"><a name="1.2.1.5"></a>4:4 4188 </td> 4189 <td valign="top">WATCHDOG_INT_MASK</td> 4190 <td valign="top" align="center">rw</td> 4191 <td valign="top" align="center">0x1</td> 4192 <td valign="top">1'b1 - masks the watchdog interrupt. No interrupt is generated. <br>See RNG_ISR for explanation on this interrupt. 4193 </td> 4194 </tr> 4195 <tr> 4196 <td valign="top" align="center"><a name="1.2.1.6"></a>5:5 4197 </td> 4198 <td valign="top">RNG_DMA_DONE_INT</td> 4199 <td valign="top" align="center">rw</td> 4200 <td valign="top" align="center">0x1</td> 4201 <td valign="top">1'b1 - masks the RNG DMA completion interrupt. No interrupt is generated. <br>See RNG_ISR for explanation on this interrupt. 4202 </td> 4203 </tr> 4204 <tr> 4205 <td valign="top" align="center"><a name="1.2.1.7"></a>31:6 4206 </td> 4207 <td valign="top">RESERVED</td> 4208 <td valign="top" align="center">rw</td> 4209 <td valign="top" align="center">0x0</td> 4210 <td valign="top">Reserved</td> 4211 </tr> 4212</table><a name="1.2.2"></a><br>1.2.2 : <b>Reg : RNG_ISR</b> : 0x000000104<br><b>reg sep address</b> : <b> reg host address</b> : <br>Status register. <br>If corresponding RNG_IMR bit is unmasked, an interrupt is generated. <br>Consists of trng_isr and prng_isr bit[15-0] - TRNG bit[31-16] - PRNG<br><table border="1" bgcolor="#EEEEEE" width="800"> 4213 <tr> 4214 <td colspan="32" align="center">RNG_ISR</td> 4215 </tr> 4216 <tr></tr> 4217</table> 4218<table border="1" width="800"> 4219 <tr> 4220 <td width="40"><b>bits</b></td> 4221 <td width="100"><b>Field name</b></td> 4222 <td width="20"><b>permission</b></td> 4223 <td width="40"><b>default</b></td> 4224 <td width="600"><b>Description</b></td> 4225 </tr> 4226 <tr> 4227 <td valign="top" align="center"><a name="1.2.2.1"></a>0:0 4228 </td> 4229 <td valign="top">EHR_VALID</td> 4230 <td valign="top" align="center">ro</td> 4231 <td valign="top" align="center">0x0</td> 4232 <td valign="top">1'b1 indicates that 192 bits have been collected in the TRNG and are ready to be read.</td> 4233 </tr> 4234 <tr> 4235 <td valign="top" align="center"><a name="1.2.2.2"></a>1:1 4236 </td> 4237 <td valign="top">AUTOCORR_ERR</td> 4238 <td valign="top" align="center">ro</td> 4239 <td valign="top" align="center">0x0</td> 4240 <td valign="top">1'b1 indicates Autocorrelation test failed four times in a row. When it set ,TRNG ceases to function until next reset.</td> 4241 </tr> 4242 <tr> 4243 <td valign="top" align="center"><a name="1.2.2.3"></a>2:2 4244 </td> 4245 <td valign="top">CRNGT_ERR</td> 4246 <td valign="top" align="center">ro</td> 4247 <td valign="top" align="center">0x0</td> 4248 <td valign="top">1'b1 indicates CRNGT in the TRNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal.</td> 4249 </tr> 4250 <tr> 4251 <td valign="top" align="center"><a name="1.2.2.4"></a>3:3 4252 </td> 4253 <td valign="top">VN_ERR</td> 4254 <td valign="top" align="center">ro</td> 4255 <td valign="top" align="center">0x0</td> 4256 <td valign="top">1'b1 indicates Von Neumann error. Error in von Neumann occurs if 32 consecutive collected bits are identical, ZERO, or ONE.</td> 4257 </tr> 4258 <tr> 4259 <td valign="top" align="center"><a name="1.2.2.5"></a>4:4 4260 </td> 4261 <td valign="top">RESERVED0</td> 4262 <td valign="top" align="center">ro</td> 4263 <td valign="top" align="center">0x0</td> 4264 <td valign="top">Reserved</td> 4265 </tr> 4266 <tr> 4267 <td valign="top" align="center"><a name="1.2.2.6"></a>5:5 4268 </td> 4269 <td valign="top">RNG_DMA_DONE</td> 4270 <td valign="top" align="center">ro</td> 4271 <td valign="top" align="center">0x0</td> 4272 <td valign="top">1'b1 indicates RNG DMA to SRAM is completed.</td> 4273 </tr> 4274 <tr> 4275 <td valign="top" align="center"><a name="1.2.2.7"></a>15:6 4276 </td> 4277 <td valign="top">RESERVED1</td> 4278 <td valign="top" align="center">ro</td> 4279 <td valign="top" align="center">0x0</td> 4280 <td valign="top">Reserved</td> 4281 </tr> 4282 <tr> 4283 <td valign="top" align="center"><a name="1.2.2.8"></a>16:16 4284 </td> 4285 <td valign="top">RESEEDING_DONE</td> 4286 <td valign="top" align="center">ro</td> 4287 <td valign="top" align="center">0x0</td> 4288 <td valign="top">1'b1 indicates completion of reseeding algorithm with no errors.</td> 4289 </tr> 4290 <tr> 4291 <td valign="top" align="center"><a name="1.2.2.9"></a>17:17 4292 </td> 4293 <td valign="top">INSTANTIATION_DONE</td> 4294 <td valign="top" align="center">ro</td> 4295 <td valign="top" align="center">0x0</td> 4296 <td valign="top">1'b1 indicates completion of instantiation algorithm with no errors.</td> 4297 </tr> 4298 <tr> 4299 <td valign="top" align="center"><a name="1.2.2.10"></a>18:18 4300 </td> 4301 <td valign="top">FINAL_UPDATE_DONE</td> 4302 <td valign="top" align="center">ro</td> 4303 <td valign="top" align="center">0x0</td> 4304 <td valign="top">1'b1 indicates completion of final update algorithm.</td> 4305 </tr> 4306 <tr> 4307 <td valign="top" align="center"><a name="1.2.2.11"></a>19:19 4308 </td> 4309 <td valign="top">OUTPUT_READY</td> 4310 <td valign="top" align="center">ro</td> 4311 <td valign="top" align="center">0x0</td> 4312 <td valign="top">1'b1 indicates that the result of PRNG is valid and ready to be read. The result can be read from the RNG_READOUT register.</td> 4313 </tr> 4314 <tr> 4315 <td valign="top" align="center"><a name="1.2.2.12"></a>20:20 4316 </td> 4317 <td valign="top">RESEED_CNTR_FULL</td> 4318 <td valign="top" align="center">ro</td> 4319 <td valign="top" align="center">0x0</td> 4320 <td valign="top">1'b1 indicates that the reseed counter has reached 2^48, requiring to run the reseed algorithm before generating new random 4321 numbers. 4322 </td> 4323 </tr> 4324 <tr> 4325 <td valign="top" align="center"><a name="1.2.2.13"></a>21:21 4326 </td> 4327 <td valign="top">RESEED_CNTR_TOP_40</td> 4328 <td valign="top" align="center">ro</td> 4329 <td valign="top" align="center">0x0</td> 4330 <td valign="top">1'b1 indicates that the top 40 bits of the reseed counter are set (that is the reseed counter is larger than 2^48-2^8). This 4331 is a recommendation for running the reseed algorithm before the counter reaches its max value. 4332 </td> 4333 </tr> 4334 <tr> 4335 <td valign="top" align="center"><a name="1.2.2.14"></a>22:22 4336 </td> 4337 <td valign="top">PRNG_CRNGT_ERR</td> 4338 <td valign="top" align="center">ro</td> 4339 <td valign="top" align="center">0x0</td> 4340 <td valign="top">1'b1 indicates CRNGT in the PRNG test failed. Failure occurs when two consecutive results of AES are equal</td> 4341 </tr> 4342 <tr> 4343 <td valign="top" align="center"><a name="1.2.2.15"></a>23:23 4344 </td> 4345 <td valign="top">REQ_SIZE</td> 4346 <td valign="top" align="center">ro</td> 4347 <td valign="top" align="center">0x0</td> 4348 <td valign="top">1'b1 indicates that the request size counter (which represents how many generations of random bits in the PRNG have been produced) 4349 has reached 2^12, thus requiring a working state update before generating new random numbers. 4350 </td> 4351 </tr> 4352 <tr> 4353 <td valign="top" align="center"><a name="1.2.2.16"></a>24:24 4354 </td> 4355 <td valign="top">KAT_ERR</td> 4356 <td valign="top" align="center">ro</td> 4357 <td valign="top" align="center">0x0</td> 4358 <td valign="top">1'b1 indicates that one of the KAT (Known Answer Tests) tests has failed. When set, the entire engine ceases to function.</td> 4359 </tr> 4360 <tr> 4361 <td valign="top" align="center"><a name="1.2.2.17"></a>26:25 4362 </td> 4363 <td valign="top">WHICH_KAT_ERR</td> 4364 <td valign="top" align="center">ro</td> 4365 <td valign="top" align="center">0x0</td> 4366 <td valign="top">When the KAT_ERR bit is set, these bits represent which Known Answer Test had failed:<br>@2'b00 - first test of instantiation<br>@2'b01 - second test of instantiation<br>@2'b10 - first test of reseeding<br>@2'b11 - second test of reseeding 4367 </td> 4368 </tr> 4369 <tr> 4370 <td valign="top" align="center"><a name="1.2.2.18"></a>31:27 4371 </td> 4372 <td valign="top">RESERVED</td> 4373 <td valign="top" align="center">ro</td> 4374 <td valign="top" align="center">0x0</td> 4375 <td valign="top">Reserved</td> 4376 </tr> 4377</table><a name="1.2.3"></a><br>1.2.3 : <b>Reg : RNG_ICR</b> : 0x000000108<br><b>reg sep address</b> : <b> reg host address</b> : <br>Interrupt/status bit clear Register. Consists of trng_icr and prng_icr bit[15-0] - TRNG bit[31-16] - PRNG<br><table border="1" bgcolor="#EEEEEE" width="800"> 4378 <tr> 4379 <td colspan="32" align="center">RNG_ICR</td> 4380 </tr> 4381 <tr></tr> 4382</table> 4383<table border="1" width="800"> 4384 <tr> 4385 <td width="40"><b>bits</b></td> 4386 <td width="100"><b>Field name</b></td> 4387 <td width="20"><b>permission</b></td> 4388 <td width="40"><b>default</b></td> 4389 <td width="600"><b>Description</b></td> 4390 </tr> 4391 <tr> 4392 <td valign="top" align="center"><a name="1.2.3.1"></a>0:0 4393 </td> 4394 <td valign="top">EHR_VALID</td> 4395 <td valign="top" align="center">wo</td> 4396 <td valign="top" align="center">0x0</td> 4397 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4398 </tr> 4399 <tr> 4400 <td valign="top" align="center"><a name="1.2.3.2"></a>1:1 4401 </td> 4402 <td valign="top">AUTOCORR_ERR</td> 4403 <td valign="top" align="center">wo</td> 4404 <td valign="top" align="center">0x0</td> 4405 <td valign="top">Cannot be cleared by SW! Only RNG reset clears this bit.</td> 4406 </tr> 4407 <tr> 4408 <td valign="top" align="center"><a name="1.2.3.3"></a>2:2 4409 </td> 4410 <td valign="top">CRNGT_ERR</td> 4411 <td valign="top" align="center">wo</td> 4412 <td valign="top" align="center">0x0</td> 4413 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4414 </tr> 4415 <tr> 4416 <td valign="top" align="center"><a name="1.2.3.4"></a>3:3 4417 </td> 4418 <td valign="top">VN_ERR</td> 4419 <td valign="top" align="center">wo</td> 4420 <td valign="top" align="center">0x0</td> 4421 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4422 </tr> 4423 <tr> 4424 <td valign="top" align="center"><a name="1.2.3.5"></a>4:4 4425 </td> 4426 <td valign="top">RNG_WATCHDOG</td> 4427 <td valign="top" align="center">wo</td> 4428 <td valign="top" align="center">0x0</td> 4429 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4430 </tr> 4431 <tr> 4432 <td valign="top" align="center"><a name="1.2.3.6"></a>5:5 4433 </td> 4434 <td valign="top">RNG_DMA_DONE</td> 4435 <td valign="top" align="center">wo</td> 4436 <td valign="top" align="center">0x0</td> 4437 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4438 </tr> 4439 <tr> 4440 <td valign="top" align="center"><a name="1.2.3.7"></a>15:6 4441 </td> 4442 <td valign="top">RESERVED0</td> 4443 <td valign="top" align="center">wo</td> 4444 <td valign="top" align="center">0x0</td> 4445 <td valign="top">Reserved</td> 4446 </tr> 4447 <tr> 4448 <td valign="top" align="center"><a name="1.2.3.8"></a>16:16 4449 </td> 4450 <td valign="top">RESEEDING_DONE</td> 4451 <td valign="top" align="center">wo</td> 4452 <td valign="top" align="center">0x0</td> 4453 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4454 </tr> 4455 <tr> 4456 <td valign="top" align="center"><a name="1.2.3.9"></a>17:17 4457 </td> 4458 <td valign="top">INSTANTIATION_DONE</td> 4459 <td valign="top" align="center">wo</td> 4460 <td valign="top" align="center">0x0</td> 4461 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4462 </tr> 4463 <tr> 4464 <td valign="top" align="center"><a name="1.2.3.10"></a>18:18 4465 </td> 4466 <td valign="top">FINAL_UPDATE_DONE</td> 4467 <td valign="top" align="center">wo</td> 4468 <td valign="top" align="center">0x0</td> 4469 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4470 </tr> 4471 <tr> 4472 <td valign="top" align="center"><a name="1.2.3.11"></a>19:19 4473 </td> 4474 <td valign="top">OUTPUT_READY</td> 4475 <td valign="top" align="center">wo</td> 4476 <td valign="top" align="center">0x0</td> 4477 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4478 </tr> 4479 <tr> 4480 <td valign="top" align="center"><a name="1.2.3.12"></a>20:20 4481 </td> 4482 <td valign="top">RESEED_CNTR_FULL</td> 4483 <td valign="top" align="center">wo</td> 4484 <td valign="top" align="center">0x0</td> 4485 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4486 </tr> 4487 <tr> 4488 <td valign="top" align="center"><a name="1.2.3.13"></a>21:21 4489 </td> 4490 <td valign="top">RESEED_CNTR_TOP_40</td> 4491 <td valign="top" align="center">wo</td> 4492 <td valign="top" align="center">0x0</td> 4493 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4494 </tr> 4495 <tr> 4496 <td valign="top" align="center"><a name="1.2.3.14"></a>22:22 4497 </td> 4498 <td valign="top">PRNG_CRNGT_ERR</td> 4499 <td valign="top" align="center">wo</td> 4500 <td valign="top" align="center">0x0</td> 4501 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4502 </tr> 4503 <tr> 4504 <td valign="top" align="center"><a name="1.2.3.15"></a>23:23 4505 </td> 4506 <td valign="top">REQ_SIZE</td> 4507 <td valign="top" align="center">wo</td> 4508 <td valign="top" align="center">0x0</td> 4509 <td valign="top">Writing value 1'b1 - clears corresponding bit in RNG_ISR</td> 4510 </tr> 4511 <tr> 4512 <td valign="top" align="center"><a name="1.2.3.16"></a>24:24 4513 </td> 4514 <td valign="top">KAT_ERR</td> 4515 <td valign="top" align="center">wo</td> 4516 <td valign="top" align="center">0x0</td> 4517 <td valign="top">Cannot be cleared by SW! Only RNG reset clears this bit.</td> 4518 </tr> 4519 <tr> 4520 <td valign="top" align="center"><a name="1.2.3.17"></a>26:25 4521 </td> 4522 <td valign="top">WHICH_KAT_ERR</td> 4523 <td valign="top" align="center">wo</td> 4524 <td valign="top" align="center">0x0</td> 4525 <td valign="top">Cannot be cleared by SW! Only RNG reset clears this bit.</td> 4526 </tr> 4527 <tr> 4528 <td valign="top" align="center"><a name="1.2.3.18"></a>31:27 4529 </td> 4530 <td valign="top">RESERVED1</td> 4531 <td valign="top" align="center">wo</td> 4532 <td valign="top" align="center">0x0</td> 4533 <td valign="top">Reserved</td> 4534 </tr> 4535</table><a name="1.2.4"></a><br>1.2.4 : <b>Reg : TRNG_CONFIG</b> : 0x00000010C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register handles TRNG configuration<br><table border="1" bgcolor="#EEEEEE" width="800"> 4536 <tr> 4537 <td colspan="32" align="center">TRNG_CONFIG</td> 4538 </tr> 4539 <tr></tr> 4540</table> 4541<table border="1" width="800"> 4542 <tr> 4543 <td width="40"><b>bits</b></td> 4544 <td width="100"><b>Field name</b></td> 4545 <td width="20"><b>permission</b></td> 4546 <td width="40"><b>default</b></td> 4547 <td width="600"><b>Description</b></td> 4548 </tr> 4549 <tr> 4550 <td valign="top" align="center"><a name="1.2.4.1"></a>1:0 4551 </td> 4552 <td valign="top">RND_SRC_SEL</td> 4553 <td valign="top" align="center">rw</td> 4554 <td valign="top" align="center">0x0</td> 4555 <td valign="top">Defines the length of the oscillator ring (= the number of inverters) out of four possible selections.</td> 4556 </tr> 4557 <tr> 4558 <td valign="top" align="center"><a name="1.2.4.2"></a>2:2 4559 </td> 4560 <td valign="top">SOP_SEL</td> 4561 <td valign="top" align="center">rw</td> 4562 <td valign="top" align="center">0x0</td> 4563 <td valign="top">Secure Output Port selection:<br>@1'b1 - sop_data port reflects TRNG output (EHR_DATA). <br>@1'b0 - sop_data port reflects PRNG output (RNG_READOUT). <br>NOTE: Secure output is used for direct connection of the RNG block outputs to an engine input key. <br>If CryptoCell does not include a HW PRNG - this field should be set to 1. 4564 </td> 4565 </tr> 4566 <tr> 4567 <td valign="top" align="center"><a name="1.2.4.3"></a>31:3 4568 </td> 4569 <td valign="top">RESERVED</td> 4570 <td valign="top" align="center">rw</td> 4571 <td valign="top" align="center">0x0</td> 4572 <td valign="top">Reserved</td> 4573 </tr> 4574</table><a name="1.2.5"></a><br>1.2.5 : <b>Reg : TRNG_VALID</b> : 0x000000110<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register indicates that the TRNG data is valid.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4575 <tr> 4576 <td colspan="32" align="center">TRNG_VALID</td> 4577 </tr> 4578 <tr></tr> 4579</table> 4580<table border="1" width="800"> 4581 <tr> 4582 <td width="40"><b>bits</b></td> 4583 <td width="100"><b>Field name</b></td> 4584 <td width="20"><b>permission</b></td> 4585 <td width="40"><b>default</b></td> 4586 <td width="600"><b>Description</b></td> 4587 </tr> 4588 <tr> 4589 <td valign="top" align="center"><a name="1.2.5.1"></a>0:0 4590 </td> 4591 <td valign="top">EHR_VALID</td> 4592 <td valign="top" align="center">ro</td> 4593 <td valign="top" align="center">0x0</td> 4594 <td valign="top">1'b1 indicates that collection of bits in the TRNG is completed, and data can be read from the EHR_DATA register.</td> 4595 </tr> 4596 <tr> 4597 <td valign="top" align="center"><a name="1.2.5.2"></a>31:1 4598 </td> 4599 <td valign="top">RESERVED</td> 4600 <td valign="top" align="center">ro</td> 4601 <td valign="top" align="center">0x0</td> 4602 <td valign="top">Reserved</td> 4603 </tr> 4604</table><a name="1.2.6"></a><br>1.2.6 : <b>Reg : EHR_DATA_0</b> : 0x000000114<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register contains the data collected in the TRNG[31_0].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set).<br><table border="1" bgcolor="#EEEEEE" width="800"> 4605 <tr> 4606 <td colspan="32" align="center">EHR_DATA_0</td> 4607 </tr> 4608 <tr></tr> 4609</table> 4610<table border="1" width="800"> 4611 <tr> 4612 <td width="40"><b>bits</b></td> 4613 <td width="100"><b>Field name</b></td> 4614 <td width="20"><b>permission</b></td> 4615 <td width="40"><b>default</b></td> 4616 <td width="600"><b>Description</b></td> 4617 </tr> 4618 <tr> 4619 <td valign="top" align="center"><a name="1.2.6.1"></a>31:0 4620 </td> 4621 <td valign="top">EHR_DATA</td> 4622 <td valign="top" align="center">ro</td> 4623 <td valign="top" align="center">0x0</td> 4624 <td valign="top">Contains the data collected in the TRNG[31_0] .<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set). 4625 </td> 4626 </tr> 4627</table><a name="1.2.7"></a><br>1.2.7 : <b>Reg : EHR_DATA_1</b> : 0x000000118<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register contains the data collected in the TRNG[63_32].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set).<br><table border="1" bgcolor="#EEEEEE" width="800"> 4628 <tr> 4629 <td colspan="32" align="center">EHR_DATA_1</td> 4630 </tr> 4631 <tr></tr> 4632</table> 4633<table border="1" width="800"> 4634 <tr> 4635 <td width="40"><b>bits</b></td> 4636 <td width="100"><b>Field name</b></td> 4637 <td width="20"><b>permission</b></td> 4638 <td width="40"><b>default</b></td> 4639 <td width="600"><b>Description</b></td> 4640 </tr> 4641 <tr> 4642 <td valign="top" align="center"><a name="1.2.7.1"></a>31:0 4643 </td> 4644 <td valign="top">EHR_DATA</td> 4645 <td valign="top" align="center">ro</td> 4646 <td valign="top" align="center">0x0</td> 4647 <td valign="top">Contains the data collected in the TRNG[63_32].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set). 4648 </td> 4649 </tr> 4650</table><a name="1.2.8"></a><br>1.2.8 : <b>Reg : EHR_DATA_2</b> : 0x00000011C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register contains the data collected in the TRNG[95_64].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set).<br><table border="1" bgcolor="#EEEEEE" width="800"> 4651 <tr> 4652 <td colspan="32" align="center">EHR_DATA_2</td> 4653 </tr> 4654 <tr></tr> 4655</table> 4656<table border="1" width="800"> 4657 <tr> 4658 <td width="40"><b>bits</b></td> 4659 <td width="100"><b>Field name</b></td> 4660 <td width="20"><b>permission</b></td> 4661 <td width="40"><b>default</b></td> 4662 <td width="600"><b>Description</b></td> 4663 </tr> 4664 <tr> 4665 <td valign="top" align="center"><a name="1.2.8.1"></a>31:0 4666 </td> 4667 <td valign="top">EHR_DATA</td> 4668 <td valign="top" align="center">ro</td> 4669 <td valign="top" align="center">0x0</td> 4670 <td valign="top">Contains the data collected in the TRNG[95_64].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set). 4671 </td> 4672 </tr> 4673</table><a name="1.2.9"></a><br>1.2.9 : <b>Reg : EHR_DATA_3</b> : 0x000000120<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register contains the data collected in the TRNG[127_96].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set).<br><table border="1" bgcolor="#EEEEEE" width="800"> 4674 <tr> 4675 <td colspan="32" align="center">EHR_DATA_3</td> 4676 </tr> 4677 <tr></tr> 4678</table> 4679<table border="1" width="800"> 4680 <tr> 4681 <td width="40"><b>bits</b></td> 4682 <td width="100"><b>Field name</b></td> 4683 <td width="20"><b>permission</b></td> 4684 <td width="40"><b>default</b></td> 4685 <td width="600"><b>Description</b></td> 4686 </tr> 4687 <tr> 4688 <td valign="top" align="center"><a name="1.2.9.1"></a>31:0 4689 </td> 4690 <td valign="top">EHR_DATA</td> 4691 <td valign="top" align="center">ro</td> 4692 <td valign="top" align="center">0x0</td> 4693 <td valign="top">Contains the data collected in the TRNG[127_96].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set). 4694 </td> 4695 </tr> 4696</table><a name="1.2.10"></a><br>1.2.10 : <b>Reg : EHR_DATA_4</b> : 0x000000124<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register contains the data collected in the TRNG[159_128].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set).<br><table border="1" bgcolor="#EEEEEE" width="800"> 4697 <tr> 4698 <td colspan="32" align="center">EHR_DATA_4</td> 4699 </tr> 4700 <tr></tr> 4701</table> 4702<table border="1" width="800"> 4703 <tr> 4704 <td width="40"><b>bits</b></td> 4705 <td width="100"><b>Field name</b></td> 4706 <td width="20"><b>permission</b></td> 4707 <td width="40"><b>default</b></td> 4708 <td width="600"><b>Description</b></td> 4709 </tr> 4710 <tr> 4711 <td valign="top" align="center"><a name="1.2.10.1"></a>31:0 4712 </td> 4713 <td valign="top">EHR_DATA</td> 4714 <td valign="top" align="center">ro</td> 4715 <td valign="top" align="center">0x0</td> 4716 <td valign="top">Contains the data collected in the TRNG[159_128].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set). 4717 </td> 4718 </tr> 4719</table><a name="1.2.11"></a><br>1.2.11 : <b>Reg : EHR_DATA_5</b> : 0x000000128<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register contains the data collected in the TRNG[191_160].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set).<br><table border="1" bgcolor="#EEEEEE" width="800"> 4720 <tr> 4721 <td colspan="32" align="center">EHR_DATA_5</td> 4722 </tr> 4723 <tr></tr> 4724</table> 4725<table border="1" width="800"> 4726 <tr> 4727 <td width="40"><b>bits</b></td> 4728 <td width="100"><b>Field name</b></td> 4729 <td width="20"><b>permission</b></td> 4730 <td width="40"><b>default</b></td> 4731 <td width="600"><b>Description</b></td> 4732 </tr> 4733 <tr> 4734 <td valign="top" align="center"><a name="1.2.11.1"></a>31:0 4735 </td> 4736 <td valign="top">EHR_DATA</td> 4737 <td valign="top" align="center">ro</td> 4738 <td valign="top" align="center">0x0</td> 4739 <td valign="top">Contains the data collected in the TRNG[191_160].<br>NOTE: can only be set while in debug mode (rng_debug_enable input is set). 4740 </td> 4741 </tr> 4742</table><a name="1.2.12"></a><br>1.2.12 : <b>Reg : RND_SOURCE_ENABLE</b> : 0x00000012C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the enable signal for the random source.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4743 <tr> 4744 <td colspan="32" align="center">RND_SOURCE_ENABLE</td> 4745 </tr> 4746 <tr></tr> 4747</table> 4748<table border="1" width="800"> 4749 <tr> 4750 <td width="40"><b>bits</b></td> 4751 <td width="100"><b>Field name</b></td> 4752 <td width="20"><b>permission</b></td> 4753 <td width="40"><b>default</b></td> 4754 <td width="600"><b>Description</b></td> 4755 </tr> 4756 <tr> 4757 <td valign="top" align="center"><a name="1.2.12.1"></a>0:0 4758 </td> 4759 <td valign="top">RND_SRC_EN</td> 4760 <td valign="top" align="center">rw</td> 4761 <td valign="top" align="center">0x0</td> 4762 <td valign="top">Enable signal for the random source.</td> 4763 </tr> 4764 <tr> 4765 <td valign="top" align="center"><a name="1.2.12.2"></a>31:1 4766 </td> 4767 <td valign="top">RESERVED</td> 4768 <td valign="top" align="center">rw</td> 4769 <td valign="top" align="center">0x0</td> 4770 <td valign="top">Reserved</td> 4771 </tr> 4772</table><a name="1.2.13"></a><br>1.2.13 : <b>Reg : SAMPLE_CNT1</b> : 0x000000130<br><b>reg sep address</b> : <b> reg host address</b> : <br>Counts clocks between sampling of random bit.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4773 <tr> 4774 <td colspan="32" align="center">SAMPLE_CNT1</td> 4775 </tr> 4776 <tr></tr> 4777</table> 4778<table border="1" width="800"> 4779 <tr> 4780 <td width="40"><b>bits</b></td> 4781 <td width="100"><b>Field name</b></td> 4782 <td width="20"><b>permission</b></td> 4783 <td width="40"><b>default</b></td> 4784 <td width="600"><b>Description</b></td> 4785 </tr> 4786 <tr> 4787 <td valign="top" align="center"><a name="1.2.13.1"></a>31:0 4788 </td> 4789 <td valign="top">SAMPLE_CNTR1</td> 4790 <td valign="top" align="center">rw</td> 4791 <td valign="top" align="center">0x</td> 4792 <td valign="top">Sets the number of rng_clk cycles between two consecutive ring oscillator samples.<br>NOTE: If the Von-Neumann is bypassed, the minimum value for sample counter must not be less than decimal seventeen. 4793 </td> 4794 </tr> 4795</table><a name="1.2.14"></a><br>1.2.14 : <b>Reg : AUTOCORR_STATISTIC</b> : 0x000000134<br><b>reg sep address</b> : <b> reg host address</b> : <br>Statistics about autocorrelation test activations.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4796 <tr> 4797 <td colspan="32" align="center">AUTOCORR_STATISTIC</td> 4798 </tr> 4799 <tr></tr> 4800</table> 4801<table border="1" width="800"> 4802 <tr> 4803 <td width="40"><b>bits</b></td> 4804 <td width="100"><b>Field name</b></td> 4805 <td width="20"><b>permission</b></td> 4806 <td width="40"><b>default</b></td> 4807 <td width="600"><b>Description</b></td> 4808 </tr> 4809 <tr> 4810 <td valign="top" align="center"><a name="1.2.14.1"></a>13:0 4811 </td> 4812 <td valign="top">AUTOCORR_TRYS</td> 4813 <td valign="top" align="center">r/wc</td> 4814 <td valign="top" align="center">0x0</td> 4815 <td valign="top">Count each time an autocorrelation test starts. Any write to the register resets the counter. Stops collecting statistics 4816 if one of the counters has reached the limit. 4817 </td> 4818 </tr> 4819 <tr> 4820 <td valign="top" align="center"><a name="1.2.14.2"></a>21:14 4821 </td> 4822 <td valign="top">AUTOCORR_FAILS</td> 4823 <td valign="top" align="center">r/wc</td> 4824 <td valign="top" align="center">0x0</td> 4825 <td valign="top">Count each time an autocorrelation test fails. Any write to the register resets the counter. Stops collecting statistics if 4826 one of the counters has reached the limit. 4827 </td> 4828 </tr> 4829 <tr> 4830 <td valign="top" align="center"><a name="1.2.14.3"></a>31:22 4831 </td> 4832 <td valign="top">RESERVED</td> 4833 <td valign="top" align="center">r/wc</td> 4834 <td valign="top" align="center">0x0</td> 4835 <td valign="top">Reserved</td> 4836 </tr> 4837</table><a name="1.2.15"></a><br>1.2.15 : <b>Reg : TRNG_DEBUG_CONTROL</b> : 0x000000138<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is used to debug the TRNG<br><table border="1" bgcolor="#EEEEEE" width="800"> 4838 <tr> 4839 <td colspan="32" align="center">TRNG_DEBUG_CONTROL</td> 4840 </tr> 4841 <tr></tr> 4842</table> 4843<table border="1" width="800"> 4844 <tr> 4845 <td width="40"><b>bits</b></td> 4846 <td width="100"><b>Field name</b></td> 4847 <td width="20"><b>permission</b></td> 4848 <td width="40"><b>default</b></td> 4849 <td width="600"><b>Description</b></td> 4850 </tr> 4851 <tr> 4852 <td valign="top" align="center"><a name="1.2.15.1"></a>0:0 4853 </td> 4854 <td valign="top">RESERVED0</td> 4855 <td valign="top" align="center">rw</td> 4856 <td valign="top" align="center">0x0</td> 4857 <td valign="top">Reserved</td> 4858 </tr> 4859 <tr> 4860 <td valign="top" align="center"><a name="1.2.15.2"></a>1:1 4861 </td> 4862 <td valign="top">VNC_BYPASS</td> 4863 <td valign="top" align="center">rw</td> 4864 <td valign="top" align="center">0x0</td> 4865 <td valign="top">When this bit is set, the Von-Neumann balancer is bypassed (including the 32 consecutive bits test).<br>NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, this bit can be set while not in debug 4866 mode. 4867 </td> 4868 </tr> 4869 <tr> 4870 <td valign="top" align="center"><a name="1.2.15.3"></a>2:2 4871 </td> 4872 <td valign="top">TRNG_CRNGT_BYPASS</td> 4873 <td valign="top" align="center">rw</td> 4874 <td valign="top" align="center">0x0</td> 4875 <td valign="top">When this bit is set, the CRNGT test in the TRNG is bypassed. <br>NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, this bit can be set while not in debug 4876 mode. 4877 </td> 4878 </tr> 4879 <tr> 4880 <td valign="top" align="center"><a name="1.2.15.4"></a>3:3 4881 </td> 4882 <td valign="top">AUTO_CORRELATE_BYPASS</td> 4883 <td valign="top" align="center">rw</td> 4884 <td valign="top" align="center">0x0</td> 4885 <td valign="top">When this bit is set, the autocorrelation test in the TRNG module is bypassed.<br>NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, this bit can be set while not in debug 4886 mode. 4887 </td> 4888 </tr> 4889 <tr> 4890 <td valign="top" align="center"><a name="1.2.15.5"></a>31:4 4891 </td> 4892 <td valign="top">RESERVED1</td> 4893 <td valign="top" align="center">rw</td> 4894 <td valign="top" align="center">0x0</td> 4895 <td valign="top">Reserved</td> 4896 </tr> 4897</table><a name="1.2.16"></a><br>1.2.16 : <b>Reg : RNG_SW_RESET</b> : 0x000000140<br><b>reg sep address</b> : <b> reg host address</b> : <br>Generate SW reset solely to RNG block.<br><table border="1" bgcolor="#EEEEEE" width="800"> 4898 <tr> 4899 <td colspan="32" align="center">RNG_SW_RESET</td> 4900 </tr> 4901 <tr></tr> 4902</table> 4903<table border="1" width="800"> 4904 <tr> 4905 <td width="40"><b>bits</b></td> 4906 <td width="100"><b>Field name</b></td> 4907 <td width="20"><b>permission</b></td> 4908 <td width="40"><b>default</b></td> 4909 <td width="600"><b>Description</b></td> 4910 </tr> 4911 <tr> 4912 <td valign="top" align="center"><a name="1.2.16.1"></a>0:0 4913 </td> 4914 <td valign="top">RNG_SW_RESET</td> 4915 <td valign="top" align="center">r/wc</td> 4916 <td valign="top" align="center">0x0</td> 4917 <td valign="top">Any value written (1'b0 or 1'b1) causes a reset cycle to the TRNG block. <br>The reset mechanism takes about four RNG clock cycles until the reset line is de-asserted. 4918 </td> 4919 </tr> 4920 <tr> 4921 <td valign="top" align="center"><a name="1.2.16.2"></a>31:1 4922 </td> 4923 <td valign="top">RESERVED</td> 4924 <td valign="top" align="center">r/wc</td> 4925 <td valign="top" align="center">0x0</td> 4926 <td valign="top">Reserved</td> 4927 </tr> 4928</table><a name="1.2.17"></a><br>1.2.17 : <b>Reg : RNG_DEBUG_EN_INPUT</b> : 0x0000001B4<br><b>reg sep address</b> : <b> reg host address</b> : <br>Defines the RNG in debug mode<br><table border="1" bgcolor="#EEEEEE" width="800"> 4929 <tr> 4930 <td colspan="32" align="center">RNG_DEBUG_EN_INPUT</td> 4931 </tr> 4932 <tr></tr> 4933</table> 4934<table border="1" width="800"> 4935 <tr> 4936 <td width="40"><b>bits</b></td> 4937 <td width="100"><b>Field name</b></td> 4938 <td width="20"><b>permission</b></td> 4939 <td width="40"><b>default</b></td> 4940 <td width="600"><b>Description</b></td> 4941 </tr> 4942 <tr> 4943 <td valign="top" align="center"><a name="1.2.17.1"></a>0:0 4944 </td> 4945 <td valign="top">RNG_DEBUG_EN</td> 4946 <td valign="top" align="center">ro</td> 4947 <td valign="top" align="center">0x0</td> 4948 <td valign="top">Reflects the rng_debug_enable input port</td> 4949 </tr> 4950 <tr> 4951 <td valign="top" align="center"><a name="1.2.17.2"></a>31:1 4952 </td> 4953 <td valign="top">RESERVED</td> 4954 <td valign="top" align="center">ro</td> 4955 <td valign="top" align="center">0x0</td> 4956 <td valign="top">Reserved</td> 4957 </tr> 4958</table><a name="1.2.18"></a><br>1.2.18 : <b>Reg : RNG_BUSY</b> : 0x0000001B8<br><b>reg sep address</b> : <b> reg host address</b> : <br>RNG busy indication<br><table border="1" bgcolor="#EEEEEE" width="800"> 4959 <tr> 4960 <td colspan="32" align="center">RNG_BUSY</td> 4961 </tr> 4962 <tr></tr> 4963</table> 4964<table border="1" width="800"> 4965 <tr> 4966 <td width="40"><b>bits</b></td> 4967 <td width="100"><b>Field name</b></td> 4968 <td width="20"><b>permission</b></td> 4969 <td width="40"><b>default</b></td> 4970 <td width="600"><b>Description</b></td> 4971 </tr> 4972 <tr> 4973 <td valign="top" align="center"><a name="1.2.18.1"></a>0:0 4974 </td> 4975 <td valign="top">RNG_BUSY</td> 4976 <td valign="top" align="center">ro</td> 4977 <td valign="top" align="center">0x0</td> 4978 <td valign="top">Reflects rng_busy output port which Consists of trng_busy and prng_busy.</td> 4979 </tr> 4980 <tr> 4981 <td valign="top" align="center"><a name="1.2.18.2"></a>1:1 4982 </td> 4983 <td valign="top">TRNG_BUSY</td> 4984 <td valign="top" align="center">ro</td> 4985 <td valign="top" align="center">0x0</td> 4986 <td valign="top">Reflects trng_busy.</td> 4987 </tr> 4988 <tr> 4989 <td valign="top" align="center"><a name="1.2.18.3"></a>2:2 4990 </td> 4991 <td valign="top">PRNG_BUSY</td> 4992 <td valign="top" align="center">ro</td> 4993 <td valign="top" align="center">0x0</td> 4994 <td valign="top">Reflects prng_busy.</td> 4995 </tr> 4996 <tr> 4997 <td valign="top" align="center"><a name="1.2.18.4"></a>31:3 4998 </td> 4999 <td valign="top">RESERVED</td> 5000 <td valign="top" align="center">ro</td> 5001 <td valign="top" align="center">0x0</td> 5002 <td valign="top">Reserved</td> 5003 </tr> 5004</table><a name="1.2.19"></a><br>1.2.19 : <b>Reg : RST_BITS_COUNTER</b> : 0x0000001BC<br><b>reg sep address</b> : <b> reg host address</b> : <br>Resets the counter of collected bits in the TRNG<br><table border="1" bgcolor="#EEEEEE" width="800"> 5005 <tr> 5006 <td colspan="32" align="center">RST_BITS_COUNTER</td> 5007 </tr> 5008 <tr></tr> 5009</table> 5010<table border="1" width="800"> 5011 <tr> 5012 <td width="40"><b>bits</b></td> 5013 <td width="100"><b>Field name</b></td> 5014 <td width="20"><b>permission</b></td> 5015 <td width="40"><b>default</b></td> 5016 <td width="600"><b>Description</b></td> 5017 </tr> 5018 <tr> 5019 <td valign="top" align="center"><a name="1.2.19.1"></a>0:0 5020 </td> 5021 <td valign="top">RST_BITS_COUNTER</td> 5022 <td valign="top" align="center">wo</td> 5023 <td valign="top" align="center">0x0</td> 5024 <td valign="top">Writing any value to this address resets the bits counter and trng valid registers.<br>RND_SORCE_ENABLE register must be unset in order for reset to take place. 5025 </td> 5026 </tr> 5027 <tr> 5028 <td valign="top" align="center"><a name="1.2.19.2"></a>31:1 5029 </td> 5030 <td valign="top">RESERVED</td> 5031 <td valign="top" align="center">wo</td> 5032 <td valign="top" align="center">0x0</td> 5033 <td valign="top">Reserved</td> 5034 </tr> 5035</table><a name="1.2.20"></a><br>1.2.20 : <b>Reg : RNG_VERSION</b> : 0x0000001C0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the RNG version<br><table border="1" bgcolor="#EEEEEE" width="800"> 5036 <tr> 5037 <td colspan="32" align="center">RNG_VERSION</td> 5038 </tr> 5039 <tr></tr> 5040</table> 5041<table border="1" width="800"> 5042 <tr> 5043 <td width="40"><b>bits</b></td> 5044 <td width="100"><b>Field name</b></td> 5045 <td width="20"><b>permission</b></td> 5046 <td width="40"><b>default</b></td> 5047 <td width="600"><b>Description</b></td> 5048 </tr> 5049 <tr> 5050 <td valign="top" align="center"><a name="1.2.20.1"></a>0:0 5051 </td> 5052 <td valign="top">EHR_WIDTH_192</td> 5053 <td valign="top" align="center">ro</td> 5054 <td valign="top" align="center">0x1</td> 5055 <td valign="top">@1'b0 - 128 bit EHR<br>@1'b1 - 192 bit EHR 5056 </td> 5057 </tr> 5058 <tr> 5059 <td valign="top" align="center"><a name="1.2.20.2"></a>1:1 5060 </td> 5061 <td valign="top">CRNGT_EXISTS</td> 5062 <td valign="top" align="center">ro</td> 5063 <td valign="top" align="center">0x1</td> 5064 <td valign="top">@1'b0 - does not exist<br>@1'b1 - exists 5065 </td> 5066 </tr> 5067 <tr> 5068 <td valign="top" align="center"><a name="1.2.20.3"></a>2:2 5069 </td> 5070 <td valign="top">AUTOCORR_EXISTS</td> 5071 <td valign="top" align="center">ro</td> 5072 <td valign="top" align="center">0x1</td> 5073 <td valign="top">@1'b0 - does not exist<br>@1'b1 - exists 5074 </td> 5075 </tr> 5076 <tr> 5077 <td valign="top" align="center"><a name="1.2.20.4"></a>3:3 5078 </td> 5079 <td valign="top">TRNG_TESTS_BYPASS_EN</td> 5080 <td valign="top" align="center">ro</td> 5081 <td valign="top" align="center">0x1</td> 5082 <td valign="top">@1'b0 - trng tests bypass not enabled<br>@1'b1 - trng tests bypass enabled 5083 </td> 5084 </tr> 5085 <tr> 5086 <td valign="top" align="center"><a name="1.2.20.5"></a>4:4 5087 </td> 5088 <td valign="top">PRNG_EXISTS</td> 5089 <td valign="top" align="center">ro</td> 5090 <td valign="top" align="center">0x0</td> 5091 <td valign="top">@1'b0 - does not exist<br>@1'b1 - exists 5092 </td> 5093 </tr> 5094 <tr> 5095 <td valign="top" align="center"><a name="1.2.20.6"></a>5:5 5096 </td> 5097 <td valign="top">KAT_EXISTS</td> 5098 <td valign="top" align="center">ro</td> 5099 <td valign="top" align="center">0x0</td> 5100 <td valign="top">@1'b0 - does not exist<br>@1'b1 - exists 5101 </td> 5102 </tr> 5103 <tr> 5104 <td valign="top" align="center"><a name="1.2.20.7"></a>6:6 5105 </td> 5106 <td valign="top">RESEEDING_EXISTS</td> 5107 <td valign="top" align="center">ro</td> 5108 <td valign="top" align="center">0x0</td> 5109 <td valign="top">@1'b0 - does not exist<br>@1'b1 - exists 5110 </td> 5111 </tr> 5112 <tr> 5113 <td valign="top" align="center"><a name="1.2.20.8"></a>7:7 5114 </td> 5115 <td valign="top">RNG_USE_5_SBOXES</td> 5116 <td valign="top" align="center">ro</td> 5117 <td valign="top" align="center">0x0</td> 5118 <td valign="top">@1'b0 - 20 SBOX AES<br>@1'b1 - 5 SBOX AES 5119 </td> 5120 </tr> 5121 <tr> 5122 <td valign="top" align="center"><a name="1.2.20.9"></a>31:8 5123 </td> 5124 <td valign="top">RESERVED</td> 5125 <td valign="top" align="center">ro</td> 5126 <td valign="top" align="center">0x0</td> 5127 <td valign="top">Reserved</td> 5128 </tr> 5129</table><a name="1.2.21"></a><br>1.2.21 : <b>Reg : RNG_CLK_ENABLE</b> : 0x0000001C4<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this register enables/disables the RNG clock.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5130 <tr> 5131 <td colspan="32" align="center">RNG_CLK_ENABLE</td> 5132 </tr> 5133 <tr></tr> 5134</table> 5135<table border="1" width="800"> 5136 <tr> 5137 <td width="40"><b>bits</b></td> 5138 <td width="100"><b>Field name</b></td> 5139 <td width="20"><b>permission</b></td> 5140 <td width="40"><b>default</b></td> 5141 <td width="600"><b>Description</b></td> 5142 </tr> 5143 <tr> 5144 <td valign="top" align="center"><a name="1.2.21.1"></a>0:0 5145 </td> 5146 <td valign="top">EN</td> 5147 <td valign="top" align="center">wo</td> 5148 <td valign="top" align="center">0x0</td> 5149 <td valign="top">Writing value 1'b1 enables RNG clock.</td> 5150 </tr> 5151 <tr> 5152 <td valign="top" align="center"><a name="1.2.21.2"></a>31:1 5153 </td> 5154 <td valign="top">RESERVED</td> 5155 <td valign="top" align="center">wo</td> 5156 <td valign="top" align="center">0x0</td> 5157 <td valign="top">Reserved</td> 5158 </tr> 5159</table><a name="1.2.22"></a><br>1.2.22 : <b>Reg : RNG_DMA_ENABLE</b> : 0x0000001C8<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this register enables/disables the RNG DMA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5160 <tr> 5161 <td colspan="32" align="center">RNG_DMA_ENABLE</td> 5162 </tr> 5163 <tr></tr> 5164</table> 5165<table border="1" width="800"> 5166 <tr> 5167 <td width="40"><b>bits</b></td> 5168 <td width="100"><b>Field name</b></td> 5169 <td width="20"><b>permission</b></td> 5170 <td width="40"><b>default</b></td> 5171 <td width="600"><b>Description</b></td> 5172 </tr> 5173 <tr> 5174 <td valign="top" align="center"><a name="1.2.22.1"></a>0:0 5175 </td> 5176 <td valign="top">EN</td> 5177 <td valign="top" align="center">r/wc</td> 5178 <td valign="top" align="center">0x0</td> 5179 <td valign="top">Writing value 1'b1 enables RNG DMA to SRAM. The Value is cleared when DMA completes its operation.</td> 5180 </tr> 5181 <tr> 5182 <td valign="top" align="center"><a name="1.2.22.2"></a>31:1 5183 </td> 5184 <td valign="top">RESERVED</td> 5185 <td valign="top" align="center">r/wc</td> 5186 <td valign="top" align="center">0x0</td> 5187 <td valign="top">Reserved</td> 5188 </tr> 5189</table><a name="1.2.23"></a><br>1.2.23 : <b>Reg : RNG_DMA_SRC_MASK</b> : 0x0000001CC<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines which ring-oscillator length should be used when using the RNG DMA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5190 <tr> 5191 <td colspan="32" align="center">RNG_DMA_SRC_MASK</td> 5192 </tr> 5193 <tr></tr> 5194</table> 5195<table border="1" width="800"> 5196 <tr> 5197 <td width="40"><b>bits</b></td> 5198 <td width="100"><b>Field name</b></td> 5199 <td width="20"><b>permission</b></td> 5200 <td width="40"><b>default</b></td> 5201 <td width="600"><b>Description</b></td> 5202 </tr> 5203 <tr> 5204 <td valign="top" align="center"><a name="1.2.23.1"></a>0:0 5205 </td> 5206 <td valign="top">EN_SRC_SEL0</td> 5207 <td valign="top" align="center">rw</td> 5208 <td valign="top" align="center">0x0</td> 5209 <td valign="top">Writing value 1'b1 enables SRC_SEL 0.</td> 5210 </tr> 5211 <tr> 5212 <td valign="top" align="center"><a name="1.2.23.2"></a>1:1 5213 </td> 5214 <td valign="top">EN_SRC_SEL1</td> 5215 <td valign="top" align="center">rw</td> 5216 <td valign="top" align="center">0x0</td> 5217 <td valign="top">Writing value 1'b1 enables SRC_SEL 1.</td> 5218 </tr> 5219 <tr> 5220 <td valign="top" align="center"><a name="1.2.23.3"></a>2:2 5221 </td> 5222 <td valign="top">EN_SRC_SEL2</td> 5223 <td valign="top" align="center">rw</td> 5224 <td valign="top" align="center">0x0</td> 5225 <td valign="top">Writing value 1'b1 enables SRC_SEL 2.</td> 5226 </tr> 5227 <tr> 5228 <td valign="top" align="center"><a name="1.2.23.4"></a>3:3 5229 </td> 5230 <td valign="top">EN_SRC_SEL3</td> 5231 <td valign="top" align="center">rw</td> 5232 <td valign="top" align="center">0x0</td> 5233 <td valign="top">Writing value 1'b1 enables SRC_SEL 3.</td> 5234 </tr> 5235 <tr> 5236 <td valign="top" align="center"><a name="1.2.23.5"></a>31:4 5237 </td> 5238 <td valign="top">RESERVED</td> 5239 <td valign="top" align="center">rw</td> 5240 <td valign="top" align="center">0x0</td> 5241 <td valign="top">Reserved</td> 5242 </tr> 5243</table><a name="1.2.24"></a><br>1.2.24 : <b>Reg : RNG_DMA_SRAM_ADDR</b> : 0x0000001D0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines the start address of the DMA for the TRNG data.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5244 <tr> 5245 <td colspan="32" align="center">RNG_DMA_SRAM_ADDR</td> 5246 </tr> 5247 <tr></tr> 5248</table> 5249<table border="1" width="800"> 5250 <tr> 5251 <td width="40"><b>bits</b></td> 5252 <td width="100"><b>Field name</b></td> 5253 <td width="20"><b>permission</b></td> 5254 <td width="40"><b>default</b></td> 5255 <td width="600"><b>Description</b></td> 5256 </tr> 5257 <tr> 5258 <td valign="top" align="center"><a name="1.2.24.1"></a>10:0 5259 </td> 5260 <td valign="top">RNG_SRAM_DMA_ADDR</td> 5261 <td valign="top" align="center">rw</td> 5262 <td valign="top" align="center">0x0</td> 5263 <td valign="top">Defines the start address of the DMA for the TRNG data.</td> 5264 </tr> 5265 <tr> 5266 <td valign="top" align="center"><a name="1.2.24.2"></a>31:11 5267 </td> 5268 <td valign="top">RESERVED</td> 5269 <td valign="top" align="center">rw</td> 5270 <td valign="top" align="center">0x0</td> 5271 <td valign="top">Reserved</td> 5272 </tr> 5273</table><a name="1.2.25"></a><br>1.2.25 : <b>Reg : RNG_DMA_SAMPLES_NUM</b> : 0x0000001D4<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines the number of 192-bits samples that the DMA collects per RNG configuration.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5274 <tr> 5275 <td colspan="32" align="center">RNG_DMA_SAMPLES_NUM</td> 5276 </tr> 5277 <tr></tr> 5278</table> 5279<table border="1" width="800"> 5280 <tr> 5281 <td width="40"><b>bits</b></td> 5282 <td width="100"><b>Field name</b></td> 5283 <td width="20"><b>permission</b></td> 5284 <td width="40"><b>default</b></td> 5285 <td width="600"><b>Description</b></td> 5286 </tr> 5287 <tr> 5288 <td valign="top" align="center"><a name="1.2.25.1"></a>7:0 5289 </td> 5290 <td valign="top">RNG_SAMPLES_NUM</td> 5291 <td valign="top" align="center">rw</td> 5292 <td valign="top" align="center">0x0</td> 5293 <td valign="top">Defines the number of 192-bits samples that the DMA collects per RNG configuration.</td> 5294 </tr> 5295 <tr> 5296 <td valign="top" align="center"><a name="1.2.25.2"></a>31:8 5297 </td> 5298 <td valign="top">RESERVED</td> 5299 <td valign="top" align="center">rw</td> 5300 <td valign="top" align="center">0x0</td> 5301 <td valign="top">Reserved</td> 5302 </tr> 5303</table><a name="1.2.26"></a><br>1.2.26 : <b>Reg : RNG_WATCHDOG_VAL</b> : 0x0000001D8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines the maximum number of clock cycles per TRNG collection of 192 samples. If the number of cycles for a 5304collection exceeds this threshold, TRNG signals an interrupt.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5305 <tr> 5306 <td colspan="32" align="center">RNG_WATCHDOG_VAL</td> 5307 </tr> 5308 <tr></tr> 5309</table> 5310<table border="1" width="800"> 5311 <tr> 5312 <td width="40"><b>bits</b></td> 5313 <td width="100"><b>Field name</b></td> 5314 <td width="20"><b>permission</b></td> 5315 <td width="40"><b>default</b></td> 5316 <td width="600"><b>Description</b></td> 5317 </tr> 5318 <tr> 5319 <td valign="top" align="center"><a name="1.2.26.1"></a>31:0 5320 </td> 5321 <td valign="top">RNG_WATCHDOG_VAL</td> 5322 <td valign="top" align="center">rw</td> 5323 <td valign="top" align="center">0x0</td> 5324 <td valign="top">Defines the maximum number of clock cycles per TRNG collection of 192 samples. If the number of cycles for a collection exceeds 5325 this threshold, TRNG signals an interrupt. 5326 </td> 5327 </tr> 5328</table><a name="1.2.27"></a><br>1.2.27 : <b>Reg : RNG_DMA_STATUS</b> : 0x0000001DC<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the RNG DMA status.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5329 <tr> 5330 <td colspan="32" align="center">RNG_DMA_STATUS</td> 5331 </tr> 5332 <tr></tr> 5333</table> 5334<table border="1" width="800"> 5335 <tr> 5336 <td width="40"><b>bits</b></td> 5337 <td width="100"><b>Field name</b></td> 5338 <td width="20"><b>permission</b></td> 5339 <td width="40"><b>default</b></td> 5340 <td width="600"><b>Description</b></td> 5341 </tr> 5342 <tr> 5343 <td valign="top" align="center"><a name="1.2.27.1"></a>0:0 5344 </td> 5345 <td valign="top">RNG_DMA_BUSY</td> 5346 <td valign="top" align="center">ro</td> 5347 <td valign="top" align="center">0x0</td> 5348 <td valign="top">Indicates whether DMA is busy.</td> 5349 </tr> 5350 <tr> 5351 <td valign="top" align="center"><a name="1.2.27.2"></a>2:1 5352 </td> 5353 <td valign="top">DMA_SRC_SEL</td> 5354 <td valign="top" align="center">ro</td> 5355 <td valign="top" align="center">0x0</td> 5356 <td valign="top">The active ring oscillator length using by DMA</td> 5357 </tr> 5358 <tr> 5359 <td valign="top" align="center"><a name="1.2.27.3"></a>10:3 5360 </td> 5361 <td valign="top">NUM_OF_SAMPLES</td> 5362 <td valign="top" align="center">ro</td> 5363 <td valign="top" align="center">0x0</td> 5364 <td valign="top">Number of samples already collected in the current ring oscillator chain length.</td> 5365 </tr> 5366 <tr> 5367 <td valign="top" align="center"><a name="1.2.27.4"></a>31:11 5368 </td> 5369 <td valign="top">RESERVED</td> 5370 <td valign="top" align="center">ro</td> 5371 <td valign="top" align="center">0x0</td> 5372 <td valign="top">Reserved</td> 5373 </tr> 5374</table><a href="#1.2">(top of block)</a><a name="1.3"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 5375 <td><b><font color="#000000">1.3 : Block: CHACHA</font></b></td> 5376 <td align="right"><font color="#000000">0x000000380</font></td> 5377</table><br><a name="1.3.1"></a><br>1.3.1 : <b>Reg : CHACHA_CONTROL_REG</b> : 0x000000380<br><b>reg sep address</b> : <b> reg host address</b> : <br>CHACHA general configuration.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5378 <tr> 5379 <td colspan="32" align="center">CHACHA_CONTROL_REG</td> 5380 </tr> 5381 <tr></tr> 5382</table> 5383<table border="1" width="800"> 5384 <tr> 5385 <td width="40"><b>bits</b></td> 5386 <td width="100"><b>Field name</b></td> 5387 <td width="20"><b>permission</b></td> 5388 <td width="40"><b>default</b></td> 5389 <td width="600"><b>Description</b></td> 5390 </tr> 5391 <tr> 5392 <td valign="top" align="center"><a name="1.3.1.1"></a>0:0 5393 </td> 5394 <td valign="top">CHACHA_OR_SALSA</td> 5395 <td valign="top" align="center">r/wc</td> 5396 <td valign="top" align="center">0x0</td> 5397 <td valign="top">Core: <br>@1'b0 - ChaCha mode. <br>@1'b1 - Salsa mode. 5398 </td> 5399 </tr> 5400 <tr> 5401 <td valign="top" align="center"><a name="1.3.1.2"></a>1:1 5402 </td> 5403 <td valign="top">INIT_FROM_HOST</td> 5404 <td valign="top" align="center">r/wc</td> 5405 <td valign="top" align="center">0x0</td> 5406 <td valign="top">Start init for new Message:<br>@1'b0 - disable. <br>@1'b1 - enable. 5407 </td> 5408 </tr> 5409 <tr> 5410 <td valign="top" align="center"><a name="1.3.1.3"></a>2:2 5411 </td> 5412 <td valign="top">CALC_KEY_FOR_POLY1305</td> 5413 <td valign="top" align="center">r/wc</td> 5414 <td valign="top" align="center">0x0</td> 5415 <td valign="top">Only if ChaCha core:<br>@1'b0 - disable. <br>@1'b1 - enable. 5416 </td> 5417 </tr> 5418 <tr> 5419 <td valign="top" align="center"><a name="1.3.1.4"></a>3:3 5420 </td> 5421 <td valign="top">KEY_LEN</td> 5422 <td valign="top" align="center">r/wc</td> 5423 <td valign="top" align="center">0x0</td> 5424 <td valign="top">For All Core: <br>@1'b0 - 256 bit. <br>@1'b1 - 128 bit. 5425 </td> 5426 </tr> 5427 <tr> 5428 <td valign="top" align="center"><a name="1.3.1.5"></a>5:4 5429 </td> 5430 <td valign="top">NUM_OF_ROUNDS</td> 5431 <td valign="top" align="center">r/wc</td> 5432 <td valign="top" align="center">0x0</td> 5433 <td valign="top">The core of ChaCha is a hash function which based on rotation operations. The hash function consist in application of 20 rounds 5434 (default value). In additional, ChaCha have two variants (they work exactly as the original algorithm): ChaCha20/8 and ChaCha20/12 5435 (using 8 and 12 rounds). <br>Default value 00<br>@00 - 20 rounds <br>@01 - 12 rounds<br>@10 - 8 rounds <br>@11 - N/A 5436 </td> 5437 </tr> 5438 <tr> 5439 <td valign="top" align="center"><a name="1.3.1.6"></a>8:6 5440 </td> 5441 <td valign="top">RESERVED</td> 5442 <td valign="top" align="center">r/wc</td> 5443 <td valign="top" align="center">0x0</td> 5444 <td valign="top">Reserved</td> 5445 </tr> 5446 <tr> 5447 <td valign="top" align="center"><a name="1.3.1.7"></a>9:9 5448 </td> 5449 <td valign="top">RESET_BLOCK_CNT</td> 5450 <td valign="top" align="center">r/wc</td> 5451 <td valign="top" align="center">0x0</td> 5452 <td valign="top">For new message</td> 5453 </tr> 5454 <tr> 5455 <td valign="top" align="center"><a name="1.3.1.8"></a>10:10 5456 </td> 5457 <td valign="top">USE_IV_96BIT</td> 5458 <td valign="top" align="center">r/wc</td> 5459 <td valign="top" align="center">0x0</td> 5460 <td valign="top">If use 96bit IV</td> 5461 </tr> 5462 <tr> 5463 <td valign="top" align="center"><a name="1.3.1.9"></a>31:11 5464 </td> 5465 <td valign="top">RESERVED1</td> 5466 <td valign="top" align="center">r/wc</td> 5467 <td valign="top" align="center">0x0</td> 5468 <td valign="top">Reserved1</td> 5469 </tr> 5470</table><a name="1.3.2"></a><br>1.3.2 : <b>Reg : CHACHA_VERSION</b> : 0x000000384<br><b>reg sep address</b> : <b> reg host address</b> : <br>CHACHA Version<br><table border="1" bgcolor="#EEEEEE" width="800"> 5471 <tr> 5472 <td colspan="32" align="center">CHACHA_VERSION</td> 5473 </tr> 5474 <tr></tr> 5475</table> 5476<table border="1" width="800"> 5477 <tr> 5478 <td width="40"><b>bits</b></td> 5479 <td width="100"><b>Field name</b></td> 5480 <td width="20"><b>permission</b></td> 5481 <td width="40"><b>default</b></td> 5482 <td width="600"><b>Description</b></td> 5483 </tr> 5484 <tr> 5485 <td valign="top" align="center"><a name="1.3.2.1"></a>31:0 5486 </td> 5487 <td valign="top">CHACHA_VERSION</td> 5488 <td valign="top" align="center">ro</td> 5489 <td valign="top" align="center">0x1</td> 5490 <td valign="top"></td> 5491 </tr> 5492</table><a name="1.3.3"></a><br>1.3.3 : <b>Reg : CHACHA_KEY0</b> : 0x000000388<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 255:224 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5493 <tr> 5494 <td colspan="32" align="center">CHACHA_KEY0</td> 5495 </tr> 5496 <tr></tr> 5497</table> 5498<table border="1" width="800"> 5499 <tr> 5500 <td width="40"><b>bits</b></td> 5501 <td width="100"><b>Field name</b></td> 5502 <td width="20"><b>permission</b></td> 5503 <td width="40"><b>default</b></td> 5504 <td width="600"><b>Description</b></td> 5505 </tr> 5506 <tr> 5507 <td valign="top" align="center"><a name="1.3.3.1"></a>31:0 5508 </td> 5509 <td valign="top">CHACHA_KEY0</td> 5510 <td valign="top" align="center">wo</td> 5511 <td valign="top" align="center">0x0</td> 5512 <td valign="top">bits 255:224 of CHACHA Key</td> 5513 </tr> 5514</table><a name="1.3.4"></a><br>1.3.4 : <b>Reg : CHACHA_KEY1</b> : 0x00000038C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 223:192 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5515 <tr> 5516 <td colspan="32" align="center">CHACHA_KEY1</td> 5517 </tr> 5518 <tr></tr> 5519</table> 5520<table border="1" width="800"> 5521 <tr> 5522 <td width="40"><b>bits</b></td> 5523 <td width="100"><b>Field name</b></td> 5524 <td width="20"><b>permission</b></td> 5525 <td width="40"><b>default</b></td> 5526 <td width="600"><b>Description</b></td> 5527 </tr> 5528 <tr> 5529 <td valign="top" align="center"><a name="1.3.4.1"></a>31:0 5530 </td> 5531 <td valign="top">CHACHA_KEY1</td> 5532 <td valign="top" align="center">wo</td> 5533 <td valign="top" align="center">0x0</td> 5534 <td valign="top">bits 223:192 of CHACHA Key</td> 5535 </tr> 5536</table><a name="1.3.5"></a><br>1.3.5 : <b>Reg : CHACHA_KEY2</b> : 0x000000390<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits191:160 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5537 <tr> 5538 <td colspan="32" align="center">CHACHA_KEY2</td> 5539 </tr> 5540 <tr></tr> 5541</table> 5542<table border="1" width="800"> 5543 <tr> 5544 <td width="40"><b>bits</b></td> 5545 <td width="100"><b>Field name</b></td> 5546 <td width="20"><b>permission</b></td> 5547 <td width="40"><b>default</b></td> 5548 <td width="600"><b>Description</b></td> 5549 </tr> 5550 <tr> 5551 <td valign="top" align="center"><a name="1.3.5.1"></a>31:0 5552 </td> 5553 <td valign="top">CHACHA_KEY2</td> 5554 <td valign="top" align="center">wo</td> 5555 <td valign="top" align="center">0x0</td> 5556 <td valign="top">bits191:160 of CHACHA Key</td> 5557 </tr> 5558</table><a name="1.3.6"></a><br>1.3.6 : <b>Reg : CHACHA_KEY3</b> : 0x000000394<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits159:128 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5559 <tr> 5560 <td colspan="32" align="center">CHACHA_KEY3</td> 5561 </tr> 5562 <tr></tr> 5563</table> 5564<table border="1" width="800"> 5565 <tr> 5566 <td width="40"><b>bits</b></td> 5567 <td width="100"><b>Field name</b></td> 5568 <td width="20"><b>permission</b></td> 5569 <td width="40"><b>default</b></td> 5570 <td width="600"><b>Description</b></td> 5571 </tr> 5572 <tr> 5573 <td valign="top" align="center"><a name="1.3.6.1"></a>31:0 5574 </td> 5575 <td valign="top">CHACHA_KEY3</td> 5576 <td valign="top" align="center">wo</td> 5577 <td valign="top" align="center">0x0</td> 5578 <td valign="top">bits 159:128 of CHACHA Key</td> 5579 </tr> 5580</table><a name="1.3.7"></a><br>1.3.7 : <b>Reg : CHACHA_KEY4</b> : 0x000000398<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5581 <tr> 5582 <td colspan="32" align="center">CHACHA_KEY4</td> 5583 </tr> 5584 <tr></tr> 5585</table> 5586<table border="1" width="800"> 5587 <tr> 5588 <td width="40"><b>bits</b></td> 5589 <td width="100"><b>Field name</b></td> 5590 <td width="20"><b>permission</b></td> 5591 <td width="40"><b>default</b></td> 5592 <td width="600"><b>Description</b></td> 5593 </tr> 5594 <tr> 5595 <td valign="top" align="center"><a name="1.3.7.1"></a>31:0 5596 </td> 5597 <td valign="top">CHACHA_KEY4</td> 5598 <td valign="top" align="center">wo</td> 5599 <td valign="top" align="center">0x0</td> 5600 <td valign="top">bits 127:96 of CHACHA Key</td> 5601 </tr> 5602</table><a name="1.3.8"></a><br>1.3.8 : <b>Reg : CHACHA_KEY5</b> : 0x00000039C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5603 <tr> 5604 <td colspan="32" align="center">CHACHA_KEY5</td> 5605 </tr> 5606 <tr></tr> 5607</table> 5608<table border="1" width="800"> 5609 <tr> 5610 <td width="40"><b>bits</b></td> 5611 <td width="100"><b>Field name</b></td> 5612 <td width="20"><b>permission</b></td> 5613 <td width="40"><b>default</b></td> 5614 <td width="600"><b>Description</b></td> 5615 </tr> 5616 <tr> 5617 <td valign="top" align="center"><a name="1.3.8.1"></a>31:0 5618 </td> 5619 <td valign="top">CHACHA_KEY5</td> 5620 <td valign="top" align="center">wo</td> 5621 <td valign="top" align="center">0x0</td> 5622 <td valign="top">bits 95:64 of CHACHA Key</td> 5623 </tr> 5624</table><a name="1.3.9"></a><br>1.3.9 : <b>Reg : CHACHA_KEY6</b> : 0x0000003A0<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5625 <tr> 5626 <td colspan="32" align="center">CHACHA_KEY6</td> 5627 </tr> 5628 <tr></tr> 5629</table> 5630<table border="1" width="800"> 5631 <tr> 5632 <td width="40"><b>bits</b></td> 5633 <td width="100"><b>Field name</b></td> 5634 <td width="20"><b>permission</b></td> 5635 <td width="40"><b>default</b></td> 5636 <td width="600"><b>Description</b></td> 5637 </tr> 5638 <tr> 5639 <td valign="top" align="center"><a name="1.3.9.1"></a>31:0 5640 </td> 5641 <td valign="top">CHACHA_KEY6</td> 5642 <td valign="top" align="center">wo</td> 5643 <td valign="top" align="center">0x0</td> 5644 <td valign="top">bits 63:32 of CHACHA Key</td> 5645 </tr> 5646</table><a name="1.3.10"></a><br>1.3.10 : <b>Reg : CHACHA_KEY7</b> : 0x0000003A4<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of CHACHA Key<br><table border="1" bgcolor="#EEEEEE" width="800"> 5647 <tr> 5648 <td colspan="32" align="center">CHACHA_KEY7</td> 5649 </tr> 5650 <tr></tr> 5651</table> 5652<table border="1" width="800"> 5653 <tr> 5654 <td width="40"><b>bits</b></td> 5655 <td width="100"><b>Field name</b></td> 5656 <td width="20"><b>permission</b></td> 5657 <td width="40"><b>default</b></td> 5658 <td width="600"><b>Description</b></td> 5659 </tr> 5660 <tr> 5661 <td valign="top" align="center"><a name="1.3.10.1"></a>31:0 5662 </td> 5663 <td valign="top">CHACHA_KEY7</td> 5664 <td valign="top" align="center">wo</td> 5665 <td valign="top" align="center">0x0</td> 5666 <td valign="top">bits 31:0 of CHACHA Key</td> 5667 </tr> 5668</table><a name="1.3.11"></a><br>1.3.11 : <b>Reg : CHACHA_IV_0</b> : 0x0000003A8<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of CHACHA_IV0 register<br><table border="1" bgcolor="#EEEEEE" width="800"> 5669 <tr> 5670 <td colspan="32" align="center">CHACHA_IV_0</td> 5671 </tr> 5672 <tr></tr> 5673</table> 5674<table border="1" width="800"> 5675 <tr> 5676 <td width="40"><b>bits</b></td> 5677 <td width="100"><b>Field name</b></td> 5678 <td width="20"><b>permission</b></td> 5679 <td width="40"><b>default</b></td> 5680 <td width="600"><b>Description</b></td> 5681 </tr> 5682 <tr> 5683 <td valign="top" align="center"><a name="1.3.11.1"></a>31:0 5684 </td> 5685 <td valign="top">CHACHA_IV_0</td> 5686 <td valign="top" align="center">rw</td> 5687 <td valign="top" align="center">0x0</td> 5688 <td valign="top">bits 31:0 of CHACHA_IV0 register</td> 5689 </tr> 5690</table><a name="1.3.12"></a><br>1.3.12 : <b>Reg : CHACHA_IV_1</b> : 0x0000003AC<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of CHACHA_IV1 register<br><table border="1" bgcolor="#EEEEEE" width="800"> 5691 <tr> 5692 <td colspan="32" align="center">CHACHA_IV_1</td> 5693 </tr> 5694 <tr></tr> 5695</table> 5696<table border="1" width="800"> 5697 <tr> 5698 <td width="40"><b>bits</b></td> 5699 <td width="100"><b>Field name</b></td> 5700 <td width="20"><b>permission</b></td> 5701 <td width="40"><b>default</b></td> 5702 <td width="600"><b>Description</b></td> 5703 </tr> 5704 <tr> 5705 <td valign="top" align="center"><a name="1.3.12.1"></a>31:0 5706 </td> 5707 <td valign="top">CHACHA_IV_1</td> 5708 <td valign="top" align="center">rw</td> 5709 <td valign="top" align="center">0x0</td> 5710 <td valign="top">bits 31:0 of CHACHA_IV1 register</td> 5711 </tr> 5712</table><a name="1.3.13"></a><br>1.3.13 : <b>Reg : CHACHA_BUSY</b> : 0x0000003B0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is set when the CHACHA/SALSA core is active<br><table border="1" bgcolor="#EEEEEE" width="800"> 5713 <tr> 5714 <td colspan="32" align="center">CHACHA_BUSY</td> 5715 </tr> 5716 <tr></tr> 5717</table> 5718<table border="1" width="800"> 5719 <tr> 5720 <td width="40"><b>bits</b></td> 5721 <td width="100"><b>Field name</b></td> 5722 <td width="20"><b>permission</b></td> 5723 <td width="40"><b>default</b></td> 5724 <td width="600"><b>Description</b></td> 5725 </tr> 5726 <tr> 5727 <td valign="top" align="center"><a name="1.3.13.1"></a>0:0 5728 </td> 5729 <td valign="top">CHACHA_BUSY</td> 5730 <td valign="top" align="center">ro</td> 5731 <td valign="top" align="center">0x0</td> 5732 <td valign="top">CHACHA_BUSY Register. this register is set when the CHACHA/SALSA core is active</td> 5733 </tr> 5734 <tr> 5735 <td valign="top" align="center"><a name="1.3.13.2"></a>31:1 5736 </td> 5737 <td valign="top">RESERVED</td> 5738 <td valign="top" align="center">ro</td> 5739 <td valign="top" align="center">0x0</td> 5740 <td valign="top">Reserved</td> 5741 </tr> 5742</table><a name="1.3.14"></a><br>1.3.14 : <b>Reg : CHACHA_HW_FLAGS</b> : 0x0000003B4<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the pre-synthesis HW flag configuration of the CHACHA/SALSA engine<br><table border="1" bgcolor="#EEEEEE" width="800"> 5743 <tr> 5744 <td colspan="32" align="center">CHACHA_HW_FLAGS</td> 5745 </tr> 5746 <tr></tr> 5747</table> 5748<table border="1" width="800"> 5749 <tr> 5750 <td width="40"><b>bits</b></td> 5751 <td width="100"><b>Field name</b></td> 5752 <td width="20"><b>permission</b></td> 5753 <td width="40"><b>default</b></td> 5754 <td width="600"><b>Description</b></td> 5755 </tr> 5756 <tr> 5757 <td valign="top" align="center"><a name="1.3.14.1"></a>0:0 5758 </td> 5759 <td valign="top">CHACHA_EXISTS</td> 5760 <td valign="top" align="center">ro</td> 5761 <td valign="top" align="center">0x1</td> 5762 <td valign="top">If this flag is set, the Salsa/ChaCha engine include ChaCha implementation:<br>@1'b0 - disable. <br>@1'b1 - enable. 5763 </td> 5764 </tr> 5765 <tr> 5766 <td valign="top" align="center"><a name="1.3.14.2"></a>1:1 5767 </td> 5768 <td valign="top">SALSA_EXISTS</td> 5769 <td valign="top" align="center">ro</td> 5770 <td valign="top" align="center">0x0</td> 5771 <td valign="top">If this flag is set, the Salsa/ChaCha engine include Salsa implementation:<br>@1'b0 - disable. <br>@1'b1 - enable. 5772 </td> 5773 </tr> 5774 <tr> 5775 <td valign="top" align="center"><a name="1.3.14.3"></a>2:2 5776 </td> 5777 <td valign="top">FAST_CHACHA</td> 5778 <td valign="top" align="center">ro</td> 5779 <td valign="top" align="center">0x0</td> 5780 <td valign="top">If this flag is set, the next matrix calculated when the current one is written to data output path (same flag for Salsa core):<br>@1'b0 - disable. <br>@1'b1 - enable. 5781 </td> 5782 </tr> 5783 <tr> 5784 <td valign="top" align="center"><a name="1.3.14.4"></a>31:3 5785 </td> 5786 <td valign="top">RESERVED</td> 5787 <td valign="top" align="center">ro</td> 5788 <td valign="top" align="center">0x0</td> 5789 <td valign="top">Reserved</td> 5790 </tr> 5791</table><a name="1.3.15"></a><br>1.3.15 : <b>Reg : CHACHA_BLOCK_CNT_LSB</b> : 0x0000003B8<br><b>reg sep address</b> : <b> reg host address</b> : <br>The two first words (n) in the last row of the cipher matrix are the block counter. At the end of each block (512b), the block_cnt 5792for the next block is written by HW to the block_cnt_lsb and block_cnt_msb registers. Need reset block counter , if start 5793new message.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5794 <tr> 5795 <td colspan="32" align="center">CHACHA_BLOCK_CNT_LSB</td> 5796 </tr> 5797 <tr></tr> 5798</table> 5799<table border="1" width="800"> 5800 <tr> 5801 <td width="40"><b>bits</b></td> 5802 <td width="100"><b>Field name</b></td> 5803 <td width="20"><b>permission</b></td> 5804 <td width="40"><b>default</b></td> 5805 <td width="600"><b>Description</b></td> 5806 </tr> 5807 <tr> 5808 <td valign="top" align="center"><a name="1.3.15.1"></a>31:0 5809 </td> 5810 <td valign="top">CHACHA_BLOCK_CNT_LSB</td> 5811 <td valign="top" align="center">rw</td> 5812 <td valign="top" align="center">0x0</td> 5813 <td valign="top">bits 31:0 of CHACHA_BLOCK_CNT_LSB register. <br>This register holds the chacha block counter bits 31:0 5814 </td> 5815 </tr> 5816</table><a name="1.3.16"></a><br>1.3.16 : <b>Reg : CHACHA_BLOCK_CNT_MSB</b> : 0x0000003BC<br><b>reg sep address</b> : <b> reg host address</b> : <br>The two first words (n) in the last row of the cipher matrix are the block counter. At the end of each block (512b), the block_cnt 5817for the next block is written by HW to the block_cnt_lsb and block_cnt_msb registers. Need reset block counter , if start 5818new message.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5819 <tr> 5820 <td colspan="32" align="center">CHACHA_BLOCK_CNT_MSB</td> 5821 </tr> 5822 <tr></tr> 5823</table> 5824<table border="1" width="800"> 5825 <tr> 5826 <td width="40"><b>bits</b></td> 5827 <td width="100"><b>Field name</b></td> 5828 <td width="20"><b>permission</b></td> 5829 <td width="40"><b>default</b></td> 5830 <td width="600"><b>Description</b></td> 5831 </tr> 5832 <tr> 5833 <td valign="top" align="center"><a name="1.3.16.1"></a>31:0 5834 </td> 5835 <td valign="top">CHACHA_BLOCK_CNT_MSB</td> 5836 <td valign="top" align="center">rw</td> 5837 <td valign="top" align="center">0x0</td> 5838 <td valign="top">bits 31:0 of CHACHA_BLOCK_CNT_MSB register. <br>This register holds the chacha block counter bits 63:32 5839 </td> 5840 </tr> 5841</table><a name="1.3.17"></a><br>1.3.17 : <b>Reg : CHACHA_SW_RESET</b> : 0x0000003C0<br><b>reg sep address</b> : <b> reg host address</b> : <br>Resets CHACHA/SALSA engine.<br><table border="1" bgcolor="#EEEEEE" width="800"> 5842 <tr> 5843 <td colspan="32" align="center">CHACHA_SW_RESET</td> 5844 </tr> 5845 <tr></tr> 5846</table> 5847<table border="1" width="800"> 5848 <tr> 5849 <td width="40"><b>bits</b></td> 5850 <td width="100"><b>Field name</b></td> 5851 <td width="20"><b>permission</b></td> 5852 <td width="40"><b>default</b></td> 5853 <td width="600"><b>Description</b></td> 5854 </tr> 5855 <tr> 5856 <td valign="top" align="center"><a name="1.3.17.1"></a>0:0 5857 </td> 5858 <td valign="top">CHACH_SW_RESET</td> 5859 <td valign="top" align="center">wo</td> 5860 <td valign="top" align="center">0x0</td> 5861 <td valign="top">Writing to this address resets the only FSM of CHACHA engine. The reset takes 4 CORE_CLK cycles.</td> 5862 </tr> 5863 <tr> 5864 <td valign="top" align="center"><a name="1.3.17.2"></a>31:1 5865 </td> 5866 <td valign="top">RESERVED</td> 5867 <td valign="top" align="center">wo</td> 5868 <td valign="top" align="center">0x0</td> 5869 <td valign="top">Reserved</td> 5870 </tr> 5871</table><a name="1.3.18"></a><br>1.3.18 : <b>Reg : CHACHA_FOR_POLY_KEY0</b> : 0x0000003C4<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 255:224 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 5872 <tr> 5873 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY0</td> 5874 </tr> 5875 <tr></tr> 5876</table> 5877<table border="1" width="800"> 5878 <tr> 5879 <td width="40"><b>bits</b></td> 5880 <td width="100"><b>Field name</b></td> 5881 <td width="20"><b>permission</b></td> 5882 <td width="40"><b>default</b></td> 5883 <td width="600"><b>Description</b></td> 5884 </tr> 5885 <tr> 5886 <td valign="top" align="center"><a name="1.3.18.1"></a>31:0 5887 </td> 5888 <td valign="top">CHACHA_FOR_POLY_KEY0</td> 5889 <td valign="top" align="center">ro</td> 5890 <td valign="top" align="center">0x0</td> 5891 <td valign="top">bits 255:224 of CHACHA_FOR_POLY_KEY</td> 5892 </tr> 5893</table><a name="1.3.19"></a><br>1.3.19 : <b>Reg : CHACHA_FOR_POLY_KEY1</b> : 0x0000003C8<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 223:192 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 5894 <tr> 5895 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY1</td> 5896 </tr> 5897 <tr></tr> 5898</table> 5899<table border="1" width="800"> 5900 <tr> 5901 <td width="40"><b>bits</b></td> 5902 <td width="100"><b>Field name</b></td> 5903 <td width="20"><b>permission</b></td> 5904 <td width="40"><b>default</b></td> 5905 <td width="600"><b>Description</b></td> 5906 </tr> 5907 <tr> 5908 <td valign="top" align="center"><a name="1.3.19.1"></a>31:0 5909 </td> 5910 <td valign="top">CHACHA_FOR_POLY_KEY1</td> 5911 <td valign="top" align="center">ro</td> 5912 <td valign="top" align="center">0x0</td> 5913 <td valign="top">bits 223:192 of CHACHA_FOR_POLY_KEY</td> 5914 </tr> 5915</table><a name="1.3.20"></a><br>1.3.20 : <b>Reg : CHACHA_FOR_POLY_KEY2</b> : 0x0000003CC<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits191:160 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 5916 <tr> 5917 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY2</td> 5918 </tr> 5919 <tr></tr> 5920</table> 5921<table border="1" width="800"> 5922 <tr> 5923 <td width="40"><b>bits</b></td> 5924 <td width="100"><b>Field name</b></td> 5925 <td width="20"><b>permission</b></td> 5926 <td width="40"><b>default</b></td> 5927 <td width="600"><b>Description</b></td> 5928 </tr> 5929 <tr> 5930 <td valign="top" align="center"><a name="1.3.20.1"></a>31:0 5931 </td> 5932 <td valign="top">CHACHA_FOR_POLY_KEY2</td> 5933 <td valign="top" align="center">ro</td> 5934 <td valign="top" align="center">0x0</td> 5935 <td valign="top">bits191:160 of CHACHA_FOR_POLY_KEY</td> 5936 </tr> 5937</table><a name="1.3.21"></a><br>1.3.21 : <b>Reg : CHACHA_FOR_POLY_KEY3</b> : 0x0000003D0<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits159:128 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 5938 <tr> 5939 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY3</td> 5940 </tr> 5941 <tr></tr> 5942</table> 5943<table border="1" width="800"> 5944 <tr> 5945 <td width="40"><b>bits</b></td> 5946 <td width="100"><b>Field name</b></td> 5947 <td width="20"><b>permission</b></td> 5948 <td width="40"><b>default</b></td> 5949 <td width="600"><b>Description</b></td> 5950 </tr> 5951 <tr> 5952 <td valign="top" align="center"><a name="1.3.21.1"></a>31:0 5953 </td> 5954 <td valign="top">CHACHA_FOR_POLY_KEY3</td> 5955 <td valign="top" align="center">ro</td> 5956 <td valign="top" align="center">0x0</td> 5957 <td valign="top">bits 159:128 of CHACHA_FOR_POLY_KEY</td> 5958 </tr> 5959</table><a name="1.3.22"></a><br>1.3.22 : <b>Reg : CHACHA_FOR_POLY_KEY4</b> : 0x0000003D4<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 5960 <tr> 5961 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY4</td> 5962 </tr> 5963 <tr></tr> 5964</table> 5965<table border="1" width="800"> 5966 <tr> 5967 <td width="40"><b>bits</b></td> 5968 <td width="100"><b>Field name</b></td> 5969 <td width="20"><b>permission</b></td> 5970 <td width="40"><b>default</b></td> 5971 <td width="600"><b>Description</b></td> 5972 </tr> 5973 <tr> 5974 <td valign="top" align="center"><a name="1.3.22.1"></a>31:0 5975 </td> 5976 <td valign="top">CHACHA_FOR_POLY_KEY4</td> 5977 <td valign="top" align="center">ro</td> 5978 <td valign="top" align="center">0x0</td> 5979 <td valign="top">bits 127:96 of CHACHA_FOR_POLY_KEY</td> 5980 </tr> 5981</table><a name="1.3.23"></a><br>1.3.23 : <b>Reg : CHACHA_FOR_POLY_KEY5</b> : 0x0000003D8<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 5982 <tr> 5983 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY5</td> 5984 </tr> 5985 <tr></tr> 5986</table> 5987<table border="1" width="800"> 5988 <tr> 5989 <td width="40"><b>bits</b></td> 5990 <td width="100"><b>Field name</b></td> 5991 <td width="20"><b>permission</b></td> 5992 <td width="40"><b>default</b></td> 5993 <td width="600"><b>Description</b></td> 5994 </tr> 5995 <tr> 5996 <td valign="top" align="center"><a name="1.3.23.1"></a>31:0 5997 </td> 5998 <td valign="top">CHACHA_FOR_POLY_KEY5</td> 5999 <td valign="top" align="center">ro</td> 6000 <td valign="top" align="center">0x0</td> 6001 <td valign="top">bits 95:64 of CHACHA_FOR_POLY_KEY</td> 6002 </tr> 6003</table><a name="1.3.24"></a><br>1.3.24 : <b>Reg : CHACHA_FOR_POLY_KEY6</b> : 0x0000003DC<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 6004 <tr> 6005 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY6</td> 6006 </tr> 6007 <tr></tr> 6008</table> 6009<table border="1" width="800"> 6010 <tr> 6011 <td width="40"><b>bits</b></td> 6012 <td width="100"><b>Field name</b></td> 6013 <td width="20"><b>permission</b></td> 6014 <td width="40"><b>default</b></td> 6015 <td width="600"><b>Description</b></td> 6016 </tr> 6017 <tr> 6018 <td valign="top" align="center"><a name="1.3.24.1"></a>31:0 6019 </td> 6020 <td valign="top">CHACHA_FOR_POLY_KEY6</td> 6021 <td valign="top" align="center">ro</td> 6022 <td valign="top" align="center">0x0</td> 6023 <td valign="top">bits 63:32 of CHACHA_FOR_POLY_KEY</td> 6024 </tr> 6025</table><a name="1.3.25"></a><br>1.3.25 : <b>Reg : CHACHA_FOR_POLY_KEY7</b> : 0x0000003E0<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of CHACHA_FOR_POLY_KEY<br><table border="1" bgcolor="#EEEEEE" width="800"> 6026 <tr> 6027 <td colspan="32" align="center">CHACHA_FOR_POLY_KEY7</td> 6028 </tr> 6029 <tr></tr> 6030</table> 6031<table border="1" width="800"> 6032 <tr> 6033 <td width="40"><b>bits</b></td> 6034 <td width="100"><b>Field name</b></td> 6035 <td width="20"><b>permission</b></td> 6036 <td width="40"><b>default</b></td> 6037 <td width="600"><b>Description</b></td> 6038 </tr> 6039 <tr> 6040 <td valign="top" align="center"><a name="1.3.25.1"></a>31:0 6041 </td> 6042 <td valign="top">CHACHA_FOR_POLY_KEY7</td> 6043 <td valign="top" align="center">ro</td> 6044 <td valign="top" align="center">0x0</td> 6045 <td valign="top">bits 31:0 of CHACHA_FOR_POLY_KEY</td> 6046 </tr> 6047</table><a name="1.3.26"></a><br>1.3.26 : <b>Reg : CHACHA_BYTE_WORD_ORDER_CNTL_REG</b> : 0x0000003E4<br><b>reg sep address</b> : <b> reg host address</b> : <br>CHACHA/SALSA DATA ORDER configuration.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6048 <tr> 6049 <td colspan="32" align="center">CHACHA_BYTE_WORD_ORDER_CNTL_REG</td> 6050 </tr> 6051 <tr></tr> 6052</table> 6053<table border="1" width="800"> 6054 <tr> 6055 <td width="40"><b>bits</b></td> 6056 <td width="100"><b>Field name</b></td> 6057 <td width="20"><b>permission</b></td> 6058 <td width="40"><b>default</b></td> 6059 <td width="600"><b>Description</b></td> 6060 </tr> 6061 <tr> 6062 <td valign="top" align="center"><a name="1.3.26.1"></a>0:0 6063 </td> 6064 <td valign="top">CHACHA_DIN_WORD_ORDER</td> 6065 <td valign="top" align="center">rw</td> 6066 <td valign="top" align="center">0x0</td> 6067 <td valign="top">Change the words order of the input data.<br>@1'b0 - disable. <br>@1'b1 - enable. (reverse each word in 128 bit input ( w0->w3, w1->w2, w2->w1,w3-w0)) 6068 </td> 6069 </tr> 6070 <tr> 6071 <td valign="top" align="center"><a name="1.3.26.2"></a>1:1 6072 </td> 6073 <td valign="top">CHACHA_DIN_BYTE_ORDER</td> 6074 <td valign="top" align="center">rw</td> 6075 <td valign="top" align="center">0x0</td> 6076 <td valign="top">Change the byte order of the input data.<br>@1'b0 - disable. <br>@1'b1 - enable. (reverse each byte in each word input (b0->b3, b1->b2, b2->b1,b3->b0)) 6077 </td> 6078 </tr> 6079 <tr> 6080 <td valign="top" align="center"><a name="1.3.26.3"></a>2:2 6081 </td> 6082 <td valign="top">CHACHA_CORE_MATRIX_LBE_ORDER</td> 6083 <td valign="top" align="center">rw</td> 6084 <td valign="top" align="center">0x0</td> 6085 <td valign="top">Change the quarter of a matrix order in core<br>@1'b0 - disable. <br>@1'b1 - enable. (reverse each quarter of a matrix (m[0-127]->m[384-511], m[128-255]->m[256-383], m[256-383]->m[128-255], m[384-511]->m[0-127])) 6086 </td> 6087 </tr> 6088 <tr> 6089 <td valign="top" align="center"><a name="1.3.26.4"></a>3:3 6090 </td> 6091 <td valign="top">CHACHA_DOUT_WORD_ORDER</td> 6092 <td valign="top" align="center">rw</td> 6093 <td valign="top" align="center">0x0</td> 6094 <td valign="top">Change the words order of the output data.<br>@1'b0 - disable. <br>@1'b1 - enable. (reverse each word in 128 bit output ( w0->w3, w1->w2, w2->w1,w3-w0)) 6095 </td> 6096 </tr> 6097 <tr> 6098 <td valign="top" align="center"><a name="1.3.26.5"></a>4:4 6099 </td> 6100 <td valign="top">CHACHA_DOUT_BYTE_ORDER</td> 6101 <td valign="top" align="center">rw</td> 6102 <td valign="top" align="center">0x0</td> 6103 <td valign="top">Change the byte order of the output data.<br>@1'b0 - disable. <br>@1'b1 - enable. (reverse each byte in each word output (b0->b3, b1->b2, b2->b1,b3->b0)) 6104 </td> 6105 </tr> 6106 <tr> 6107 <td valign="top" align="center"><a name="1.3.26.6"></a>31:5 6108 </td> 6109 <td valign="top">RESERVED</td> 6110 <td valign="top" align="center">rw</td> 6111 <td valign="top" align="center">0x0</td> 6112 <td valign="top">Reserved</td> 6113 </tr> 6114</table><a name="1.3.27"></a><br>1.3.27 : <b>Reg : CHACHA_DEBUG_REG</b> : 0x0000003E8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is used to debug the CHACHA engine<br><table border="1" bgcolor="#EEEEEE" width="800"> 6115 <tr> 6116 <td colspan="32" align="center">CHACHA_DEBUG_REG</td> 6117 </tr> 6118 <tr></tr> 6119</table> 6120<table border="1" width="800"> 6121 <tr> 6122 <td width="40"><b>bits</b></td> 6123 <td width="100"><b>Field name</b></td> 6124 <td width="20"><b>permission</b></td> 6125 <td width="40"><b>default</b></td> 6126 <td width="600"><b>Description</b></td> 6127 </tr> 6128 <tr> 6129 <td valign="top" align="center"><a name="1.3.27.1"></a>1:0 6130 </td> 6131 <td valign="top">CHACHA_DEBUG_FSM_STATE</td> 6132 <td valign="top" align="center">ro</td> 6133 <td valign="top" align="center">0x0</td> 6134 <td valign="top">CHACHA_DEBUG_FSM_STATE<br>@0x0 - IDLE_STATE<br>@0x1 - INIT_STATE<br>@0x2 - ROUNDS_STATE<br>@0x3 - FINAL_STATE 6135 </td> 6136 </tr> 6137 <tr> 6138 <td valign="top" align="center"><a name="1.3.27.2"></a>31:2 6139 </td> 6140 <td valign="top">RESERVED</td> 6141 <td valign="top" align="center">ro</td> 6142 <td valign="top" align="center">0x0</td> 6143 <td valign="top">Reserved</td> 6144 </tr> 6145</table><a href="#1.3">(top of block)</a><a name="1.4"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 6146 <td><b><font color="#000000">1.4 : Block: AES</font></b></td> 6147 <td align="right"><font color="#000000">0x000000400</font></td> 6148</table><br><a name="1.4.1"></a><br>1.4.1 : <b>Reg : AES_KEY_0_0</b> : 0x000000400<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6149 <tr> 6150 <td colspan="32" align="center">AES_KEY_0_0</td> 6151 </tr> 6152 <tr></tr> 6153</table> 6154<table border="1" width="800"> 6155 <tr> 6156 <td width="40"><b>bits</b></td> 6157 <td width="100"><b>Field name</b></td> 6158 <td width="20"><b>permission</b></td> 6159 <td width="40"><b>default</b></td> 6160 <td width="600"><b>Description</b></td> 6161 </tr> 6162 <tr> 6163 <td valign="top" align="center"><a name="1.4.1.1"></a>31:0 6164 </td> 6165 <td valign="top">AES_KEY_0_0</td> 6166 <td valign="top" align="center">wo</td> 6167 <td valign="top" align="center">0x0</td> 6168 <td valign="top">bits 31:0 of AES Key0.</td> 6169 </tr> 6170</table><a name="1.4.2"></a><br>1.4.2 : <b>Reg : AES_KEY_0_1</b> : 0x000000404<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6171 <tr> 6172 <td colspan="32" align="center">AES_KEY_0_1</td> 6173 </tr> 6174 <tr></tr> 6175</table> 6176<table border="1" width="800"> 6177 <tr> 6178 <td width="40"><b>bits</b></td> 6179 <td width="100"><b>Field name</b></td> 6180 <td width="20"><b>permission</b></td> 6181 <td width="40"><b>default</b></td> 6182 <td width="600"><b>Description</b></td> 6183 </tr> 6184 <tr> 6185 <td valign="top" align="center"><a name="1.4.2.1"></a>31:0 6186 </td> 6187 <td valign="top">AES_KEY_0_1</td> 6188 <td valign="top" align="center">wo</td> 6189 <td valign="top" align="center">0x0</td> 6190 <td valign="top">bits 63:32 of AES Key0.</td> 6191 </tr> 6192</table><a name="1.4.3"></a><br>1.4.3 : <b>Reg : AES_KEY_0_2</b> : 0x000000408<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6193 <tr> 6194 <td colspan="32" align="center">AES_KEY_0_2</td> 6195 </tr> 6196 <tr></tr> 6197</table> 6198<table border="1" width="800"> 6199 <tr> 6200 <td width="40"><b>bits</b></td> 6201 <td width="100"><b>Field name</b></td> 6202 <td width="20"><b>permission</b></td> 6203 <td width="40"><b>default</b></td> 6204 <td width="600"><b>Description</b></td> 6205 </tr> 6206 <tr> 6207 <td valign="top" align="center"><a name="1.4.3.1"></a>31:0 6208 </td> 6209 <td valign="top">AES_KEY_0_2</td> 6210 <td valign="top" align="center">wo</td> 6211 <td valign="top" align="center">0x0</td> 6212 <td valign="top">bits 95:64 of AES Key0.</td> 6213 </tr> 6214</table><a name="1.4.4"></a><br>1.4.4 : <b>Reg : AES_KEY_0_3</b> : 0x00000040C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6215 <tr> 6216 <td colspan="32" align="center">AES_KEY_0_3</td> 6217 </tr> 6218 <tr></tr> 6219</table> 6220<table border="1" width="800"> 6221 <tr> 6222 <td width="40"><b>bits</b></td> 6223 <td width="100"><b>Field name</b></td> 6224 <td width="20"><b>permission</b></td> 6225 <td width="40"><b>default</b></td> 6226 <td width="600"><b>Description</b></td> 6227 </tr> 6228 <tr> 6229 <td valign="top" align="center"><a name="1.4.4.1"></a>31:0 6230 </td> 6231 <td valign="top">AES_KEY_0_3</td> 6232 <td valign="top" align="center">wo</td> 6233 <td valign="top" align="center">0x0</td> 6234 <td valign="top">bits 127:96 of AES Key0.</td> 6235 </tr> 6236</table><a name="1.4.5"></a><br>1.4.5 : <b>Reg : AES_KEY_0_4</b> : 0x000000410<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 159:128 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling 6237operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6238 <tr> 6239 <td colspan="32" align="center">AES_KEY_0_4</td> 6240 </tr> 6241 <tr></tr> 6242</table> 6243<table border="1" width="800"> 6244 <tr> 6245 <td width="40"><b>bits</b></td> 6246 <td width="100"><b>Field name</b></td> 6247 <td width="20"><b>permission</b></td> 6248 <td width="40"><b>default</b></td> 6249 <td width="600"><b>Description</b></td> 6250 </tr> 6251 <tr> 6252 <td valign="top" align="center"><a name="1.4.5.1"></a>31:0 6253 </td> 6254 <td valign="top">AES_KEY_0_4</td> 6255 <td valign="top" align="center">wo</td> 6256 <td valign="top" align="center">0x0</td> 6257 <td valign="top">bits 159:128 of AES Key0 .</td> 6258 </tr> 6259</table><a name="1.4.6"></a><br>1.4.6 : <b>Reg : AES_KEY_0_5</b> : 0x000000414<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 191:160 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling 6260operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6261 <tr> 6262 <td colspan="32" align="center">AES_KEY_0_5</td> 6263 </tr> 6264 <tr></tr> 6265</table> 6266<table border="1" width="800"> 6267 <tr> 6268 <td width="40"><b>bits</b></td> 6269 <td width="100"><b>Field name</b></td> 6270 <td width="20"><b>permission</b></td> 6271 <td width="40"><b>default</b></td> 6272 <td width="600"><b>Description</b></td> 6273 </tr> 6274 <tr> 6275 <td valign="top" align="center"><a name="1.4.6.1"></a>31:0 6276 </td> 6277 <td valign="top">AES_KEY_0_5</td> 6278 <td valign="top" align="center">wo</td> 6279 <td valign="top" align="center">0x0</td> 6280 <td valign="top">bits 191:160 of AES Key0.</td> 6281 </tr> 6282</table><a name="1.4.7"></a><br>1.4.7 : <b>Reg : AES_KEY_0_6</b> : 0x000000418<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 223:192 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling 6283operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6284 <tr> 6285 <td colspan="32" align="center">AES_KEY_0_6</td> 6286 </tr> 6287 <tr></tr> 6288</table> 6289<table border="1" width="800"> 6290 <tr> 6291 <td width="40"><b>bits</b></td> 6292 <td width="100"><b>Field name</b></td> 6293 <td width="20"><b>permission</b></td> 6294 <td width="40"><b>default</b></td> 6295 <td width="600"><b>Description</b></td> 6296 </tr> 6297 <tr> 6298 <td valign="top" align="center"><a name="1.4.7.1"></a>31:0 6299 </td> 6300 <td valign="top">AES_KEY_0_6</td> 6301 <td valign="top" align="center">wo</td> 6302 <td valign="top" align="center">0x0</td> 6303 <td valign="top">bits 223:192 of AES Key0.</td> 6304 </tr> 6305</table><a name="1.4.8"></a><br>1.4.8 : <b>Reg : AES_KEY_0_7</b> : 0x00000041C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 255:224 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling 6306operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6307 <tr> 6308 <td colspan="32" align="center">AES_KEY_0_7</td> 6309 </tr> 6310 <tr></tr> 6311</table> 6312<table border="1" width="800"> 6313 <tr> 6314 <td width="40"><b>bits</b></td> 6315 <td width="100"><b>Field name</b></td> 6316 <td width="20"><b>permission</b></td> 6317 <td width="40"><b>default</b></td> 6318 <td width="600"><b>Description</b></td> 6319 </tr> 6320 <tr> 6321 <td valign="top" align="center"><a name="1.4.8.1"></a>31:0 6322 </td> 6323 <td valign="top">AES_KEY_0_7</td> 6324 <td valign="top" align="center">wo</td> 6325 <td valign="top" align="center">0x0</td> 6326 <td valign="top">bits 255:224 of AES Key0.</td> 6327 </tr> 6328</table><a name="1.4.9"></a><br>1.4.9 : <b>Reg : AES_KEY_1_0</b> : 0x000000420<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6329 <tr> 6330 <td colspan="32" align="center">AES_KEY_1_0</td> 6331 </tr> 6332 <tr></tr> 6333</table> 6334<table border="1" width="800"> 6335 <tr> 6336 <td width="40"><b>bits</b></td> 6337 <td width="100"><b>Field name</b></td> 6338 <td width="20"><b>permission</b></td> 6339 <td width="40"><b>default</b></td> 6340 <td width="600"><b>Description</b></td> 6341 </tr> 6342 <tr> 6343 <td valign="top" align="center"><a name="1.4.9.1"></a>31:0 6344 </td> 6345 <td valign="top">AES_KEY_1_0</td> 6346 <td valign="top" align="center">wo</td> 6347 <td valign="top" align="center">0x0</td> 6348 <td valign="top">bits 31:0 of AES Key1.</td> 6349 </tr> 6350</table><a name="1.4.10"></a><br>1.4.10 : <b>Reg : AES_KEY_1_1</b> : 0x000000424<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6351 <tr> 6352 <td colspan="32" align="center">AES_KEY_1_1</td> 6353 </tr> 6354 <tr></tr> 6355</table> 6356<table border="1" width="800"> 6357 <tr> 6358 <td width="40"><b>bits</b></td> 6359 <td width="100"><b>Field name</b></td> 6360 <td width="20"><b>permission</b></td> 6361 <td width="40"><b>default</b></td> 6362 <td width="600"><b>Description</b></td> 6363 </tr> 6364 <tr> 6365 <td valign="top" align="center"><a name="1.4.10.1"></a>31:0 6366 </td> 6367 <td valign="top">AES_KEY_1_1</td> 6368 <td valign="top" align="center">wo</td> 6369 <td valign="top" align="center">0x0</td> 6370 <td valign="top">bits 63:32 of AES Key1.</td> 6371 </tr> 6372</table><a name="1.4.11"></a><br>1.4.11 : <b>Reg : AES_KEY_1_2</b> : 0x000000428<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6373 <tr> 6374 <td colspan="32" align="center">AES_KEY_1_2</td> 6375 </tr> 6376 <tr></tr> 6377</table> 6378<table border="1" width="800"> 6379 <tr> 6380 <td width="40"><b>bits</b></td> 6381 <td width="100"><b>Field name</b></td> 6382 <td width="20"><b>permission</b></td> 6383 <td width="40"><b>default</b></td> 6384 <td width="600"><b>Description</b></td> 6385 </tr> 6386 <tr> 6387 <td valign="top" align="center"><a name="1.4.11.1"></a>31:0 6388 </td> 6389 <td valign="top">AES_KEY_1_2</td> 6390 <td valign="top" align="center">wo</td> 6391 <td valign="top" align="center">0x0</td> 6392 <td valign="top">bits 95:64 of AES Key1.</td> 6393 </tr> 6394</table><a name="1.4.12"></a><br>1.4.12 : <b>Reg : AES_KEY_1_3</b> : 0x00000042C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6395 <tr> 6396 <td colspan="32" align="center">AES_KEY_1_3</td> 6397 </tr> 6398 <tr></tr> 6399</table> 6400<table border="1" width="800"> 6401 <tr> 6402 <td width="40"><b>bits</b></td> 6403 <td width="100"><b>Field name</b></td> 6404 <td width="20"><b>permission</b></td> 6405 <td width="40"><b>default</b></td> 6406 <td width="600"><b>Description</b></td> 6407 </tr> 6408 <tr> 6409 <td valign="top" align="center"><a name="1.4.12.1"></a>31:0 6410 </td> 6411 <td valign="top">AES_KEY_1_3</td> 6412 <td valign="top" align="center">wo</td> 6413 <td valign="top" align="center">0x0</td> 6414 <td valign="top">bits 127:96 of AES Key1.</td> 6415 </tr> 6416</table><a name="1.4.13"></a><br>1.4.13 : <b>Reg : AES_KEY_1_4</b> : 0x000000430<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 159:128 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6417 <tr> 6418 <td colspan="32" align="center">AES_KEY_1_4</td> 6419 </tr> 6420 <tr></tr> 6421</table> 6422<table border="1" width="800"> 6423 <tr> 6424 <td width="40"><b>bits</b></td> 6425 <td width="100"><b>Field name</b></td> 6426 <td width="20"><b>permission</b></td> 6427 <td width="40"><b>default</b></td> 6428 <td width="600"><b>Description</b></td> 6429 </tr> 6430 <tr> 6431 <td valign="top" align="center"><a name="1.4.13.1"></a>31:0 6432 </td> 6433 <td valign="top">AES_KEY_1_4</td> 6434 <td valign="top" align="center">wo</td> 6435 <td valign="top" align="center">0x0</td> 6436 <td valign="top">bits 159:128 of AES Key1.</td> 6437 </tr> 6438</table><a name="1.4.14"></a><br>1.4.14 : <b>Reg : AES_KEY_1_5</b> : 0x000000434<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 191:160 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6439 <tr> 6440 <td colspan="32" align="center">AES_KEY_1_5</td> 6441 </tr> 6442 <tr></tr> 6443</table> 6444<table border="1" width="800"> 6445 <tr> 6446 <td width="40"><b>bits</b></td> 6447 <td width="100"><b>Field name</b></td> 6448 <td width="20"><b>permission</b></td> 6449 <td width="40"><b>default</b></td> 6450 <td width="600"><b>Description</b></td> 6451 </tr> 6452 <tr> 6453 <td valign="top" align="center"><a name="1.4.14.1"></a>31:0 6454 </td> 6455 <td valign="top">AES_KEY_1_5</td> 6456 <td valign="top" align="center">wo</td> 6457 <td valign="top" align="center">0x0</td> 6458 <td valign="top">bits 191:160 of AES Key1.</td> 6459 </tr> 6460</table><a name="1.4.15"></a><br>1.4.15 : <b>Reg : AES_KEY_1_6</b> : 0x000000438<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 223:192 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6461 <tr> 6462 <td colspan="32" align="center">AES_KEY_1_6</td> 6463 </tr> 6464 <tr></tr> 6465</table> 6466<table border="1" width="800"> 6467 <tr> 6468 <td width="40"><b>bits</b></td> 6469 <td width="100"><b>Field name</b></td> 6470 <td width="20"><b>permission</b></td> 6471 <td width="40"><b>default</b></td> 6472 <td width="600"><b>Description</b></td> 6473 </tr> 6474 <tr> 6475 <td valign="top" align="center"><a name="1.4.15.1"></a>31:0 6476 </td> 6477 <td valign="top">AES_KEY_1_6</td> 6478 <td valign="top" align="center">wo</td> 6479 <td valign="top" align="center">0x0</td> 6480 <td valign="top">bits 223:192 of AES Key1.</td> 6481 </tr> 6482</table><a name="1.4.16"></a><br>1.4.16 : <b>Reg : AES_KEY_1_7</b> : 0x00000043C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 255:224 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6483 <tr> 6484 <td colspan="32" align="center">AES_KEY_1_7</td> 6485 </tr> 6486 <tr></tr> 6487</table> 6488<table border="1" width="800"> 6489 <tr> 6490 <td width="40"><b>bits</b></td> 6491 <td width="100"><b>Field name</b></td> 6492 <td width="20"><b>permission</b></td> 6493 <td width="40"><b>default</b></td> 6494 <td width="600"><b>Description</b></td> 6495 </tr> 6496 <tr> 6497 <td valign="top" align="center"><a name="1.4.16.1"></a>31:0 6498 </td> 6499 <td valign="top">AES_KEY_1_7</td> 6500 <td valign="top" align="center">wo</td> 6501 <td valign="top" align="center">0x0</td> 6502 <td valign="top">bits 255:224 of AES Key1.</td> 6503 </tr> 6504</table><a name="1.4.17"></a><br>1.4.17 : <b>Reg : AES_IV_0_0</b> : 0x000000440<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of AES_IV0 register. <br>AES IV0 is used as the AES IV (Initialization Value) register in non-tunneling operations, <br>and as the first tunnel stage IV register in tunneling operations. <br>The IV register should be loaded according to the AES mode:<br>in AES CBC/CBC-MAC - the AES IV register should be loaded with the IV (initialization vector).<br>in XTS-AES - the AES IV register should be loaded with the 'T' value (unless the HW T calculation mode is active, in which 6505the 'T' value is calculated by the HW).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6506 <tr> 6507 <td colspan="32" align="center">AES_IV_0_0</td> 6508 </tr> 6509 <tr></tr> 6510</table> 6511<table border="1" width="800"> 6512 <tr> 6513 <td width="40"><b>bits</b></td> 6514 <td width="100"><b>Field name</b></td> 6515 <td width="20"><b>permission</b></td> 6516 <td width="40"><b>default</b></td> 6517 <td width="600"><b>Description</b></td> 6518 </tr> 6519 <tr> 6520 <td valign="top" align="center"><a name="1.4.17.1"></a>31:0 6521 </td> 6522 <td valign="top">AES_IV_0_0</td> 6523 <td valign="top" align="center">r/wc</td> 6524 <td valign="top" align="center">0x0</td> 6525 <td valign="top">bits 31:0 of AES_IV0 register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description 6526 </td> 6527 </tr> 6528</table><a name="1.4.18"></a><br>1.4.18 : <b>Reg : AES_IV_0_1</b> : 0x000000444<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of AES_IV0 128b register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description<br><table border="1" bgcolor="#EEEEEE" width="800"> 6529 <tr> 6530 <td colspan="32" align="center">AES_IV_0_1</td> 6531 </tr> 6532 <tr></tr> 6533</table> 6534<table border="1" width="800"> 6535 <tr> 6536 <td width="40"><b>bits</b></td> 6537 <td width="100"><b>Field name</b></td> 6538 <td width="20"><b>permission</b></td> 6539 <td width="40"><b>default</b></td> 6540 <td width="600"><b>Description</b></td> 6541 </tr> 6542 <tr> 6543 <td valign="top" align="center"><a name="1.4.18.1"></a>31:0 6544 </td> 6545 <td valign="top">AES_IV_0_1</td> 6546 <td valign="top" align="center">r/wc</td> 6547 <td valign="top" align="center">0x0</td> 6548 <td valign="top">bits 63:32 of AES_IV0 register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description 6549 </td> 6550 </tr> 6551</table><a name="1.4.19"></a><br>1.4.19 : <b>Reg : AES_IV_0_2</b> : 0x000000448<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of AES_IV0 128b register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description<br><table border="1" bgcolor="#EEEEEE" width="800"> 6552 <tr> 6553 <td colspan="32" align="center">AES_IV_0_2</td> 6554 </tr> 6555 <tr></tr> 6556</table> 6557<table border="1" width="800"> 6558 <tr> 6559 <td width="40"><b>bits</b></td> 6560 <td width="100"><b>Field name</b></td> 6561 <td width="20"><b>permission</b></td> 6562 <td width="40"><b>default</b></td> 6563 <td width="600"><b>Description</b></td> 6564 </tr> 6565 <tr> 6566 <td valign="top" align="center"><a name="1.4.19.1"></a>31:0 6567 </td> 6568 <td valign="top">AES_IV_0_2</td> 6569 <td valign="top" align="center">r/wc</td> 6570 <td valign="top" align="center">0x0</td> 6571 <td valign="top">bits 95:64 of AES_IV0 register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description 6572 </td> 6573 </tr> 6574</table><a name="1.4.20"></a><br>1.4.20 : <b>Reg : AES_IV_0_3</b> : 0x00000044C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of AES_IV0 128b register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description<br><table border="1" bgcolor="#EEEEEE" width="800"> 6575 <tr> 6576 <td colspan="32" align="center">AES_IV_0_3</td> 6577 </tr> 6578 <tr></tr> 6579</table> 6580<table border="1" width="800"> 6581 <tr> 6582 <td width="40"><b>bits</b></td> 6583 <td width="100"><b>Field name</b></td> 6584 <td width="20"><b>permission</b></td> 6585 <td width="40"><b>default</b></td> 6586 <td width="600"><b>Description</b></td> 6587 </tr> 6588 <tr> 6589 <td valign="top" align="center"><a name="1.4.20.1"></a>31:0 6590 </td> 6591 <td valign="top">AES_IV_0_3</td> 6592 <td valign="top" align="center">r/wc</td> 6593 <td valign="top" align="center">0x0</td> 6594 <td valign="top">bits 127:96 of AES_IV0 register. <br>For the description of AES_IV0, see the AES_IV_0_0 register description 6595 </td> 6596 </tr> 6597</table><a name="1.4.21"></a><br>1.4.21 : <b>Reg : AES_IV_1_0</b> : 0x000000450<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of AES_IV1 128b register. <br>AES IV1 is used as the AES IV (Initialization Value) register as the second tunnel stage IV register in tunneling operations. 6598<br>The IV register should be loaded according to the AES mode:<br>in AES CBC/CBC-MAC - the AES IV register should be loaded with the IV (initialization vector).<br>in XTS-AES - the AES IV register should be loaded with the 'T' value (unless the HW T calculation mode is active, in which 6599the 'T' value is calculated by the HW.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6600 <tr> 6601 <td colspan="32" align="center">AES_IV_1_0</td> 6602 </tr> 6603 <tr></tr> 6604</table> 6605<table border="1" width="800"> 6606 <tr> 6607 <td width="40"><b>bits</b></td> 6608 <td width="100"><b>Field name</b></td> 6609 <td width="20"><b>permission</b></td> 6610 <td width="40"><b>default</b></td> 6611 <td width="600"><b>Description</b></td> 6612 </tr> 6613 <tr> 6614 <td valign="top" align="center"><a name="1.4.21.1"></a>31:0 6615 </td> 6616 <td valign="top">AES_IV_1_0</td> 6617 <td valign="top" align="center">r/wc</td> 6618 <td valign="top" align="center">0x0</td> 6619 <td valign="top">bits 31:0 of AES_IV1 register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description 6620 </td> 6621 </tr> 6622</table><a name="1.4.22"></a><br>1.4.22 : <b>Reg : AES_IV_1_1</b> : 0x000000454<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of AES_IV1 128b register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description<br><table border="1" bgcolor="#EEEEEE" width="800"> 6623 <tr> 6624 <td colspan="32" align="center">AES_IV_1_1</td> 6625 </tr> 6626 <tr></tr> 6627</table> 6628<table border="1" width="800"> 6629 <tr> 6630 <td width="40"><b>bits</b></td> 6631 <td width="100"><b>Field name</b></td> 6632 <td width="20"><b>permission</b></td> 6633 <td width="40"><b>default</b></td> 6634 <td width="600"><b>Description</b></td> 6635 </tr> 6636 <tr> 6637 <td valign="top" align="center"><a name="1.4.22.1"></a>31:0 6638 </td> 6639 <td valign="top">AES_IV_1_1</td> 6640 <td valign="top" align="center">r/wc</td> 6641 <td valign="top" align="center">0x0</td> 6642 <td valign="top">bits 63:32 of AES_IV1 register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description 6643 </td> 6644 </tr> 6645</table><a name="1.4.23"></a><br>1.4.23 : <b>Reg : AES_IV_1_2</b> : 0x000000458<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of AES_IV1 128b register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description<br><table border="1" bgcolor="#EEEEEE" width="800"> 6646 <tr> 6647 <td colspan="32" align="center">AES_IV_1_2</td> 6648 </tr> 6649 <tr></tr> 6650</table> 6651<table border="1" width="800"> 6652 <tr> 6653 <td width="40"><b>bits</b></td> 6654 <td width="100"><b>Field name</b></td> 6655 <td width="20"><b>permission</b></td> 6656 <td width="40"><b>default</b></td> 6657 <td width="600"><b>Description</b></td> 6658 </tr> 6659 <tr> 6660 <td valign="top" align="center"><a name="1.4.23.1"></a>31:0 6661 </td> 6662 <td valign="top">AES_IV_1_2</td> 6663 <td valign="top" align="center">r/wc</td> 6664 <td valign="top" align="center">0x0</td> 6665 <td valign="top">bits 95:64 of AES_IV1 register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description 6666 </td> 6667 </tr> 6668</table><a name="1.4.24"></a><br>1.4.24 : <b>Reg : AES_IV_1_3</b> : 0x00000045C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of AES_IV1 128b register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description<br><table border="1" bgcolor="#EEEEEE" width="800"> 6669 <tr> 6670 <td colspan="32" align="center">AES_IV_1_3</td> 6671 </tr> 6672 <tr></tr> 6673</table> 6674<table border="1" width="800"> 6675 <tr> 6676 <td width="40"><b>bits</b></td> 6677 <td width="100"><b>Field name</b></td> 6678 <td width="20"><b>permission</b></td> 6679 <td width="40"><b>default</b></td> 6680 <td width="600"><b>Description</b></td> 6681 </tr> 6682 <tr> 6683 <td valign="top" align="center"><a name="1.4.24.1"></a>31:0 6684 </td> 6685 <td valign="top">AES_IV_1_3</td> 6686 <td valign="top" align="center">r/wc</td> 6687 <td valign="top" align="center">0x0</td> 6688 <td valign="top">bits 127:96 of AES_IV1 register. <br>For the description of AES_IV1, see the AES_IV_1_0 register description 6689 </td> 6690 </tr> 6691</table><a name="1.4.25"></a><br>1.4.25 : <b>Reg : AES_CTR_0_0</b> : 0x000000460<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 31:0 of AES_CTR0 128b register. <br>AES CTR0 is used as the AES CTR (counter) register in non-tunneling operations, and as the first tunnel stage CTR register 6692in tunneling operations. <br>The CTR register should be loaded according to the AES mode:<br>in AES CTR/GCTR - the AES CTR register should be loaded with the counter value.<br>in XTS-AES - the AES CTR register should be loaded with the 'i' value (in order to calculate the T value from it, if HW T 6693calculation is supported).<br><table border="1" bgcolor="#EEEEEE" width="800"> 6694 <tr> 6695 <td colspan="32" align="center">AES_CTR_0_0</td> 6696 </tr> 6697 <tr></tr> 6698</table> 6699<table border="1" width="800"> 6700 <tr> 6701 <td width="40"><b>bits</b></td> 6702 <td width="100"><b>Field name</b></td> 6703 <td width="20"><b>permission</b></td> 6704 <td width="40"><b>default</b></td> 6705 <td width="600"><b>Description</b></td> 6706 </tr> 6707 <tr> 6708 <td valign="top" align="center"><a name="1.4.25.1"></a>31:0 6709 </td> 6710 <td valign="top">AES_CTR_0_0</td> 6711 <td valign="top" align="center">r/wc</td> 6712 <td valign="top" align="center">0x0</td> 6713 <td valign="top">bits 31:0 of AES_CTR0 register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description 6714 </td> 6715 </tr> 6716</table><a name="1.4.26"></a><br>1.4.26 : <b>Reg : AES_CTR_0_1</b> : 0x000000464<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 63:32 of AES_CTR0 128b register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6717 <tr> 6718 <td colspan="32" align="center">AES_CTR_0_1</td> 6719 </tr> 6720 <tr></tr> 6721</table> 6722<table border="1" width="800"> 6723 <tr> 6724 <td width="40"><b>bits</b></td> 6725 <td width="100"><b>Field name</b></td> 6726 <td width="20"><b>permission</b></td> 6727 <td width="40"><b>default</b></td> 6728 <td width="600"><b>Description</b></td> 6729 </tr> 6730 <tr> 6731 <td valign="top" align="center"><a name="1.4.26.1"></a>31:0 6732 </td> 6733 <td valign="top">AES_CTR_0_1</td> 6734 <td valign="top" align="center">r/wc</td> 6735 <td valign="top" align="center">0x0</td> 6736 <td valign="top">bits 63:32 of AES_CTR0 register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description 6737 </td> 6738 </tr> 6739</table><a name="1.4.27"></a><br>1.4.27 : <b>Reg : AES_CTR_0_2</b> : 0x000000468<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 95:64 of AES_CTR0 128b register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6740 <tr> 6741 <td colspan="32" align="center">AES_CTR_0_2</td> 6742 </tr> 6743 <tr></tr> 6744</table> 6745<table border="1" width="800"> 6746 <tr> 6747 <td width="40"><b>bits</b></td> 6748 <td width="100"><b>Field name</b></td> 6749 <td width="20"><b>permission</b></td> 6750 <td width="40"><b>default</b></td> 6751 <td width="600"><b>Description</b></td> 6752 </tr> 6753 <tr> 6754 <td valign="top" align="center"><a name="1.4.27.1"></a>31:0 6755 </td> 6756 <td valign="top">AES_CTR_0_2</td> 6757 <td valign="top" align="center">r/wc</td> 6758 <td valign="top" align="center">0x0</td> 6759 <td valign="top">bits 95:64 of AES_CTR0 register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description 6760 </td> 6761 </tr> 6762</table><a name="1.4.28"></a><br>1.4.28 : <b>Reg : AES_CTR_0_3</b> : 0x00000046C<br><b>reg sep address</b> : <b> reg host address</b> : <br>bits 127:96 of AES_CTR0 128b register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6763 <tr> 6764 <td colspan="32" align="center">AES_CTR_0_3</td> 6765 </tr> 6766 <tr></tr> 6767</table> 6768<table border="1" width="800"> 6769 <tr> 6770 <td width="40"><b>bits</b></td> 6771 <td width="100"><b>Field name</b></td> 6772 <td width="20"><b>permission</b></td> 6773 <td width="40"><b>default</b></td> 6774 <td width="600"><b>Description</b></td> 6775 </tr> 6776 <tr> 6777 <td valign="top" align="center"><a name="1.4.28.1"></a>31:0 6778 </td> 6779 <td valign="top">AES_CTR_0_3</td> 6780 <td valign="top" align="center">r/wc</td> 6781 <td valign="top" align="center">0x0</td> 6782 <td valign="top">bits 127:96 of AES_CTR0 register. <br>For the description of AES_CTR0, see the AES_CTR_0_0 register description 6783 </td> 6784 </tr> 6785</table><a name="1.4.29"></a><br>1.4.29 : <b>Reg : AES_BUSY</b> : 0x000000470<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is set when the AES core is active<br><table border="1" bgcolor="#EEEEEE" width="800"> 6786 <tr> 6787 <td colspan="32" align="center">AES_BUSY</td> 6788 </tr> 6789 <tr></tr> 6790</table> 6791<table border="1" width="800"> 6792 <tr> 6793 <td width="40"><b>bits</b></td> 6794 <td width="100"><b>Field name</b></td> 6795 <td width="20"><b>permission</b></td> 6796 <td width="40"><b>default</b></td> 6797 <td width="600"><b>Description</b></td> 6798 </tr> 6799 <tr> 6800 <td valign="top" align="center"><a name="1.4.29.1"></a>0:0 6801 </td> 6802 <td valign="top">AES_BUSY</td> 6803 <td valign="top" align="center">ro</td> 6804 <td valign="top" align="center">0x0</td> 6805 <td valign="top">AES_BUSY Register. this register is set when the AES core is active</td> 6806 </tr> 6807 <tr> 6808 <td valign="top" align="center"><a name="1.4.29.2"></a>31:1 6809 </td> 6810 <td valign="top">RESERVED</td> 6811 <td valign="top" align="center">ro</td> 6812 <td valign="top" align="center">0x0</td> 6813 <td valign="top">31'b0</td> 6814 </tr> 6815</table><a name="1.4.30"></a><br>1.4.30 : <b>Reg : AES_SK</b> : 0x000000478<br><b>reg sep address</b> : <b> reg host address</b> : <br>writing to this address causes sampling of the HW key to the AES_KEY0 register<br><table border="1" bgcolor="#EEEEEE" width="800"> 6816 <tr> 6817 <td colspan="32" align="center">AES_SK</td> 6818 </tr> 6819 <tr></tr> 6820</table> 6821<table border="1" width="800"> 6822 <tr> 6823 <td width="40"><b>bits</b></td> 6824 <td width="100"><b>Field name</b></td> 6825 <td width="20"><b>permission</b></td> 6826 <td width="40"><b>default</b></td> 6827 <td width="600"><b>Description</b></td> 6828 </tr> 6829 <tr> 6830 <td valign="top" align="center"><a name="1.4.30.1"></a>0:0 6831 </td> 6832 <td valign="top">AES_SK</td> 6833 <td valign="top" align="center">wm</td> 6834 <td valign="top" align="center">0x0</td> 6835 <td valign="top">writing to this address causes sampling of the HW key to the AES_KEY0 register</td> 6836 </tr> 6837 <tr> 6838 <td valign="top" align="center"><a name="1.4.30.2"></a>31:1 6839 </td> 6840 <td valign="top">RESERVED</td> 6841 <td valign="top" align="center">wm</td> 6842 <td valign="top" align="center">0x0</td> 6843 <td valign="top">Reserved</td> 6844 </tr> 6845</table><a name="1.4.31"></a><br>1.4.31 : <b>Reg : AES_CMAC_INIT</b> : 0x00000047C<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this address triggers the AES engine generating of K1 and K2 for AES CMAC operations.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6846 <tr> 6847 <td colspan="32" align="center">AES_CMAC_INIT</td> 6848 </tr> 6849 <tr></tr> 6850</table> 6851<table border="1" width="800"> 6852 <tr> 6853 <td width="40"><b>bits</b></td> 6854 <td width="100"><b>Field name</b></td> 6855 <td width="20"><b>permission</b></td> 6856 <td width="40"><b>default</b></td> 6857 <td width="600"><b>Description</b></td> 6858 </tr> 6859 <tr> 6860 <td valign="top" align="center"><a name="1.4.31.1"></a>0:0 6861 </td> 6862 <td valign="top">AES_CMAC_INIT</td> 6863 <td valign="top" align="center">wo</td> 6864 <td valign="top" align="center">0x0</td> 6865 <td valign="top">Writing to this address starts the generating of K1 and K2 for AES CMAC operations</td> 6866 </tr> 6867 <tr> 6868 <td valign="top" align="center"><a name="1.4.31.2"></a>31:1 6869 </td> 6870 <td valign="top">RESERVED</td> 6871 <td valign="top" align="center">wo</td> 6872 <td valign="top" align="center">0x0</td> 6873 <td valign="top">Reserved</td> 6874 </tr> 6875</table><a name="1.4.32"></a><br>1.4.32 : <b>Reg : AES_SK1</b> : 0x0000004B4<br><b>reg sep address</b> : <b> reg host address</b> : <br>writing to this address causes sampling of the HW key to the AES_KEY1 register<br><table border="1" bgcolor="#EEEEEE" width="800"> 6876 <tr> 6877 <td colspan="32" align="center">AES_SK1</td> 6878 </tr> 6879 <tr></tr> 6880</table> 6881<table border="1" width="800"> 6882 <tr> 6883 <td width="40"><b>bits</b></td> 6884 <td width="100"><b>Field name</b></td> 6885 <td width="20"><b>permission</b></td> 6886 <td width="40"><b>default</b></td> 6887 <td width="600"><b>Description</b></td> 6888 </tr> 6889 <tr> 6890 <td valign="top" align="center"><a name="1.4.32.1"></a>0:0 6891 </td> 6892 <td valign="top">AES_SK1</td> 6893 <td valign="top" align="center">wm</td> 6894 <td valign="top" align="center">0x0</td> 6895 <td valign="top">writing to this address causes sampling of the HW key to the AES_KEY1 register</td> 6896 </tr> 6897 <tr> 6898 <td valign="top" align="center"><a name="1.4.32.2"></a>31:1 6899 </td> 6900 <td valign="top">RESERVED</td> 6901 <td valign="top" align="center">wm</td> 6902 <td valign="top" align="center">0x0</td> 6903 <td valign="top">Reserved</td> 6904 </tr> 6905</table><a name="1.4.33"></a><br>1.4.33 : <b>Reg : AES_REMAINING_BYTES</b> : 0x0000004BC<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register should be set with the amount of remaining bytes until the end of the current AES operation. The AES engine 6906counts down from this value to determine the last / one before last blocks in AES CMAC, XTS AES and AES CCM.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6907 <tr> 6908 <td colspan="32" align="center">AES_REMAINING_BYTES</td> 6909 </tr> 6910 <tr></tr> 6911</table> 6912<table border="1" width="800"> 6913 <tr> 6914 <td width="40"><b>bits</b></td> 6915 <td width="100"><b>Field name</b></td> 6916 <td width="20"><b>permission</b></td> 6917 <td width="40"><b>default</b></td> 6918 <td width="600"><b>Description</b></td> 6919 </tr> 6920 <tr> 6921 <td valign="top" align="center"><a name="1.4.33.1"></a>31:0 6922 </td> 6923 <td valign="top">AES_REMAINING_BYTES</td> 6924 <td valign="top" align="center">r/wc</td> 6925 <td valign="top" align="center">0x0</td> 6926 <td valign="top">This register should be set with the amount of remaining bytes until the end of the current AES operation. The AES engine 6927 counts down from this value to determine the last / one before last blocks in AES CMAC, XTS AES and AES CCM. 6928 </td> 6929 </tr> 6930</table><a name="1.4.34"></a><br>1.4.34 : <b>Reg : AES_CONTROL</b> : 0x0000004C0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the configuration of the AES engine<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 6931 <tr> 6932 <td colspan="32" align="center">AES_CONTROL</td> 6933 </tr> 6934 <tr></tr> 6935</table> 6936<table border="1" width="800"> 6937 <tr> 6938 <td width="40"><b>bits</b></td> 6939 <td width="100"><b>Field name</b></td> 6940 <td width="20"><b>permission</b></td> 6941 <td width="40"><b>default</b></td> 6942 <td width="600"><b>Description</b></td> 6943 </tr> 6944 <tr> 6945 <td valign="top" align="center"><a name="1.4.34.1"></a>0:0 6946 </td> 6947 <td valign="top">DEC_KEY0</td> 6948 <td valign="top" align="center">rw</td> 6949 <td valign="top" align="center">0x0</td> 6950 <td valign="top">This field determines whether the AES performs Decrypt/Encrypt operations, in non-tunneling operations:<br>@0 - Encrypt<br>@1 - Decrypt 6951 </td> 6952 </tr> 6953 <tr> 6954 <td valign="top" align="center"><a name="1.4.34.2"></a>1:1 6955 </td> 6956 <td valign="top">MODE0_IS_CBC_CTS</td> 6957 <td valign="top" align="center">rw</td> 6958 <td valign="top" align="center">0x0</td> 6959 <td valign="top">If MODE_KEY0 is set to 3'b001 (CBC), and this field is set - the mode is CBC-CTS. In addition, If MODE_KEY0 is set to 3'b010 6960 (CTR), and this field is set - the mode is GCTR. 6961 </td> 6962 </tr> 6963 <tr> 6964 <td valign="top" align="center"><a name="1.4.34.3"></a>4:2 6965 </td> 6966 <td valign="top">MODE_KEY0</td> 6967 <td valign="top" align="center">rw</td> 6968 <td valign="top" align="center">0x0</td> 6969 <td valign="top">This field determines the AES mode in non tunneling operations, and the AES mode of the first stage in tunneling operations:<br>@000 - ECB<br>@001 - CBC<br>@010 - CTR <br>@011 - CBC MAC<br>@100 - XEX/XTS<br>@101 - XCBC-MAC <br>@110 -OFB<br>@111 - CMAC 6970 </td> 6971 </tr> 6972 <tr> 6973 <td valign="top" align="center"><a name="1.4.34.4"></a>7:5 6974 </td> 6975 <td valign="top">MODE_KEY1</td> 6976 <td valign="top" align="center">rw</td> 6977 <td valign="top" align="center">0x0</td> 6978 <td valign="top">This field determines the AES mode of the second stage operation in tunneling operations:<br>@000 - ECB<br>@001 - CBC<br>@010 - CTR <br>@011 - CBC MAC<br>@100 - XEX/XTS<br>@101 - XCBC-MAC <br>@110 -OFB<br>@111 - CMAC 6979 </td> 6980 </tr> 6981 <tr> 6982 <td valign="top" align="center"><a name="1.4.34.5"></a>8:8 6983 </td> 6984 <td valign="top">CBC_IS_ESSIV</td> 6985 <td valign="top" align="center">rw</td> 6986 <td valign="top" align="center">0x0</td> 6987 <td valign="top">If MODE_KEY0 is set to 3'b001 (CBC), and this field is set - the mode is CBC-with ESSIV.</td> 6988 </tr> 6989 <tr> 6990 <td valign="top" align="center"><a name="1.4.34.6"></a>9:9 6991 </td> 6992 <td valign="top">RESERVED0</td> 6993 <td valign="top" align="center">rw</td> 6994 <td valign="top" align="center">0x0</td> 6995 <td valign="top">Reserved</td> 6996 </tr> 6997 <tr> 6998 <td valign="top" align="center"><a name="1.4.34.7"></a>10:10 6999 </td> 7000 <td valign="top">AES_TUNNEL_IS_ON</td> 7001 <td valign="top" align="center">rw</td> 7002 <td valign="top" align="center">0x0</td> 7003 <td valign="top">This field determines whether the AES performs dual-tunnel operations or standard non-tunneling operations:<br>@0 - standard non-tunneling operations<br>@1 - tunneling operations. 7004 </td> 7005 </tr> 7006 <tr> 7007 <td valign="top" align="center"><a name="1.4.34.8"></a>11:11 7008 </td> 7009 <td valign="top">CBC_IS_BITLOCKER</td> 7010 <td valign="top" align="center">rw</td> 7011 <td valign="top" align="center">0x0</td> 7012 <td valign="top">If MODE_KEY0 is set to 3'b001 (CBC), and this field is set - the mode isBITLOCKER.</td> 7013 </tr> 7014 <tr> 7015 <td valign="top" align="center"><a name="1.4.34.9"></a>13:12 7016 </td> 7017 <td valign="top">NK_KEY0</td> 7018 <td valign="top" align="center">rw</td> 7019 <td valign="top" align="center">0x0</td> 7020 <td valign="top">This field determines the AES Key length in non tunneling operations, and the AES key length of the first stage in tunneling 7021 operations:<br>@00 - 128 bits key<br>@01 - 192 bits key <br>@10 - 256 bits key <br>@11 - N/A 7022 </td> 7023 </tr> 7024 <tr> 7025 <td valign="top" align="center"><a name="1.4.34.10"></a>15:14 7026 </td> 7027 <td valign="top">NK_KEY1</td> 7028 <td valign="top" align="center">rw</td> 7029 <td valign="top" align="center">0x0</td> 7030 <td valign="top">This field determines the AES key length of the second stage operation in tunneling operations:<br>@00 - 128 bits key <br>@01 - 192 bits key <br>@10 - 256 bits key <br>@11 - N/A 7031 </td> 7032 </tr> 7033 <tr> 7034 <td valign="top" align="center"><a name="1.4.34.11"></a>21:16 7035 </td> 7036 <td valign="top">RESERVED2</td> 7037 <td valign="top" align="center">rw</td> 7038 <td valign="top" align="center">0x0</td> 7039 <td valign="top">Reserved</td> 7040 </tr> 7041 <tr> 7042 <td valign="top" align="center"><a name="1.4.34.12"></a>22:22 7043 </td> 7044 <td valign="top">AES_TUNNEL1_DECRYPT</td> 7045 <td valign="top" align="center">rw</td> 7046 <td valign="top" align="center">0x0</td> 7047 <td valign="top">This field determines whether the second tunnel stage performs encrypt or decrypt operation :<br>@0 - the second tunnel stage performs encrypt operations. <br>@1 - the second tunnel stage performs decrypt operations. 7048 </td> 7049 </tr> 7050 <tr> 7051 <td valign="top" align="center"><a name="1.4.34.13"></a>23:23 7052 </td> 7053 <td valign="top">AES_TUN_B1_USES_PADDED_DATA_IN</td> 7054 <td valign="top" align="center">rw</td> 7055 <td valign="top" align="center">0x0</td> 7056 <td valign="top">This field determines, for tunneling operations, the data that is fed to the second tunneling stage:<br>@0 - the output of the first block (standard tunneling operation).<br>@1- data_in after padding rather than the output of the first block. 7057 </td> 7058 </tr> 7059 <tr> 7060 <td valign="top" align="center"><a name="1.4.34.14"></a>24:24 7061 </td> 7062 <td valign="top">AES_TUNNEL0_ENCRYPT</td> 7063 <td valign="top" align="center">rw</td> 7064 <td valign="top" align="center">0x0</td> 7065 <td valign="top">This field determines whether the first tunnel stage performs encrypt or decrypt operation :<br>@0 - the first tunnel stage performs decrypt operations.<br>@1 - the first tunnel stage performs encrypt operations. 7066 </td> 7067 </tr> 7068 <tr> 7069 <td valign="top" align="center"><a name="1.4.34.15"></a>25:25 7070 </td> 7071 <td valign="top">AES_OUTPUT_MID_TUNNEL_DATA</td> 7072 <td valign="top" align="center">rw</td> 7073 <td valign="top" align="center">0x0</td> 7074 <td valign="top">This fields determines whether the AES output is the result of the first or second tunneling stage:<br>@0 - The AES engine outputs the result of the second tunnel stage (standard tunneling).<br>@1 - The AES engine outputs the result of the first tunnel stage. 7075 </td> 7076 </tr> 7077 <tr> 7078 <td valign="top" align="center"><a name="1.4.34.16"></a>26:26 7079 </td> 7080 <td valign="top">AES_TUNNEL_B1_PAD_EN</td> 7081 <td valign="top" align="center">rw</td> 7082 <td valign="top" align="center">0x0</td> 7083 <td valign="top">This field determines whether the input data to the second tunnel stage is padded with zeroes (according to the remaining_bytes 7084 value) or not:<br>@0 - The data input to the second tunnel block is not padded with zeros.<br>@1 - The data input to the second tunnel block is padded with zeros. 7085 </td> 7086 </tr> 7087 <tr> 7088 <td valign="top" align="center"><a name="1.4.34.17"></a>27:27 7089 </td> 7090 <td valign="top">RESERVED3</td> 7091 <td valign="top" align="center">rw</td> 7092 <td valign="top" align="center">0x0</td> 7093 <td valign="top">Reserved</td> 7094 </tr> 7095 <tr> 7096 <td valign="top" align="center"><a name="1.4.34.18"></a>28:28 7097 </td> 7098 <td valign="top">AES_OUT_MID_TUN_TO_HASH</td> 7099 <td valign="top" align="center">rw</td> 7100 <td valign="top" align="center">0x0</td> 7101 <td valign="top">This field determines for AES-TO-HASH-AND-DOUT tunneling operations, whether the AES outputs to the HASH the result of the 7102 first or the second tunneling stage:<br>@0 - The AES engine writes to the hash the result of the second tunnel stage.<br>@1 - The AES engine writes to the hash the result of the first tunnel stage. 7103 </td> 7104 </tr> 7105 <tr> 7106 <td valign="top" align="center"><a name="1.4.34.19"></a>29:29 7107 </td> 7108 <td valign="top">AES_XOR_CRYPTOKEY</td> 7109 <td valign="top" align="center">rw</td> 7110 <td valign="top" align="center">0x0</td> 7111 <td valign="top">This field determines the value that is written to AES_KEY0, when AES_SK is kicked:<br>@0 - The value that is written to AES_KEY0 is the value of the HW cryptokey, as is.<br>@1 - The value that is written to AES_KEY0 is the value of the HW cryptokey xored with the current value of AES_KEY0. 7112 </td> 7113 </tr> 7114 <tr> 7115 <td valign="top" align="center"><a name="1.4.34.20"></a>30:30 7116 </td> 7117 <td valign="top">RESERVED4</td> 7118 <td valign="top" align="center">rw</td> 7119 <td valign="top" align="center">0x0</td> 7120 <td valign="top">Reserved</td> 7121 </tr> 7122 <tr> 7123 <td valign="top" align="center"><a name="1.4.34.21"></a>31:31 7124 </td> 7125 <td valign="top">DIRECT_ACCESS</td> 7126 <td valign="top" align="center">rw</td> 7127 <td valign="top" align="center">0x0</td> 7128 <td valign="top">Using direct access and not the din-dout interface</td> 7129 </tr> 7130</table><a name="1.4.35"></a><br>1.4.35 : <b>Reg : AES_HW_FLAGS</b> : 0x0000004C8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the pre-synthesis HW flag configuration of the AES engine<br><table border="1" bgcolor="#EEEEEE" width="800"> 7131 <tr> 7132 <td colspan="32" align="center">AES_HW_FLAGS</td> 7133 </tr> 7134 <tr></tr> 7135</table> 7136<table border="1" width="800"> 7137 <tr> 7138 <td width="40"><b>bits</b></td> 7139 <td width="100"><b>Field name</b></td> 7140 <td width="20"><b>permission</b></td> 7141 <td width="40"><b>default</b></td> 7142 <td width="600"><b>Description</b></td> 7143 </tr> 7144 <tr> 7145 <td valign="top" align="center"><a name="1.4.35.1"></a>0:0 7146 </td> 7147 <td valign="top">SUPPORT_256_192_KEY</td> 7148 <td valign="top" align="center">ro</td> 7149 <td valign="top" align="center">0x1</td> 7150 <td valign="top">the SUPPORT_256_192_KEY flag</td> 7151 </tr> 7152 <tr> 7153 <td valign="top" align="center"><a name="1.4.35.2"></a>1:1 7154 </td> 7155 <td valign="top">AES_LARGE_RKEK</td> 7156 <td valign="top" align="center">ro</td> 7157 <td valign="top" align="center">0x1</td> 7158 <td valign="top">the AES_LARGE_RKEK flag</td> 7159 </tr> 7160 <tr> 7161 <td valign="top" align="center"><a name="1.4.35.3"></a>2:2 7162 </td> 7163 <td valign="top">DPA_CNTRMSR_EXIST</td> 7164 <td valign="top" align="center">ro</td> 7165 <td valign="top" align="center">0x0</td> 7166 <td valign="top">the DPA_CNTRMSR_EXIST flag</td> 7167 </tr> 7168 <tr> 7169 <td valign="top" align="center"><a name="1.4.35.4"></a>3:3 7170 </td> 7171 <td valign="top">CTR_EXIST</td> 7172 <td valign="top" align="center">ro</td> 7173 <td valign="top" align="center">0x1</td> 7174 <td valign="top">the CTR_EXIST flag</td> 7175 </tr> 7176 <tr> 7177 <td valign="top" align="center"><a name="1.4.35.5"></a>4:4 7178 </td> 7179 <td valign="top">ONLY_ENCRYPT</td> 7180 <td valign="top" align="center">ro</td> 7181 <td valign="top" align="center">0x0</td> 7182 <td valign="top">the ONLY_ENCRYPT flag</td> 7183 </tr> 7184 <tr> 7185 <td valign="top" align="center"><a name="1.4.35.6"></a>5:5 7186 </td> 7187 <td valign="top">USE_SBOX_TABLE</td> 7188 <td valign="top" align="center">ro</td> 7189 <td valign="top" align="center">0x0</td> 7190 <td valign="top">the USE_SBOX_TABLE flag</td> 7191 </tr> 7192 <tr> 7193 <td valign="top" align="center"><a name="1.4.35.7"></a>7:6 7194 </td> 7195 <td valign="top">RESERVED0</td> 7196 <td valign="top" align="center">ro</td> 7197 <td valign="top" align="center">0x0</td> 7198 <td valign="top">Reserved</td> 7199 </tr> 7200 <tr> 7201 <td valign="top" align="center"><a name="1.4.35.8"></a>8:8 7202 </td> 7203 <td valign="top">USE_5_SBOXES</td> 7204 <td valign="top" align="center">ro</td> 7205 <td valign="top" align="center">0x1</td> 7206 <td valign="top">the USE_5_SBOXES flag</td> 7207 </tr> 7208 <tr> 7209 <td valign="top" align="center"><a name="1.4.35.9"></a>9:9 7210 </td> 7211 <td valign="top">AES_SUPPORT_PREV_IV</td> 7212 <td valign="top" align="center">ro</td> 7213 <td valign="top" align="center">0x0</td> 7214 <td valign="top">the AES_SUPPORT_PREV_IV flag</td> 7215 </tr> 7216 <tr> 7217 <td valign="top" align="center"><a name="1.4.35.10"></a>10:10 7218 </td> 7219 <td valign="top">aes_tunnel_exists</td> 7220 <td valign="top" align="center">ro</td> 7221 <td valign="top" align="center">0x1</td> 7222 <td valign="top">the aes_tunnel_exists flag</td> 7223 </tr> 7224 <tr> 7225 <td valign="top" align="center"><a name="1.4.35.11"></a>11:11 7226 </td> 7227 <td valign="top">SECOND_REGS_SET_EXIST</td> 7228 <td valign="top" align="center">ro</td> 7229 <td valign="top" align="center">0x1</td> 7230 <td valign="top">the SECOND_REGS_SET_EXIST flag</td> 7231 </tr> 7232 <tr> 7233 <td valign="top" align="center"><a name="1.4.35.12"></a>12:12 7234 </td> 7235 <td valign="top">DFA_CNTRMSR_EXIST</td> 7236 <td valign="top" align="center">ro</td> 7237 <td valign="top" align="center">0x1</td> 7238 <td valign="top">the DFA_CNTRMSR_EXIST flag</td> 7239 </tr> 7240 <tr> 7241 <td valign="top" align="center"><a name="1.4.35.13"></a>31:13 7242 </td> 7243 <td valign="top">RESERVED1</td> 7244 <td valign="top" align="center">ro</td> 7245 <td valign="top" align="center">0x0</td> 7246 <td valign="top">Reserved</td> 7247 </tr> 7248</table><a name="1.4.36"></a><br>1.4.36 : <b>Reg : AES_CTR_NO_INCREMENT</b> : 0x0000004D8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register enables the AES CTR no increment mode (in which the counter mode is not incremented between 2 blocks)<br><table border="1" bgcolor="#EEEEEE" width="800"> 7249 <tr> 7250 <td colspan="32" align="center">AES_CTR_NO_INCREMENT</td> 7251 </tr> 7252 <tr></tr> 7253</table> 7254<table border="1" width="800"> 7255 <tr> 7256 <td width="40"><b>bits</b></td> 7257 <td width="100"><b>Field name</b></td> 7258 <td width="20"><b>permission</b></td> 7259 <td width="40"><b>default</b></td> 7260 <td width="600"><b>Description</b></td> 7261 </tr> 7262 <tr> 7263 <td valign="top" align="center"><a name="1.4.36.1"></a>0:0 7264 </td> 7265 <td valign="top">AES_CTR_NO_INCREMENT</td> 7266 <td valign="top" align="center">rw</td> 7267 <td valign="top" align="center">0x0</td> 7268 <td valign="top">This field enables the AES CTR "no increment" mode (in which the counter mode is not incremented between 2 blocks)</td> 7269 </tr> 7270 <tr> 7271 <td valign="top" align="center"><a name="1.4.36.2"></a>31:1 7272 </td> 7273 <td valign="top">RESERVED</td> 7274 <td valign="top" align="center">rw</td> 7275 <td valign="top" align="center">0x0</td> 7276 <td valign="top">Reserved</td> 7277 </tr> 7278</table><a name="1.4.37"></a><br>1.4.37 : <b>Reg : AES_DFA_IS_ON</b> : 0x0000004F0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register disable/enable the AES dfa.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7279 <tr> 7280 <td colspan="32" align="center">AES_DFA_IS_ON</td> 7281 </tr> 7282 <tr></tr> 7283</table> 7284<table border="1" width="800"> 7285 <tr> 7286 <td width="40"><b>bits</b></td> 7287 <td width="100"><b>Field name</b></td> 7288 <td width="20"><b>permission</b></td> 7289 <td width="40"><b>default</b></td> 7290 <td width="600"><b>Description</b></td> 7291 </tr> 7292 <tr> 7293 <td valign="top" align="center"><a name="1.4.37.1"></a>0:0 7294 </td> 7295 <td valign="top">AES_DFA_IS_ON</td> 7296 <td valign="top" align="center">r/wc</td> 7297 <td valign="top" align="center">0x0</td> 7298 <td valign="top">writing to this register turns the DFA counter-measures on. this register exists only if DFA countermeasures are supported</td> 7299 </tr> 7300 <tr> 7301 <td valign="top" align="center"><a name="1.4.37.2"></a>31:1 7302 </td> 7303 <td valign="top">RESERVED</td> 7304 <td valign="top" align="center">r/wc</td> 7305 <td valign="top" align="center">0x0</td> 7306 <td valign="top">Reserved</td> 7307 </tr> 7308</table><a name="1.4.38"></a><br>1.4.38 : <b>Reg : AES_DFA_ERR_STATUS</b> : 0x0000004F8<br><b>reg sep address</b> : <b> reg host address</b> : <br>dfa error status register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7309 <tr> 7310 <td colspan="32" align="center">AES_DFA_ERR_STATUS</td> 7311 </tr> 7312 <tr></tr> 7313</table> 7314<table border="1" width="800"> 7315 <tr> 7316 <td width="40"><b>bits</b></td> 7317 <td width="100"><b>Field name</b></td> 7318 <td width="20"><b>permission</b></td> 7319 <td width="40"><b>default</b></td> 7320 <td width="600"><b>Description</b></td> 7321 </tr> 7322 <tr> 7323 <td valign="top" align="center"><a name="1.4.38.1"></a>0:0 7324 </td> 7325 <td valign="top">AES_DFA_ERR_STATUS</td> 7326 <td valign="top" align="center">ro</td> 7327 <td valign="top" align="center">0x0</td> 7328 <td valign="top">after a DFA violation this register is set and the AES block is disabled) until the next reset. this register only exists 7329 if DFA countermeasures is are supported 7330 </td> 7331 </tr> 7332 <tr> 7333 <td valign="top" align="center"><a name="1.4.38.2"></a>31:1 7334 </td> 7335 <td valign="top">RESERVED</td> 7336 <td valign="top" align="center">ro</td> 7337 <td valign="top" align="center">0x0</td> 7338 <td valign="top">Reserved</td> 7339 </tr> 7340</table><a name="1.4.39"></a><br>1.4.39 : <b>Reg : AES_CMAC_SIZE0_KICK</b> : 0x000000524<br><b>reg sep address</b> : <b> reg host address</b> : <br>writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from 7341the AES_IV0 register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7342 <tr> 7343 <td colspan="32" align="center">AES_CMAC_SIZE0_KICK</td> 7344 </tr> 7345 <tr></tr> 7346</table> 7347<table border="1" width="800"> 7348 <tr> 7349 <td width="40"><b>bits</b></td> 7350 <td width="100"><b>Field name</b></td> 7351 <td width="20"><b>permission</b></td> 7352 <td width="40"><b>default</b></td> 7353 <td width="600"><b>Description</b></td> 7354 </tr> 7355 <tr> 7356 <td valign="top" align="center"><a name="1.4.39.1"></a>0:0 7357 </td> 7358 <td valign="top">AES_CMAC_SIZE0_KICK</td> 7359 <td valign="top" align="center">wm</td> 7360 <td valign="top" align="center">0x0</td> 7361 <td valign="top">writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from 7362 the AES_IV0 register. 7363 </td> 7364 </tr> 7365 <tr> 7366 <td valign="top" align="center"><a name="1.4.39.2"></a>31:1 7367 </td> 7368 <td valign="top">RESERVED</td> 7369 <td valign="top" align="center">wm</td> 7370 <td valign="top" align="center">0x0</td> 7371 <td valign="top">Reserved</td> 7372 </tr> 7373</table><a href="#1.4">(top of block)</a><a name="1.5"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 7374 <td><b><font color="#000000">1.5 : Block: HASH</font></b></td> 7375 <td align="right"><font color="#000000">0x000000640</font></td> 7376</table><br><a name="1.5.1"></a><br>1.5.1 : <b>Reg : HASH_H0</b> : 0x000000640<br><b>reg sep address</b> : <b> reg host address</b> : <br>H0 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7377 <tr> 7378 <td colspan="32" align="center">HASH_H0</td> 7379 </tr> 7380 <tr></tr> 7381</table> 7382<table border="1" width="800"> 7383 <tr> 7384 <td width="40"><b>bits</b></td> 7385 <td width="100"><b>Field name</b></td> 7386 <td width="20"><b>permission</b></td> 7387 <td width="40"><b>default</b></td> 7388 <td width="600"><b>Description</b></td> 7389 </tr> 7390 <tr> 7391 <td valign="top" align="center"><a name="1.5.1.1"></a>31:0 7392 </td> 7393 <td valign="top">HASH_H0</td> 7394 <td valign="top" align="center">r/wc</td> 7395 <td valign="top" align="center">0x0</td> 7396 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7397 </td> 7398 </tr> 7399</table><a name="1.5.2"></a><br>1.5.2 : <b>Reg : HASH_H1</b> : 0x000000644<br><b>reg sep address</b> : <b> reg host address</b> : <br>H1 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7400 <tr> 7401 <td colspan="32" align="center">HASH_H1</td> 7402 </tr> 7403 <tr></tr> 7404</table> 7405<table border="1" width="800"> 7406 <tr> 7407 <td width="40"><b>bits</b></td> 7408 <td width="100"><b>Field name</b></td> 7409 <td width="20"><b>permission</b></td> 7410 <td width="40"><b>default</b></td> 7411 <td width="600"><b>Description</b></td> 7412 </tr> 7413 <tr> 7414 <td valign="top" align="center"><a name="1.5.2.1"></a>31:0 7415 </td> 7416 <td valign="top">HASH_H1</td> 7417 <td valign="top" align="center">r/wc</td> 7418 <td valign="top" align="center">0x0</td> 7419 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7420 </td> 7421 </tr> 7422</table><a name="1.5.3"></a><br>1.5.3 : <b>Reg : HASH_H2</b> : 0x000000648<br><b>reg sep address</b> : <b> reg host address</b> : <br>H2 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7423 <tr> 7424 <td colspan="32" align="center">HASH_H2</td> 7425 </tr> 7426 <tr></tr> 7427</table> 7428<table border="1" width="800"> 7429 <tr> 7430 <td width="40"><b>bits</b></td> 7431 <td width="100"><b>Field name</b></td> 7432 <td width="20"><b>permission</b></td> 7433 <td width="40"><b>default</b></td> 7434 <td width="600"><b>Description</b></td> 7435 </tr> 7436 <tr> 7437 <td valign="top" align="center"><a name="1.5.3.1"></a>31:0 7438 </td> 7439 <td valign="top">HASH_H2</td> 7440 <td valign="top" align="center">r/wc</td> 7441 <td valign="top" align="center">0x0</td> 7442 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7443 </td> 7444 </tr> 7445</table><a name="1.5.4"></a><br>1.5.4 : <b>Reg : HASH_H3</b> : 0x00000064C<br><b>reg sep address</b> : <b> reg host address</b> : <br>H3 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7446 <tr> 7447 <td colspan="32" align="center">HASH_H3</td> 7448 </tr> 7449 <tr></tr> 7450</table> 7451<table border="1" width="800"> 7452 <tr> 7453 <td width="40"><b>bits</b></td> 7454 <td width="100"><b>Field name</b></td> 7455 <td width="20"><b>permission</b></td> 7456 <td width="40"><b>default</b></td> 7457 <td width="600"><b>Description</b></td> 7458 </tr> 7459 <tr> 7460 <td valign="top" align="center"><a name="1.5.4.1"></a>31:0 7461 </td> 7462 <td valign="top">HASH_H3</td> 7463 <td valign="top" align="center">r/wc</td> 7464 <td valign="top" align="center">0x0</td> 7465 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7466 </td> 7467 </tr> 7468</table><a name="1.5.5"></a><br>1.5.5 : <b>Reg : HASH_H4</b> : 0x000000650<br><b>reg sep address</b> : <b> reg host address</b> : <br>H4 data. can only be written in the following HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7469 <tr> 7470 <td colspan="32" align="center">HASH_H4</td> 7471 </tr> 7472 <tr></tr> 7473</table> 7474<table border="1" width="800"> 7475 <tr> 7476 <td width="40"><b>bits</b></td> 7477 <td width="100"><b>Field name</b></td> 7478 <td width="20"><b>permission</b></td> 7479 <td width="40"><b>default</b></td> 7480 <td width="600"><b>Description</b></td> 7481 </tr> 7482 <tr> 7483 <td valign="top" align="center"><a name="1.5.5.1"></a>31:0 7484 </td> 7485 <td valign="top">HASH_H4</td> 7486 <td valign="top" align="center">r/wc</td> 7487 <td valign="top" align="center">0x0</td> 7488 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7489 </td> 7490 </tr> 7491</table><a name="1.5.6"></a><br>1.5.6 : <b>Reg : HASH_H5</b> : 0x000000654<br><b>reg sep address</b> : <b> reg host address</b> : <br>H5 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7492 <tr> 7493 <td colspan="32" align="center">HASH_H5</td> 7494 </tr> 7495 <tr></tr> 7496</table> 7497<table border="1" width="800"> 7498 <tr> 7499 <td width="40"><b>bits</b></td> 7500 <td width="100"><b>Field name</b></td> 7501 <td width="20"><b>permission</b></td> 7502 <td width="40"><b>default</b></td> 7503 <td width="600"><b>Description</b></td> 7504 </tr> 7505 <tr> 7506 <td valign="top" align="center"><a name="1.5.6.1"></a>31:0 7507 </td> 7508 <td valign="top">HASH_H5</td> 7509 <td valign="top" align="center">r/wc</td> 7510 <td valign="top" align="center">0x0</td> 7511 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7512 </td> 7513 </tr> 7514</table><a name="1.5.7"></a><br>1.5.7 : <b>Reg : HASH_H6</b> : 0x000000658<br><b>reg sep address</b> : <b> reg host address</b> : <br>H6 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7515 <tr> 7516 <td colspan="32" align="center">HASH_H6</td> 7517 </tr> 7518 <tr></tr> 7519</table> 7520<table border="1" width="800"> 7521 <tr> 7522 <td width="40"><b>bits</b></td> 7523 <td width="100"><b>Field name</b></td> 7524 <td width="20"><b>permission</b></td> 7525 <td width="40"><b>default</b></td> 7526 <td width="600"><b>Description</b></td> 7527 </tr> 7528 <tr> 7529 <td valign="top" align="center"><a name="1.5.7.1"></a>31:0 7530 </td> 7531 <td valign="top">HASH_H6</td> 7532 <td valign="top" align="center">r/wc</td> 7533 <td valign="top" align="center">0x0</td> 7534 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7535 </td> 7536 </tr> 7537</table><a name="1.5.8"></a><br>1.5.8 : <b>Reg : HASH_H7</b> : 0x00000065C<br><b>reg sep address</b> : <b> reg host address</b> : <br>H7 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7538 <tr> 7539 <td colspan="32" align="center">HASH_H7</td> 7540 </tr> 7541 <tr></tr> 7542</table> 7543<table border="1" width="800"> 7544 <tr> 7545 <td width="40"><b>bits</b></td> 7546 <td width="100"><b>Field name</b></td> 7547 <td width="20"><b>permission</b></td> 7548 <td width="40"><b>default</b></td> 7549 <td width="600"><b>Description</b></td> 7550 </tr> 7551 <tr> 7552 <td valign="top" align="center"><a name="1.5.8.1"></a>31:0 7553 </td> 7554 <td valign="top">HASH_H7</td> 7555 <td valign="top" align="center">r/wc</td> 7556 <td valign="top" align="center">0x0</td> 7557 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7558 </td> 7559 </tr> 7560</table><a name="1.5.9"></a><br>1.5.9 : <b>Reg : HASH_H8</b> : 0x000000660<br><b>reg sep address</b> : <b> reg host address</b> : <br>H8 data. can only be written in the following HASH_CONTROL modes: SHA384 SHA512<br><table border="1" bgcolor="#EEEEEE" width="800"> 7561 <tr> 7562 <td colspan="32" align="center">HASH_H8</td> 7563 </tr> 7564 <tr></tr> 7565</table> 7566<table border="1" width="800"> 7567 <tr> 7568 <td width="40"><b>bits</b></td> 7569 <td width="100"><b>Field name</b></td> 7570 <td width="20"><b>permission</b></td> 7571 <td width="40"><b>default</b></td> 7572 <td width="600"><b>Description</b></td> 7573 </tr> 7574 <tr> 7575 <td valign="top" align="center"><a name="1.5.9.1"></a>31:0 7576 </td> 7577 <td valign="top">HASH_H8</td> 7578 <td valign="top" align="center">r/wc</td> 7579 <td valign="top" align="center">0x0</td> 7580 <td valign="top">1) Write initial Hash value. <br>2) Read final Hash value - result. 7581 </td> 7582 </tr> 7583</table><a name="1.5.10"></a><br>1.5.10 : <b>Reg : AUTO_HW_PADDING</b> : 0x000000684<br><b>reg sep address</b> : <b> reg host address</b> : <br>HW padding automatically activated by engine. For the special case of ZERO bytes data vector this register should not be used! 7584instead use HASH_PAD_CFG<br><table border="1" bgcolor="#EEEEEE" width="800"> 7585 <tr> 7586 <td colspan="32" align="center">AUTO_HW_PADDING</td> 7587 </tr> 7588 <tr></tr> 7589</table> 7590<table border="1" width="800"> 7591 <tr> 7592 <td width="40"><b>bits</b></td> 7593 <td width="100"><b>Field name</b></td> 7594 <td width="20"><b>permission</b></td> 7595 <td width="40"><b>default</b></td> 7596 <td width="600"><b>Description</b></td> 7597 </tr> 7598 <tr> 7599 <td valign="top" align="center"><a name="1.5.10.1"></a>0:0 7600 </td> 7601 <td valign="top">EN</td> 7602 <td valign="top" align="center">wo</td> 7603 <td valign="top" align="center">0x0</td> 7604 <td valign="top">1'b1 - Enable Automatic HW padding (No need for SW intervention by writing PAD_CFG). <br>Note: Not supported for 0 bytes !<br>Note: Disable this register when HASH op is done 7605 </td> 7606 </tr> 7607 <tr> 7608 <td valign="top" align="center"><a name="1.5.10.2"></a>31:1 7609 </td> 7610 <td valign="top">RESERVED</td> 7611 <td valign="top" align="center">wo</td> 7612 <td valign="top" align="center">0x0</td> 7613 <td valign="top">Reserved</td> 7614 </tr> 7615</table><a name="1.5.11"></a><br>1.5.11 : <b>Reg : HASH_XOR_DIN</b> : 0x000000688<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is always xored with the input to the hash engine,it should be '0' if xored is not reqiured .<br><table border="1" bgcolor="#EEEEEE" width="800"> 7616 <tr> 7617 <td colspan="32" align="center">HASH_XOR_DIN</td> 7618 </tr> 7619 <tr></tr> 7620</table> 7621<table border="1" width="800"> 7622 <tr> 7623 <td width="40"><b>bits</b></td> 7624 <td width="100"><b>Field name</b></td> 7625 <td width="20"><b>permission</b></td> 7626 <td width="40"><b>default</b></td> 7627 <td width="600"><b>Description</b></td> 7628 </tr> 7629 <tr> 7630 <td valign="top" align="center"><a name="1.5.11.1"></a>31:0 7631 </td> 7632 <td valign="top">HASH_XOR_DATA</td> 7633 <td valign="top" align="center">rw</td> 7634 <td valign="top" align="center">0x0</td> 7635 <td valign="top">This register holds the value to be xor-ed with hash input data.</td> 7636 </tr> 7637</table><a name="1.5.12"></a><br>1.5.12 : <b>Reg : LOAD_INIT_STATE</b> : 0x000000694<br><b>reg sep address</b> : <b> reg host address</b> : <br>Indication to HASH that the following data is to be loaded into initial value registers in HASH(H0:H15) or IV to AES MAC<br><table border="1" bgcolor="#EEEEEE" width="800"> 7638 <tr> 7639 <td colspan="32" align="center">LOAD_INIT_STATE</td> 7640 </tr> 7641 <tr></tr> 7642</table> 7643<table border="1" width="800"> 7644 <tr> 7645 <td width="40"><b>bits</b></td> 7646 <td width="100"><b>Field name</b></td> 7647 <td width="20"><b>permission</b></td> 7648 <td width="40"><b>default</b></td> 7649 <td width="600"><b>Description</b></td> 7650 </tr> 7651 <tr> 7652 <td valign="top" align="center"><a name="1.5.12.1"></a>0:0 7653 </td> 7654 <td valign="top">LOAD</td> 7655 <td valign="top" align="center">wo</td> 7656 <td valign="top" align="center">0x0</td> 7657 <td valign="top">Load data to initial state registers. digest/iv for hash/aes_mac. When done loading data this bit should be reset</td> 7658 </tr> 7659 <tr> 7660 <td valign="top" align="center"><a name="1.5.12.2"></a>31:1 7661 </td> 7662 <td valign="top">RESERVED</td> 7663 <td valign="top" align="center">wo</td> 7664 <td valign="top" align="center">0x0</td> 7665 <td valign="top">Reserved</td> 7666 </tr> 7667</table><a name="1.5.13"></a><br>1.5.13 : <b>Reg : HASH_SEL_AES_MAC</b> : 0x0000006A4<br><b>reg sep address</b> : <b> reg host address</b> : <br>select the AES MAC module rather than the hash module<br><table border="1" bgcolor="#EEEEEE" width="800"> 7668 <tr> 7669 <td colspan="32" align="center">HASH_SEL_AES_MAC</td> 7670 </tr> 7671 <tr></tr> 7672</table> 7673<table border="1" width="800"> 7674 <tr> 7675 <td width="40"><b>bits</b></td> 7676 <td width="100"><b>Field name</b></td> 7677 <td width="20"><b>permission</b></td> 7678 <td width="40"><b>default</b></td> 7679 <td width="600"><b>Description</b></td> 7680 </tr> 7681 <tr> 7682 <td valign="top" align="center"><a name="1.5.13.1"></a>0:0 7683 </td> 7684 <td valign="top">HASH_SEL_AES_MAC</td> 7685 <td valign="top" align="center">wo</td> 7686 <td valign="top" align="center">0x0</td> 7687 <td valign="top">@1'b0 - select the hash module<br>@1'b1 - select the AES mac module 7688 </td> 7689 </tr> 7690 <tr> 7691 <td valign="top" align="center"><a name="1.5.13.2"></a>1:1 7692 </td> 7693 <td valign="top">GHASH_SEL</td> 7694 <td valign="top" align="center">wo</td> 7695 <td valign="top" align="center">0x0</td> 7696 <td valign="top">@1'b0 - select the hash module<br>@1'b1 - select the ghash module 7697 </td> 7698 </tr> 7699 <tr> 7700 <td valign="top" align="center"><a name="1.5.13.3"></a>31:2 7701 </td> 7702 <td valign="top">RESERVED</td> 7703 <td valign="top" align="center">wo</td> 7704 <td valign="top" align="center">0x0</td> 7705 <td valign="top">Reserved</td> 7706 </tr> 7707</table><a name="1.5.14"></a><br>1.5.14 : <b>Reg : HASH_VERSION</b> : 0x0000007B0<br><b>reg sep address</b> : <b> reg host address</b> : <br>HASH VERSION Register<br><table border="1" bgcolor="#EEEEEE" width="800"> 7708 <tr> 7709 <td colspan="32" align="center">HASH_VERSION</td> 7710 </tr> 7711 <tr></tr> 7712</table> 7713<table border="1" width="800"> 7714 <tr> 7715 <td width="40"><b>bits</b></td> 7716 <td width="100"><b>Field name</b></td> 7717 <td width="20"><b>permission</b></td> 7718 <td width="40"><b>default</b></td> 7719 <td width="600"><b>Description</b></td> 7720 </tr> 7721 <tr> 7722 <td valign="top" align="center"><a name="1.5.14.1"></a>7:0 7723 </td> 7724 <td valign="top">FIXES</td> 7725 <td valign="top" align="center">ro</td> 7726 <td valign="top" align="center">0x0</td> 7727 <td valign="top"></td> 7728 </tr> 7729 <tr> 7730 <td valign="top" align="center"><a name="1.5.14.2"></a>11:8 7731 </td> 7732 <td valign="top">MINOR_VERSION_NUMBER</td> 7733 <td valign="top" align="center">ro</td> 7734 <td valign="top" align="center">0x0</td> 7735 <td valign="top">minor version number</td> 7736 </tr> 7737 <tr> 7738 <td valign="top" align="center"><a name="1.5.14.3"></a>15:12 7739 </td> 7740 <td valign="top">MAJOR_VERSION_NUMBER</td> 7741 <td valign="top" align="center">ro</td> 7742 <td valign="top" align="center">0x0</td> 7743 <td valign="top">major version number</td> 7744 </tr> 7745 <tr> 7746 <td valign="top" align="center"><a name="1.5.14.4"></a>31:16 7747 </td> 7748 <td valign="top">RESERVED</td> 7749 <td valign="top" align="center">ro</td> 7750 <td valign="top" align="center">0x0</td> 7751 <td valign="top">Reserved</td> 7752 </tr> 7753</table><a name="1.5.15"></a><br>1.5.15 : <b>Reg : HASH_CONTROL</b> : 0x0000007C0<br><b>reg sep address</b> : <b> reg host address</b> : <br>HASH_CONTROL Register. selects which HASH mode to run<br><table border="1" bgcolor="#EEEEEE" width="800"> 7754 <tr> 7755 <td colspan="32" align="center">HASH_CONTROL</td> 7756 </tr> 7757 <tr></tr> 7758</table> 7759<table border="1" width="800"> 7760 <tr> 7761 <td width="40"><b>bits</b></td> 7762 <td width="100"><b>Field name</b></td> 7763 <td width="20"><b>permission</b></td> 7764 <td width="40"><b>default</b></td> 7765 <td width="600"><b>Description</b></td> 7766 </tr> 7767 <tr> 7768 <td valign="top" align="center"><a name="1.5.15.1"></a>1:0 7769 </td> 7770 <td valign="top">MODE_0_1</td> 7771 <td valign="top" align="center">rw</td> 7772 <td valign="top" align="center">0x0</td> 7773 <td valign="top">bits 1:0 of the HASH mode field. The hash mode field possible values are:<br>@4'b0000 - MD5 if present<br>@4'b0001 - SHA-1<br>@4'b0010 - SHA-256<br>@4'b1010 - SHA-224 7774 </td> 7775 </tr> 7776 <tr> 7777 <td valign="top" align="center"><a name="1.5.15.2"></a>2:2 7778 </td> 7779 <td valign="top">RESERVED0</td> 7780 <td valign="top" align="center">rw</td> 7781 <td valign="top" align="center">0x0</td> 7782 <td valign="top">Reserved</td> 7783 </tr> 7784 <tr> 7785 <td valign="top" align="center"><a name="1.5.15.3"></a>3:3 7786 </td> 7787 <td valign="top">MODE_3</td> 7788 <td valign="top" align="center">rw</td> 7789 <td valign="top" align="center">0x0</td> 7790 <td valign="top">bit 3 of the HASH mode field. The hash mode field possible values are:4'b0000 - MD5 if present 4'b0001 - SHA-1 4'b0010 - SHA-256 7791 4'b1010 - SHA-224 7792 </td> 7793 </tr> 7794 <tr> 7795 <td valign="top" align="center"><a name="1.5.15.4"></a>31:4 7796 </td> 7797 <td valign="top">RESERVED1</td> 7798 <td valign="top" align="center">rw</td> 7799 <td valign="top" align="center">0x0</td> 7800 <td valign="top">Reserved</td> 7801 </tr> 7802</table><a name="1.5.16"></a><br>1.5.16 : <b>Reg : HASH_PAD_EN</b> : 0x0000007C4<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register enables the hash hw padding .<br><table border="1" bgcolor="#EEEEEE" width="800"> 7803 <tr> 7804 <td colspan="32" align="center">HASH_PAD_EN</td> 7805 </tr> 7806 <tr></tr> 7807</table> 7808<table border="1" width="800"> 7809 <tr> 7810 <td width="40"><b>bits</b></td> 7811 <td width="100"><b>Field name</b></td> 7812 <td width="20"><b>permission</b></td> 7813 <td width="40"><b>default</b></td> 7814 <td width="600"><b>Description</b></td> 7815 </tr> 7816 <tr> 7817 <td valign="top" align="center"><a name="1.5.16.1"></a>0:0 7818 </td> 7819 <td valign="top">EN</td> 7820 <td valign="top" align="center">rw</td> 7821 <td valign="top" align="center">0x1</td> 7822 <td valign="top">1 - Enable generation of padding by HW Pad block.<br>0 - Disable generation of padding by HW Pad block. 7823 </td> 7824 </tr> 7825 <tr> 7826 <td valign="top" align="center"><a name="1.5.16.2"></a>31:1 7827 </td> 7828 <td valign="top">RESERVED</td> 7829 <td valign="top" align="center">rw</td> 7830 <td valign="top" align="center">0x0</td> 7831 <td valign="top">Reserved</td> 7832 </tr> 7833</table><a name="1.5.17"></a><br>1.5.17 : <b>Reg : HASH_PAD_CFG</b> : 0x0000007C8<br><b>reg sep address</b> : <b> reg host address</b> : <br>HASH_PAD_CFG Register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7834 <tr> 7835 <td colspan="32" align="center">HASH_PAD_CFG</td> 7836 </tr> 7837 <tr></tr> 7838</table> 7839<table border="1" width="800"> 7840 <tr> 7841 <td width="40"><b>bits</b></td> 7842 <td width="100"><b>Field name</b></td> 7843 <td width="20"><b>permission</b></td> 7844 <td width="40"><b>default</b></td> 7845 <td width="600"><b>Description</b></td> 7846 </tr> 7847 <tr> 7848 <td valign="top" align="center"><a name="1.5.17.1"></a>1:0 7849 </td> 7850 <td valign="top">RESERVED0</td> 7851 <td valign="top" align="center">rw</td> 7852 <td valign="top" align="center">0x0</td> 7853 <td valign="top">Reserved</td> 7854 </tr> 7855 <tr> 7856 <td valign="top" align="center"><a name="1.5.17.2"></a>2:2 7857 </td> 7858 <td valign="top">DO_PAD</td> 7859 <td valign="top" align="center">rw</td> 7860 <td valign="top" align="center">0x0</td> 7861 <td valign="top">Enable Padding generation. must be reset upon completion of padding.</td> 7862 </tr> 7863 <tr> 7864 <td valign="top" align="center"><a name="1.5.17.3"></a>31:3 7865 </td> 7866 <td valign="top">RESERVED1</td> 7867 <td valign="top" align="center">rw</td> 7868 <td valign="top" align="center">0x0</td> 7869 <td valign="top">Reserved</td> 7870 </tr> 7871</table><a name="1.5.18"></a><br>1.5.18 : <b>Reg : HASH_CUR_LEN_0</b> : 0x0000007CC<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register hold the length of current hash operation bit 31:0.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7872 <tr> 7873 <td colspan="32" align="center">HASH_CUR_LEN_0</td> 7874 </tr> 7875 <tr></tr> 7876</table> 7877<table border="1" width="800"> 7878 <tr> 7879 <td width="40"><b>bits</b></td> 7880 <td width="100"><b>Field name</b></td> 7881 <td width="20"><b>permission</b></td> 7882 <td width="40"><b>default</b></td> 7883 <td width="600"><b>Description</b></td> 7884 </tr> 7885 <tr> 7886 <td valign="top" align="center"><a name="1.5.18.1"></a>31:0 7887 </td> 7888 <td valign="top">Length</td> 7889 <td valign="top" align="center">rw</td> 7890 <td valign="top" align="center">0x0</td> 7891 <td valign="top">Represent the current length of valid bits where digest need to be computed In Bytes.</td> 7892 </tr> 7893</table><a name="1.5.19"></a><br>1.5.19 : <b>Reg : HASH_CUR_LEN_1</b> : 0x0000007D0<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register hold the length of current hash operation bit 63:32.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7894 <tr> 7895 <td colspan="32" align="center">HASH_CUR_LEN_1</td> 7896 </tr> 7897 <tr></tr> 7898</table> 7899<table border="1" width="800"> 7900 <tr> 7901 <td width="40"><b>bits</b></td> 7902 <td width="100"><b>Field name</b></td> 7903 <td width="20"><b>permission</b></td> 7904 <td width="40"><b>default</b></td> 7905 <td width="600"><b>Description</b></td> 7906 </tr> 7907 <tr> 7908 <td valign="top" align="center"><a name="1.5.19.1"></a>31:0 7909 </td> 7910 <td valign="top">Length</td> 7911 <td valign="top" align="center">rw</td> 7912 <td valign="top" align="center">0x0</td> 7913 <td valign="top">Represent the current length of valid bits where digest need to be computed In Bytes.</td> 7914 </tr> 7915</table><a name="1.5.20"></a><br>1.5.20 : <b>Reg : HASH_PARAM</b> : 0x0000007DC<br><b>reg sep address</b> : <b> reg host address</b> : <br>HASH_PARAM Register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 7916 <tr> 7917 <td colspan="32" align="center">HASH_PARAM</td> 7918 </tr> 7919 <tr></tr> 7920</table> 7921<table border="1" width="800"> 7922 <tr> 7923 <td width="40"><b>bits</b></td> 7924 <td width="100"><b>Field name</b></td> 7925 <td width="20"><b>permission</b></td> 7926 <td width="40"><b>default</b></td> 7927 <td width="600"><b>Description</b></td> 7928 </tr> 7929 <tr> 7930 <td valign="top" align="center"><a name="1.5.20.1"></a>3:0 7931 </td> 7932 <td valign="top">CW</td> 7933 <td valign="top" align="center">ro</td> 7934 <td valign="top" align="center">0x1</td> 7935 <td valign="top">Indicates the number of concurrent words the hash is using to compute signature. 1 - One concurrent w(t). 2 - Two concurrent 7936 w(t). 7937 </td> 7938 </tr> 7939 <tr> 7940 <td valign="top" align="center"><a name="1.5.20.2"></a>7:4 7941 </td> 7942 <td valign="top">CH</td> 7943 <td valign="top" align="center">ro</td> 7944 <td valign="top" align="center">0x0</td> 7945 <td valign="top">Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. 0 - One Hi value is updated at a time 7946 1 - All Hi values are updated at the same time. 7947 </td> 7948 </tr> 7949 <tr> 7950 <td valign="top" align="center"><a name="1.5.20.3"></a>11:8 7951 </td> 7952 <td valign="top">DW</td> 7953 <td valign="top" align="center">ro</td> 7954 <td valign="top" align="center">0x0</td> 7955 <td valign="top">Determine the granularity of word size. 0 - 32 bit word data. 1 - 64 bit word data.</td> 7956 </tr> 7957 <tr> 7958 <td valign="top" align="center"><a name="1.5.20.4"></a>12:12 7959 </td> 7960 <td valign="top">SHA_512_EXISTS</td> 7961 <td valign="top" align="center">ro</td> 7962 <td valign="top" align="center">0x0</td> 7963 <td valign="top">Indicate if SHA-512 is present in the design. By default SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are present 7964 only 1 - SHA-1 and all SHA-2 are present (SHA-256 SHA-512). 7965 </td> 7966 </tr> 7967 <tr> 7968 <td valign="top" align="center"><a name="1.5.20.5"></a>13:13 7969 </td> 7970 <td valign="top">PAD_EXISTS</td> 7971 <td valign="top" align="center">ro</td> 7972 <td valign="top" align="center">0x1</td> 7973 <td valign="top">Indicate if pad block is present in the design. 0 - pad function is not supported by hardware. 1 - pad function is supported 7974 by hardware. 7975 </td> 7976 </tr> 7977 <tr> 7978 <td valign="top" align="center"><a name="1.5.20.6"></a>14:14 7979 </td> 7980 <td valign="top">MD5_EXISTS</td> 7981 <td valign="top" align="center">ro</td> 7982 <td valign="top" align="center">0x0</td> 7983 <td valign="top">Indicate if MD5 is present in HW</td> 7984 </tr> 7985 <tr> 7986 <td valign="top" align="center"><a name="1.5.20.7"></a>15:15 7987 </td> 7988 <td valign="top">HMAC_EXISTS</td> 7989 <td valign="top" align="center">ro</td> 7990 <td valign="top" align="center">0x0</td> 7991 <td valign="top">Indicate if HMAC logic is present in the design</td> 7992 </tr> 7993 <tr> 7994 <td valign="top" align="center"><a name="1.5.20.8"></a>16:16 7995 </td> 7996 <td valign="top">SHA_256_EXISTS</td> 7997 <td valign="top" align="center">ro</td> 7998 <td valign="top" align="center">0x1</td> 7999 <td valign="top">Indicate if SHA-256 is present in the design</td> 8000 </tr> 8001 <tr> 8002 <td valign="top" align="center"><a name="1.5.20.9"></a>17:17 8003 </td> 8004 <td valign="top">HASH_COMPARE_EXISTS</td> 8005 <td valign="top" align="center">ro</td> 8006 <td valign="top" align="center">0x0</td> 8007 <td valign="top">Indicate if COMPARE digest logic is present in the design</td> 8008 </tr> 8009 <tr> 8010 <td valign="top" align="center"><a name="1.5.20.10"></a>18:18 8011 </td> 8012 <td valign="top">DUMP_HASH_TO_DOUT_EXISTS</td> 8013 <td valign="top" align="center">ro</td> 8014 <td valign="top" align="center">0x0</td> 8015 <td valign="top">Indicate if HASH to dout is present in the design</td> 8016 </tr> 8017 <tr> 8018 <td valign="top" align="center"><a name="1.5.20.11"></a>31:19 8019 </td> 8020 <td valign="top">RESERVED</td> 8021 <td valign="top" align="center">ro</td> 8022 <td valign="top" align="center">0x0</td> 8023 <td valign="top">Reserved</td> 8024 </tr> 8025</table><a name="1.5.21"></a><br>1.5.21 : <b>Reg : HASH_AES_SW_RESET</b> : 0x0000007E4<br><b>reg sep address</b> : <b> reg host address</b> : <br>HASH_AES_SW_RESET Register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8026 <tr> 8027 <td colspan="32" align="center">HASH_AES_SW_RESET</td> 8028 </tr> 8029 <tr></tr> 8030</table> 8031<table border="1" width="800"> 8032 <tr> 8033 <td width="40"><b>bits</b></td> 8034 <td width="100"><b>Field name</b></td> 8035 <td width="20"><b>permission</b></td> 8036 <td width="40"><b>default</b></td> 8037 <td width="600"><b>Description</b></td> 8038 </tr> 8039 <tr> 8040 <td valign="top" align="center"><a name="1.5.21.1"></a>0:0 8041 </td> 8042 <td valign="top">HASH_AES_SW_RESET</td> 8043 <td valign="top" align="center">wo</td> 8044 <td valign="top" align="center">0x0</td> 8045 <td valign="top">Hash receive reset internally.</td> 8046 </tr> 8047 <tr> 8048 <td valign="top" align="center"><a name="1.5.21.2"></a>31:1 8049 </td> 8050 <td valign="top">RESERVED</td> 8051 <td valign="top" align="center">wo</td> 8052 <td valign="top" align="center">0x0</td> 8053 <td valign="top">Reserved</td> 8054 </tr> 8055</table><a name="1.5.22"></a><br>1.5.22 : <b>Reg : HASH_ENDIANESS</b> : 0x0000007E8<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register hold the HASH_ENDIANESS configuration.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8056 <tr> 8057 <td colspan="32" align="center">HASH_ENDIANESS</td> 8058 </tr> 8059 <tr></tr> 8060</table> 8061<table border="1" width="800"> 8062 <tr> 8063 <td width="40"><b>bits</b></td> 8064 <td width="100"><b>Field name</b></td> 8065 <td width="20"><b>permission</b></td> 8066 <td width="40"><b>default</b></td> 8067 <td width="600"><b>Description</b></td> 8068 </tr> 8069 <tr> 8070 <td valign="top" align="center"><a name="1.5.22.1"></a>0:0 8071 </td> 8072 <td valign="top">ENDIAN</td> 8073 <td valign="top" align="center">rw</td> 8074 <td valign="top" align="center">0x1</td> 8075 <td valign="top">The default value is little-endian. The data and generation of padding can be swapped to be big-endian.</td> 8076 </tr> 8077 <tr> 8078 <td valign="top" align="center"><a name="1.5.22.2"></a>31:1 8079 </td> 8080 <td valign="top">RESERVED</td> 8081 <td valign="top" align="center">rw</td> 8082 <td valign="top" align="center">0x0</td> 8083 <td valign="top">Reserved</td> 8084 </tr> 8085</table><a href="#1.5">(top of block)</a><a name="1.6"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 8086 <td><b><font color="#000000">1.6 : Block: MISC</font></b></td> 8087 <td align="right"><font color="#000000">0x000000800</font></td> 8088</table><br><a name="1.6.1"></a><br>1.6.1 : <b>Reg : AES_CLK_ENABLE</b> : 0x000000810<br><b>reg sep address</b> : <b> reg host address</b> : <br>The AES clock enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8089 <tr> 8090 <td colspan="32" align="center">AES_CLK_ENABLE</td> 8091 </tr> 8092 <tr></tr> 8093</table> 8094<table border="1" width="800"> 8095 <tr> 8096 <td width="40"><b>bits</b></td> 8097 <td width="100"><b>Field name</b></td> 8098 <td width="20"><b>permission</b></td> 8099 <td width="40"><b>default</b></td> 8100 <td width="600"><b>Description</b></td> 8101 </tr> 8102 <tr> 8103 <td valign="top" align="center"><a name="1.6.1.1"></a>0:0 8104 </td> 8105 <td valign="top">EN</td> 8106 <td valign="top" align="center">rw</td> 8107 <td valign="top" align="center">0x0</td> 8108 <td valign="top">@1'b1 - the AES clock is enabled.<br>@1'b0 - the AES clock is disabled. 8109 </td> 8110 </tr> 8111 <tr> 8112 <td valign="top" align="center"><a name="1.6.1.2"></a>31:1 8113 </td> 8114 <td valign="top">RESERVED</td> 8115 <td valign="top" align="center">rw</td> 8116 <td valign="top" align="center">0x0</td> 8117 <td valign="top">Reserved</td> 8118 </tr> 8119</table><a name="1.6.2"></a><br>1.6.2 : <b>Reg : HASH_CLK_ENABLE</b> : 0x000000818<br><b>reg sep address</b> : <b> reg host address</b> : <br>The HASH clock enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8120 <tr> 8121 <td colspan="32" align="center">HASH_CLK_ENABLE</td> 8122 </tr> 8123 <tr></tr> 8124</table> 8125<table border="1" width="800"> 8126 <tr> 8127 <td width="40"><b>bits</b></td> 8128 <td width="100"><b>Field name</b></td> 8129 <td width="20"><b>permission</b></td> 8130 <td width="40"><b>default</b></td> 8131 <td width="600"><b>Description</b></td> 8132 </tr> 8133 <tr> 8134 <td valign="top" align="center"><a name="1.6.2.1"></a>0:0 8135 </td> 8136 <td valign="top">EN</td> 8137 <td valign="top" align="center">rw</td> 8138 <td valign="top" align="center">0x0</td> 8139 <td valign="top">@1'b1 - the HASH clock is enabled.<br>@1'b0 - the HASH clock is disabled. 8140 </td> 8141 </tr> 8142 <tr> 8143 <td valign="top" align="center"><a name="1.6.2.2"></a>31:1 8144 </td> 8145 <td valign="top">RESERVED</td> 8146 <td valign="top" align="center">rw</td> 8147 <td valign="top" align="center">0x0</td> 8148 <td valign="top">Reserved</td> 8149 </tr> 8150</table><a name="1.6.3"></a><br>1.6.3 : <b>Reg : PKA_CLK_ENABLE</b> : 0x00000081C<br><b>reg sep address</b> : <b> reg host address</b> : <br>The PKA clock enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8151 <tr> 8152 <td colspan="32" align="center">PKA_CLK_ENABLE</td> 8153 </tr> 8154 <tr></tr> 8155</table> 8156<table border="1" width="800"> 8157 <tr> 8158 <td width="40"><b>bits</b></td> 8159 <td width="100"><b>Field name</b></td> 8160 <td width="20"><b>permission</b></td> 8161 <td width="40"><b>default</b></td> 8162 <td width="600"><b>Description</b></td> 8163 </tr> 8164 <tr> 8165 <td valign="top" align="center"><a name="1.6.3.1"></a>0:0 8166 </td> 8167 <td valign="top">EN</td> 8168 <td valign="top" align="center">rw</td> 8169 <td valign="top" align="center">0x0</td> 8170 <td valign="top">@1'b1 - the PKA clock is enabled.<br>@1'b0 - the PKA clock is disabled. 8171 </td> 8172 </tr> 8173 <tr> 8174 <td valign="top" align="center"><a name="1.6.3.2"></a>31:1 8175 </td> 8176 <td valign="top">RESERVED</td> 8177 <td valign="top" align="center">rw</td> 8178 <td valign="top" align="center">0x0</td> 8179 <td valign="top">Reserved</td> 8180 </tr> 8181</table><a name="1.6.4"></a><br>1.6.4 : <b>Reg : DMA_CLK_ENABLE</b> : 0x000000820<br><b>reg sep address</b> : <b> reg host address</b> : <br>DMA_CLK enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8182 <tr> 8183 <td colspan="32" align="center">DMA_CLK_ENABLE</td> 8184 </tr> 8185 <tr></tr> 8186</table> 8187<table border="1" width="800"> 8188 <tr> 8189 <td width="40"><b>bits</b></td> 8190 <td width="100"><b>Field name</b></td> 8191 <td width="20"><b>permission</b></td> 8192 <td width="40"><b>default</b></td> 8193 <td width="600"><b>Description</b></td> 8194 </tr> 8195 <tr> 8196 <td valign="top" align="center"><a name="1.6.4.1"></a>0:0 8197 </td> 8198 <td valign="top">EN</td> 8199 <td valign="top" align="center">rw</td> 8200 <td valign="top" align="center">0x0</td> 8201 <td valign="top">@1'b1 - the DMA clock is enabled.<br>@1'b0 - the DMA clock is disabled. 8202 </td> 8203 </tr> 8204 <tr> 8205 <td valign="top" align="center"><a name="1.6.4.2"></a>31:1 8206 </td> 8207 <td valign="top">RESERVED</td> 8208 <td valign="top" align="center">rw</td> 8209 <td valign="top" align="center">0x0</td> 8210 <td valign="top">Reserved</td> 8211 </tr> 8212</table><a name="1.6.5"></a><br>1.6.5 : <b>Reg : CLK_STATUS</b> : 0x000000824<br><b>reg sep address</b> : <b> reg host address</b> : <br>The CryptoCell clocks' status register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8213 <tr> 8214 <td colspan="32" align="center">CLK_STATUS</td> 8215 </tr> 8216 <tr></tr> 8217</table> 8218<table border="1" width="800"> 8219 <tr> 8220 <td width="40"><b>bits</b></td> 8221 <td width="100"><b>Field name</b></td> 8222 <td width="20"><b>permission</b></td> 8223 <td width="40"><b>default</b></td> 8224 <td width="600"><b>Description</b></td> 8225 </tr> 8226 <tr> 8227 <td valign="top" align="center"><a name="1.6.5.1"></a>0:0 8228 </td> 8229 <td valign="top">AES_CLK_STATUS</td> 8230 <td valign="top" align="center">ro</td> 8231 <td valign="top" align="center">0x0</td> 8232 <td valign="top">@1'b1 - the AES clock is enabled.<br>@1'b0 - the AES clock is disabled. 8233 </td> 8234 </tr> 8235 <tr> 8236 <td valign="top" align="center"><a name="1.6.5.2"></a>1:1 8237 </td> 8238 <td valign="top">RESERVED</td> 8239 <td valign="top" align="center">ro</td> 8240 <td valign="top" align="center">0x0</td> 8241 <td valign="top">@1'b1 - the DES clock is enabled.<br>@1'b0 - the DES clock is disabled. 8242 </td> 8243 </tr> 8244 <tr> 8245 <td valign="top" align="center"><a name="1.6.5.3"></a>2:2 8246 </td> 8247 <td valign="top">HASH_CLK_STATUS</td> 8248 <td valign="top" align="center">ro</td> 8249 <td valign="top" align="center">0x0</td> 8250 <td valign="top">@1'b1 - the HASH clock is enabled.<br>@1'b0 - the HASH clock is disabled. 8251 </td> 8252 </tr> 8253 <tr> 8254 <td valign="top" align="center"><a name="1.6.5.4"></a>3:3 8255 </td> 8256 <td valign="top">PKA_CLK_STATUS</td> 8257 <td valign="top" align="center">ro</td> 8258 <td valign="top" align="center">0x0</td> 8259 <td valign="top">@1'b1 - the PKA clock is enabled.<br>@1'b0 - the PKA clock is disabled. 8260 </td> 8261 </tr> 8262 <tr> 8263 <td valign="top" align="center"><a name="1.6.5.5"></a>6:4 8264 </td> 8265 <td valign="top">RESERVED0</td> 8266 <td valign="top" align="center">ro</td> 8267 <td valign="top" align="center">0x0</td> 8268 <td valign="top">Reserved</td> 8269 </tr> 8270 <tr> 8271 <td valign="top" align="center"><a name="1.6.5.6"></a>7:7 8272 </td> 8273 <td valign="top">CHACHA_CLK_STATUS</td> 8274 <td valign="top" align="center">ro</td> 8275 <td valign="top" align="center">0x0</td> 8276 <td valign="top">@1'b1 - the CHACHA clock is enabled.<br>@1'b0 - the CHACHA clock is disabled. 8277 </td> 8278 </tr> 8279 <tr> 8280 <td valign="top" align="center"><a name="1.6.5.7"></a>8:8 8281 </td> 8282 <td valign="top">DMA_CLK_STATUS</td> 8283 <td valign="top" align="center">ro</td> 8284 <td valign="top" align="center">0x1</td> 8285 <td valign="top">@1'b1 - the DMA clock is enabled.<br>@1'b0 - the DMA clock is disabled. 8286 </td> 8287 </tr> 8288 <tr> 8289 <td valign="top" align="center"><a name="1.6.5.8"></a>31:9 8290 </td> 8291 <td valign="top">RESERVED1</td> 8292 <td valign="top" align="center">ro</td> 8293 <td valign="top" align="center">0x0</td> 8294 <td valign="top">Reserved</td> 8295 </tr> 8296</table><a name="1.6.6"></a><br>1.6.6 : <b>Reg : CHACHA_CLK_ENABLE</b> : 0x000000858<br><b>reg sep address</b> : <b> reg host address</b> : <br>CHACHA /SALSA clock enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8297 <tr> 8298 <td colspan="32" align="center">CHACHA_CLK_ENABLE</td> 8299 </tr> 8300 <tr></tr> 8301</table> 8302<table border="1" width="800"> 8303 <tr> 8304 <td width="40"><b>bits</b></td> 8305 <td width="100"><b>Field name</b></td> 8306 <td width="20"><b>permission</b></td> 8307 <td width="40"><b>default</b></td> 8308 <td width="600"><b>Description</b></td> 8309 </tr> 8310 <tr> 8311 <td valign="top" align="center"><a name="1.6.6.1"></a>0:0 8312 </td> 8313 <td valign="top">EN</td> 8314 <td valign="top" align="center">wo</td> 8315 <td valign="top" align="center">0x0</td> 8316 <td valign="top">@1'b1 - the CHACHA / SALSA clock is enabled.<br>@1'b0 - the CHACHA / SALSA clock is disabled. 8317 </td> 8318 </tr> 8319 <tr> 8320 <td valign="top" align="center"><a name="1.6.6.2"></a>31:1 8321 </td> 8322 <td valign="top">RESERVED</td> 8323 <td valign="top" align="center">wo</td> 8324 <td valign="top" align="center">0x0</td> 8325 <td valign="top">Reserved</td> 8326 </tr> 8327</table><a href="#1.6">(top of block)</a><a name="1.7"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 8328 <td><b><font color="#000000">1.7 : Block: CC_CTL</font></b></td> 8329 <td align="right"><font color="#000000">0x000000900</font></td> 8330</table><br><a name="1.7.1"></a><br>1.7.1 : <b>Reg : CRYPTO_CTL</b> : 0x000000900<br><b>reg sep address</b> : <b> reg host address</b> : <br>Defines the cryptographic flow.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8331 <tr> 8332 <td colspan="32" align="center">CRYPTO_CTL</td> 8333 </tr> 8334 <tr></tr> 8335</table> 8336<table border="1" width="800"> 8337 <tr> 8338 <td width="40"><b>bits</b></td> 8339 <td width="100"><b>Field name</b></td> 8340 <td width="20"><b>permission</b></td> 8341 <td width="40"><b>default</b></td> 8342 <td width="600"><b>Description</b></td> 8343 </tr> 8344 <tr> 8345 <td valign="top" align="center"><a name="1.7.1.1"></a>4:0 8346 </td> 8347 <td valign="top">MODE</td> 8348 <td valign="top" align="center">wo</td> 8349 <td valign="top" align="center">0x0</td> 8350 <td valign="top">Determines the active cryptographic engine:<br>@5'b0000 - BYPASS<br>@5'b0001 - AES<br>@5'b0010 - AES_TO_HASH<br>@5'b0011 - AES_AND_HASH<br>@5'b0100 - DES<br>@5'b0101 - DES_TO_HASH<br>@5'b0110 - DES_AND_HASH<br>@5'b0111 - HASH<br>@5'b1001 - AES_MAC_AND_BYPASS<br>@5'b1010 - AES_TO_HASH_AND_DOUT<br>@5'b1011 - Reserved<br>@5'b1000 - Reserved 8351 </td> 8352 </tr> 8353 <tr> 8354 <td valign="top" align="center"><a name="1.7.1.2"></a>31:5 8355 </td> 8356 <td valign="top">RESERVED</td> 8357 <td valign="top" align="center">wo</td> 8358 <td valign="top" align="center">0x0</td> 8359 <td valign="top">Reserved</td> 8360 </tr> 8361</table><a name="1.7.2"></a><br>1.7.2 : <b>Reg : CRYPTO_BUSY</b> : 0x000000910<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is set when the cryptographic core is busy.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8362 <tr> 8363 <td colspan="32" align="center">CRYPTO_BUSY</td> 8364 </tr> 8365 <tr></tr> 8366</table> 8367<table border="1" width="800"> 8368 <tr> 8369 <td width="40"><b>bits</b></td> 8370 <td width="100"><b>Field name</b></td> 8371 <td width="20"><b>permission</b></td> 8372 <td width="40"><b>default</b></td> 8373 <td width="600"><b>Description</b></td> 8374 </tr> 8375 <tr> 8376 <td valign="top" align="center"><a name="1.7.2.1"></a>0:0 8377 </td> 8378 <td valign="top">CRYPTO_BUSY</td> 8379 <td valign="top" align="center">ro</td> 8380 <td valign="top" align="center">0x0</td> 8381 <td valign="top">@1'b0 - Ready<br>@1'b1 - Busy<br>Asserted when AES_BUSY or DES_BUSY or HASH_BUSY are asserted or when the DIN FIFO is not empty. 8382 </td> 8383 </tr> 8384 <tr> 8385 <td valign="top" align="center"><a name="1.7.2.2"></a>31:1 8386 </td> 8387 <td valign="top">RESERVED</td> 8388 <td valign="top" align="center">ro</td> 8389 <td valign="top" align="center">0x0</td> 8390 <td valign="top">Reserved</td> 8391 </tr> 8392</table><a name="1.7.3"></a><br>1.7.3 : <b>Reg : HASH_BUSY</b> : 0x00000091C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is set when the Hash engine is busy.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8393 <tr> 8394 <td colspan="32" align="center">HASH_BUSY</td> 8395 </tr> 8396 <tr></tr> 8397</table> 8398<table border="1" width="800"> 8399 <tr> 8400 <td width="40"><b>bits</b></td> 8401 <td width="100"><b>Field name</b></td> 8402 <td width="20"><b>permission</b></td> 8403 <td width="40"><b>default</b></td> 8404 <td width="600"><b>Description</b></td> 8405 </tr> 8406 <tr> 8407 <td valign="top" align="center"><a name="1.7.3.1"></a>0:0 8408 </td> 8409 <td valign="top">HASH_BUSY</td> 8410 <td valign="top" align="center">ro</td> 8411 <td valign="top" align="center">0x0</td> 8412 <td valign="top">@1'b0 - Ready<br>@1'b1 - Busy<br>Asserted when hash engine is busy. 8413 </td> 8414 </tr> 8415 <tr> 8416 <td valign="top" align="center"><a name="1.7.3.2"></a>31:1 8417 </td> 8418 <td valign="top">RESERVED</td> 8419 <td valign="top" align="center">ro</td> 8420 <td valign="top" align="center">0x0</td> 8421 <td valign="top">Reserved</td> 8422 </tr> 8423</table><a name="1.7.4"></a><br>1.7.4 : <b>Reg : CONTEXT_ID</b> : 0x000000930<br><b>reg sep address</b> : <b> reg host address</b> : <br>A general RD/WR register. For Firmware use.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8424 <tr> 8425 <td colspan="32" align="center">CONTEXT_ID</td> 8426 </tr> 8427 <tr></tr> 8428</table> 8429<table border="1" width="800"> 8430 <tr> 8431 <td width="40"><b>bits</b></td> 8432 <td width="100"><b>Field name</b></td> 8433 <td width="20"><b>permission</b></td> 8434 <td width="40"><b>default</b></td> 8435 <td width="600"><b>Description</b></td> 8436 </tr> 8437 <tr> 8438 <td valign="top" align="center"><a name="1.7.4.1"></a>7:0 8439 </td> 8440 <td valign="top">CONTEXT_ID</td> 8441 <td valign="top" align="center">rw</td> 8442 <td valign="top" align="center">0x0</td> 8443 <td valign="top">Context ID</td> 8444 </tr> 8445 <tr> 8446 <td valign="top" align="center"><a name="1.7.4.2"></a>31:8 8447 </td> 8448 <td valign="top">RESERVED</td> 8449 <td valign="top" align="center">rw</td> 8450 <td valign="top" align="center">0x0</td> 8451 <td valign="top">Reserved</td> 8452 </tr> 8453</table><a href="#1.7">(top of block)</a><a name="1.8"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 8454 <td><b><font color="#000000">1.8 : Block: GHASH</font></b></td> 8455 <td align="right"><font color="#000000">0x000000960</font></td> 8456</table><br><a name="1.8.1"></a><br>1.8.1 : <b>Reg : GHASH_SUBKEY_0_0</b> : 0x000000960<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 31:0 of GHASH Key0 (used as the GHASH module key).<br><table border="1" bgcolor="#EEEEEE" width="800"> 8457 <tr> 8458 <td colspan="32" align="center">GHASH_SUBKEY_0_0</td> 8459 </tr> 8460 <tr></tr> 8461</table> 8462<table border="1" width="800"> 8463 <tr> 8464 <td width="40"><b>bits</b></td> 8465 <td width="100"><b>Field name</b></td> 8466 <td width="20"><b>permission</b></td> 8467 <td width="40"><b>default</b></td> 8468 <td width="600"><b>Description</b></td> 8469 </tr> 8470 <tr> 8471 <td valign="top" align="center"><a name="1.8.1.1"></a>31:0 8472 </td> 8473 <td valign="top">GHASH_SUBKEY_0_0</td> 8474 <td valign="top" align="center">wo</td> 8475 <td valign="top" align="center">0x0</td> 8476 <td valign="top">Bits 31:0 of GHASH Key0.</td> 8477 </tr> 8478</table><a name="1.8.2"></a><br>1.8.2 : <b>Reg : GHASH_SUBKEY_0_1</b> : 0x000000964<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 63:32 of GHASH Key0 (used as the GHASH module key).<br><table border="1" bgcolor="#EEEEEE" width="800"> 8479 <tr> 8480 <td colspan="32" align="center">GHASH_SUBKEY_0_1</td> 8481 </tr> 8482 <tr></tr> 8483</table> 8484<table border="1" width="800"> 8485 <tr> 8486 <td width="40"><b>bits</b></td> 8487 <td width="100"><b>Field name</b></td> 8488 <td width="20"><b>permission</b></td> 8489 <td width="40"><b>default</b></td> 8490 <td width="600"><b>Description</b></td> 8491 </tr> 8492 <tr> 8493 <td valign="top" align="center"><a name="1.8.2.1"></a>31:0 8494 </td> 8495 <td valign="top">GHASH_SUBKEY_0_1</td> 8496 <td valign="top" align="center">wo</td> 8497 <td valign="top" align="center">0x0</td> 8498 <td valign="top">Bits 63:32 of GHASH Key0.</td> 8499 </tr> 8500</table><a name="1.8.3"></a><br>1.8.3 : <b>Reg : GHASH_SUBKEY_0_2</b> : 0x000000968<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 95:64 of GHASH Key0 (used as the GHASH module key).<br><table border="1" bgcolor="#EEEEEE" width="800"> 8501 <tr> 8502 <td colspan="32" align="center">GHASH_SUBKEY_0_2</td> 8503 </tr> 8504 <tr></tr> 8505</table> 8506<table border="1" width="800"> 8507 <tr> 8508 <td width="40"><b>bits</b></td> 8509 <td width="100"><b>Field name</b></td> 8510 <td width="20"><b>permission</b></td> 8511 <td width="40"><b>default</b></td> 8512 <td width="600"><b>Description</b></td> 8513 </tr> 8514 <tr> 8515 <td valign="top" align="center"><a name="1.8.3.1"></a>31:0 8516 </td> 8517 <td valign="top">GHASH_SUBKEY_0_2</td> 8518 <td valign="top" align="center">wo</td> 8519 <td valign="top" align="center">0x0</td> 8520 <td valign="top">Bits 95:64 of GHASH Key0.</td> 8521 </tr> 8522</table><a name="1.8.4"></a><br>1.8.4 : <b>Reg : GHASH_SUBKEY_0_3</b> : 0x00000096C<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 127:96 of GHASH Key0 (used as the GHASH module key).<br><table border="1" bgcolor="#EEEEEE" width="800"> 8523 <tr> 8524 <td colspan="32" align="center">GHASH_SUBKEY_0_3</td> 8525 </tr> 8526 <tr></tr> 8527</table> 8528<table border="1" width="800"> 8529 <tr> 8530 <td width="40"><b>bits</b></td> 8531 <td width="100"><b>Field name</b></td> 8532 <td width="20"><b>permission</b></td> 8533 <td width="40"><b>default</b></td> 8534 <td width="600"><b>Description</b></td> 8535 </tr> 8536 <tr> 8537 <td valign="top" align="center"><a name="1.8.4.1"></a>31:0 8538 </td> 8539 <td valign="top">GHASH_SUBKEY_0_3</td> 8540 <td valign="top" align="center">wo</td> 8541 <td valign="top" align="center">0x0</td> 8542 <td valign="top">Bits 127:96 of GHASH Key0.</td> 8543 </tr> 8544</table><a name="1.8.5"></a><br>1.8.5 : <b>Reg : GHASH_IV_0_0</b> : 0x000000970<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 31:0 of GHASH_IV0 register. <br>GHASH IV0 is used as the GHASH IV (Initialization Value) register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8545 <tr> 8546 <td colspan="32" align="center">GHASH_IV_0_0</td> 8547 </tr> 8548 <tr></tr> 8549</table> 8550<table border="1" width="800"> 8551 <tr> 8552 <td width="40"><b>bits</b></td> 8553 <td width="100"><b>Field name</b></td> 8554 <td width="20"><b>permission</b></td> 8555 <td width="40"><b>default</b></td> 8556 <td width="600"><b>Description</b></td> 8557 </tr> 8558 <tr> 8559 <td valign="top" align="center"><a name="1.8.5.1"></a>31:0 8560 </td> 8561 <td valign="top">GHASH_IV_0_0</td> 8562 <td valign="top" align="center">r/wc</td> 8563 <td valign="top" align="center">0x0</td> 8564 <td valign="top">Bits 31:0 of GHASH_IV0 register of the GHASH module. <br>For the description of GHASH_IV0, see the GHASH_0_0 register description 8565 </td> 8566 </tr> 8567</table><a name="1.8.6"></a><br>1.8.6 : <b>Reg : GHASH_IV_0_1</b> : 0x000000974<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 63:32 of GHASH_IV0 register. <br>GHASH IV0 is used as the GHASH IV (Initialization Value) register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8568 <tr> 8569 <td colspan="32" align="center">GHASH_IV_0_1</td> 8570 </tr> 8571 <tr></tr> 8572</table> 8573<table border="1" width="800"> 8574 <tr> 8575 <td width="40"><b>bits</b></td> 8576 <td width="100"><b>Field name</b></td> 8577 <td width="20"><b>permission</b></td> 8578 <td width="40"><b>default</b></td> 8579 <td width="600"><b>Description</b></td> 8580 </tr> 8581 <tr> 8582 <td valign="top" align="center"><a name="1.8.6.1"></a>31:0 8583 </td> 8584 <td valign="top">GHASH_IV_0_1</td> 8585 <td valign="top" align="center">r/wc</td> 8586 <td valign="top" align="center">0x0</td> 8587 <td valign="top">Bits 63:32 of GHASH_IV0 register of the GHASH module. <br>For the description of GHASH_IV0, see the GHASH_0_0 register description 8588 </td> 8589 </tr> 8590</table><a name="1.8.7"></a><br>1.8.7 : <b>Reg : GHASH_IV_0_2</b> : 0x000000978<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 95:64 of GHASH_IV0 register. <br>GHASH IV0 is used as the GHASH IV (Initialization Value) register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8591 <tr> 8592 <td colspan="32" align="center">GHASH_IV_0_2</td> 8593 </tr> 8594 <tr></tr> 8595</table> 8596<table border="1" width="800"> 8597 <tr> 8598 <td width="40"><b>bits</b></td> 8599 <td width="100"><b>Field name</b></td> 8600 <td width="20"><b>permission</b></td> 8601 <td width="40"><b>default</b></td> 8602 <td width="600"><b>Description</b></td> 8603 </tr> 8604 <tr> 8605 <td valign="top" align="center"><a name="1.8.7.1"></a>31:0 8606 </td> 8607 <td valign="top">GHASH_IV_0_2</td> 8608 <td valign="top" align="center">r/wc</td> 8609 <td valign="top" align="center">0x0</td> 8610 <td valign="top">Bits 95:64 of GHASH_IV0 register of the GHASH module. <br>For the description of GHASH_IV0, see the GHASH_0_0 register description 8611 </td> 8612 </tr> 8613</table><a name="1.8.8"></a><br>1.8.8 : <b>Reg : GHASH_IV_0_3</b> : 0x00000097C<br><b>reg sep address</b> : <b> reg host address</b> : <br>Bits 127:96 of GHASH_IV0 register. <br>GHASH IV0 is used as the GHASH IV (Initialization Value) register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8614 <tr> 8615 <td colspan="32" align="center">GHASH_IV_0_3</td> 8616 </tr> 8617 <tr></tr> 8618</table> 8619<table border="1" width="800"> 8620 <tr> 8621 <td width="40"><b>bits</b></td> 8622 <td width="100"><b>Field name</b></td> 8623 <td width="20"><b>permission</b></td> 8624 <td width="40"><b>default</b></td> 8625 <td width="600"><b>Description</b></td> 8626 </tr> 8627 <tr> 8628 <td valign="top" align="center"><a name="1.8.8.1"></a>31:0 8629 </td> 8630 <td valign="top">GHASH_IV_0_3</td> 8631 <td valign="top" align="center">r/wc</td> 8632 <td valign="top" align="center">0x0</td> 8633 <td valign="top">Bits 127:96 of GHASH_IV0 register of the GHASH module. <br>For the description of GHASH_IV0, see the GHASH_0_0 register description 8634 </td> 8635 </tr> 8636</table><a name="1.8.9"></a><br>1.8.9 : <b>Reg : GHASH_BUSY</b> : 0x000000980<br><b>reg sep address</b> : <b> reg host address</b> : <br>The GHASH module GHASH_BUSY Register. This register is set when the GHASH core is active.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8637 <tr> 8638 <td colspan="32" align="center">GHASH_BUSY</td> 8639 </tr> 8640 <tr></tr> 8641</table> 8642<table border="1" width="800"> 8643 <tr> 8644 <td width="40"><b>bits</b></td> 8645 <td width="100"><b>Field name</b></td> 8646 <td width="20"><b>permission</b></td> 8647 <td width="40"><b>default</b></td> 8648 <td width="600"><b>Description</b></td> 8649 </tr> 8650 <tr> 8651 <td valign="top" align="center"><a name="1.8.9.1"></a>0:0 8652 </td> 8653 <td valign="top">GHASH_BUSY</td> 8654 <td valign="top" align="center">ro</td> 8655 <td valign="top" align="center">0x0</td> 8656 <td valign="top">GHASH_BUSY Register. this register is set when the GHASH core is active</td> 8657 </tr> 8658 <tr> 8659 <td valign="top" align="center"><a name="1.8.9.2"></a>31:1 8660 </td> 8661 <td valign="top">RESERVED</td> 8662 <td valign="top" align="center">ro</td> 8663 <td valign="top" align="center">0x0</td> 8664 <td valign="top">Reserved</td> 8665 </tr> 8666</table><a name="1.8.10"></a><br>1.8.10 : <b>Reg : GHASH_INIT</b> : 0x000000984<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this address sets the GHASH engine to be ready to a new GHASH operation.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8667 <tr> 8668 <td colspan="32" align="center">GHASH_INIT</td> 8669 </tr> 8670 <tr></tr> 8671</table> 8672<table border="1" width="800"> 8673 <tr> 8674 <td width="40"><b>bits</b></td> 8675 <td width="100"><b>Field name</b></td> 8676 <td width="20"><b>permission</b></td> 8677 <td width="40"><b>default</b></td> 8678 <td width="600"><b>Description</b></td> 8679 </tr> 8680 <tr> 8681 <td valign="top" align="center"><a name="1.8.10.1"></a>0:0 8682 </td> 8683 <td valign="top">GHASH_INIT</td> 8684 <td valign="top" align="center">wo</td> 8685 <td valign="top" align="center">0x0</td> 8686 <td valign="top">Writing to this address sets the GHASH engine to be ready to a new GHASH operation.</td> 8687 </tr> 8688 <tr> 8689 <td valign="top" align="center"><a name="1.8.10.2"></a>31:1 8690 </td> 8691 <td valign="top">RESERVED</td> 8692 <td valign="top" align="center">wo</td> 8693 <td valign="top" align="center">0x0</td> 8694 <td valign="top">Reserved</td> 8695 </tr> 8696</table><a href="#1.8">(top of block)</a><a name="1.9"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 8697 <td><b><font color="#000000">1.9 : Block: HOST_RGF</font></b></td> 8698 <td align="right"><font color="#000000">0x000000A00</font></td> 8699</table><br><a name="1.9.1"></a><br>1.9.1 : <b>Reg : HOST_RGF_IRR</b> : 0x000000A00<br><b>reg sep address</b> : <b> reg host address</b> : <br>The Interrupt Request register. Each bit of this register holds the interrupt status of a single interrupt source.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8700 <tr> 8701 <td colspan="32" align="center">HOST_RGF_IRR</td> 8702 </tr> 8703 <tr></tr> 8704</table> 8705<table border="1" width="800"> 8706 <tr> 8707 <td width="40"><b>bits</b></td> 8708 <td width="100"><b>Field name</b></td> 8709 <td width="20"><b>permission</b></td> 8710 <td width="40"><b>default</b></td> 8711 <td width="600"><b>Description</b></td> 8712 </tr> 8713 <tr> 8714 <td valign="top" align="center"><a name="1.9.1.1"></a>3:0 8715 </td> 8716 <td valign="top">unused0</td> 8717 <td valign="top" align="center">ro</td> 8718 <td valign="top" align="center">0x0</td> 8719 <td valign="top">Reserved</td> 8720 </tr> 8721 <tr> 8722 <td valign="top" align="center"><a name="1.9.1.2"></a>4:4 8723 </td> 8724 <td valign="top">SRAM_TO_DIN_INT</td> 8725 <td valign="top" align="center">ro</td> 8726 <td valign="top" align="center">0x0</td> 8727 <td valign="top">The SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered to DIN buffer from SRAM.</td> 8728 </tr> 8729 <tr> 8730 <td valign="top" align="center"><a name="1.9.1.3"></a>5:5 8731 </td> 8732 <td valign="top">DOUT_TO_SRAM_INT</td> 8733 <td valign="top" align="center">ro</td> 8734 <td valign="top" align="center">0x0</td> 8735 <td valign="top">The DOUT to SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered to SRAM buffer from DOUT.</td> 8736 </tr> 8737 <tr> 8738 <td valign="top" align="center"><a name="1.9.1.4"></a>6:6 8739 </td> 8740 <td valign="top">MEM_TO_DIN_INT</td> 8741 <td valign="top" align="center">ro</td> 8742 <td valign="top" align="center">0x0</td> 8743 <td valign="top">The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered to DIN buffer from memory.</td> 8744 </tr> 8745 <tr> 8746 <td valign="top" align="center"><a name="1.9.1.5"></a>7:7 8747 </td> 8748 <td valign="top">DOUT_TO_MEM_INT</td> 8749 <td valign="top" align="center">ro</td> 8750 <td valign="top" align="center">0x0</td> 8751 <td valign="top">The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered to memory buffer from 8752 DOUT. 8753 </td> 8754 </tr> 8755 <tr> 8756 <td valign="top" align="center"><a name="1.9.1.6"></a>8:8 8757 </td> 8758 <td valign="top">AHB_ERR_INT</td> 8759 <td valign="top" align="center">ro</td> 8760 <td valign="top" align="center">0x0</td> 8761 <td valign="top">The AXI error interrupt status.</td> 8762 </tr> 8763 <tr> 8764 <td valign="top" align="center"><a name="1.9.1.7"></a>9:9 8765 </td> 8766 <td valign="top">PKA_EXP_INT</td> 8767 <td valign="top" align="center">ro</td> 8768 <td valign="top" align="center">0x0</td> 8769 <td valign="top">The PKA end of operation interrupt status.</td> 8770 </tr> 8771 <tr> 8772 <td valign="top" align="center"><a name="1.9.1.8"></a>10:10 8773 </td> 8774 <td valign="top">RNG_INT</td> 8775 <td valign="top" align="center">ro</td> 8776 <td valign="top" align="center">0x0</td> 8777 <td valign="top">The RNG interrupt status.</td> 8778 </tr> 8779 <tr> 8780 <td valign="top" align="center"><a name="1.9.1.9"></a>11:11 8781 </td> 8782 <td valign="top">SYM_DMA_COMPLETED</td> 8783 <td valign="top" align="center">ro</td> 8784 <td valign="top" align="center">0x0</td> 8785 <td valign="top">The GPR interrupt status.</td> 8786 </tr> 8787 <tr> 8788 <td valign="top" align="center"><a name="1.9.1.10"></a>31:12 8789 </td> 8790 <td valign="top">RESERVED2</td> 8791 <td valign="top" align="center">ro</td> 8792 <td valign="top" align="center">0x0</td> 8793 <td valign="top">Reserved</td> 8794 </tr> 8795</table><a name="1.9.2"></a><br>1.9.2 : <b>Reg : HOST_RGF_IMR</b> : 0x000000A04<br><b>reg sep address</b> : <b> reg host address</b> : <br>The Interrupt Mask register. Each bit of this register holds the mask of a single interrupt source.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8796 <tr> 8797 <td colspan="32" align="center">HOST_RGF_IMR</td> 8798 </tr> 8799 <tr></tr> 8800</table> 8801<table border="1" width="800"> 8802 <tr> 8803 <td width="40"><b>bits</b></td> 8804 <td width="100"><b>Field name</b></td> 8805 <td width="20"><b>permission</b></td> 8806 <td width="40"><b>default</b></td> 8807 <td width="600"><b>Description</b></td> 8808 </tr> 8809 <tr> 8810 <td valign="top" align="center"><a name="1.9.2.1"></a>3:0 8811 </td> 8812 <td valign="top">unused0</td> 8813 <td valign="top" align="center">rw</td> 8814 <td valign="top" align="center">0x</td> 8815 <td valign="top">Reserved</td> 8816 </tr> 8817 <tr> 8818 <td valign="top" align="center"><a name="1.9.2.2"></a>4:4 8819 </td> 8820 <td valign="top">SRAM_TO_DIN_MASK</td> 8821 <td valign="top" align="center">rw</td> 8822 <td valign="top" align="center">0x1</td> 8823 <td valign="top">The SRAM to DIN DMA done interrupt mask.</td> 8824 </tr> 8825 <tr> 8826 <td valign="top" align="center"><a name="1.9.2.3"></a>5:5 8827 </td> 8828 <td valign="top">DOUT_TO_SRAM_MASK</td> 8829 <td valign="top" align="center">rw</td> 8830 <td valign="top" align="center">0x1</td> 8831 <td valign="top">The DOUT to SRAM DMA done interrupt mask.</td> 8832 </tr> 8833 <tr> 8834 <td valign="top" align="center"><a name="1.9.2.4"></a>6:6 8835 </td> 8836 <td valign="top">MEM_TO_DIN_MASK</td> 8837 <td valign="top" align="center">rw</td> 8838 <td valign="top" align="center">0x1</td> 8839 <td valign="top">The memory to DIN DMA done interrupt mask.</td> 8840 </tr> 8841 <tr> 8842 <td valign="top" align="center"><a name="1.9.2.5"></a>7:7 8843 </td> 8844 <td valign="top">DOUT_TO_MEM_MASK</td> 8845 <td valign="top" align="center">rw</td> 8846 <td valign="top" align="center">0x1</td> 8847 <td valign="top">The DOUT to memory DMA done interrupt mask.</td> 8848 </tr> 8849 <tr> 8850 <td valign="top" align="center"><a name="1.9.2.6"></a>8:8 8851 </td> 8852 <td valign="top">AXI_ERR_MASK</td> 8853 <td valign="top" align="center">rw</td> 8854 <td valign="top" align="center">0x1</td> 8855 <td valign="top">The AXI error interrupt mask.</td> 8856 </tr> 8857 <tr> 8858 <td valign="top" align="center"><a name="1.9.2.7"></a>9:9 8859 </td> 8860 <td valign="top">PKA_EXP_MASK</td> 8861 <td valign="top" align="center">rw</td> 8862 <td valign="top" align="center">0x1</td> 8863 <td valign="top">The PKA end of operation interrupt mask.</td> 8864 </tr> 8865 <tr> 8866 <td valign="top" align="center"><a name="1.9.2.8"></a>10:10 8867 </td> 8868 <td valign="top">RNG_INT_MASK</td> 8869 <td valign="top" align="center">rw</td> 8870 <td valign="top" align="center">0x1</td> 8871 <td valign="top">The RNG interrupt mask.</td> 8872 </tr> 8873 <tr> 8874 <td valign="top" align="center"><a name="1.9.2.9"></a>11:11 8875 </td> 8876 <td valign="top">SYM_DMA_COMPLETED_MASK</td> 8877 <td valign="top" align="center">rw</td> 8878 <td valign="top" align="center">0x1</td> 8879 <td valign="top">The GPR interrupt mask.</td> 8880 </tr> 8881 <tr> 8882 <td valign="top" align="center"><a name="1.9.2.10"></a>31:12 8883 </td> 8884 <td valign="top">RESERVED0</td> 8885 <td valign="top" align="center">rw</td> 8886 <td valign="top" align="center">0x0</td> 8887 <td valign="top">Reserved</td> 8888 </tr> 8889</table><a name="1.9.3"></a><br>1.9.3 : <b>Reg : HOST_RGF_ICR</b> : 0x000000A08<br><b>reg sep address</b> : <b> reg host address</b> : <br>Interrupt Clear Register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8890 <tr> 8891 <td colspan="32" align="center">HOST_RGF_ICR</td> 8892 </tr> 8893 <tr></tr> 8894</table> 8895<table border="1" width="800"> 8896 <tr> 8897 <td width="40"><b>bits</b></td> 8898 <td width="100"><b>Field name</b></td> 8899 <td width="20"><b>permission</b></td> 8900 <td width="40"><b>default</b></td> 8901 <td width="600"><b>Description</b></td> 8902 </tr> 8903 <tr> 8904 <td valign="top" align="center"><a name="1.9.3.1"></a>3:0 8905 </td> 8906 <td valign="top">RESERVED0</td> 8907 <td valign="top" align="center">wo</td> 8908 <td valign="top" align="center">0x0</td> 8909 <td valign="top">Reserved</td> 8910 </tr> 8911 <tr> 8912 <td valign="top" align="center"><a name="1.9.3.2"></a>4:4 8913 </td> 8914 <td valign="top">SRAM_TO_DIN_CLEAR</td> 8915 <td valign="top" align="center">wo</td> 8916 <td valign="top" align="center">0x0</td> 8917 <td valign="top">The SRAM to DIN DMA done interrupt clear.</td> 8918 </tr> 8919 <tr> 8920 <td valign="top" align="center"><a name="1.9.3.3"></a>5:5 8921 </td> 8922 <td valign="top">DOUT_TO_SRAM_CLEAR</td> 8923 <td valign="top" align="center">wo</td> 8924 <td valign="top" align="center">0x0</td> 8925 <td valign="top">The DOUT to SRAM DMA done interrupt clear.</td> 8926 </tr> 8927 <tr> 8928 <td valign="top" align="center"><a name="1.9.3.4"></a>6:6 8929 </td> 8930 <td valign="top">MEM_TO_DIN_CLEAR</td> 8931 <td valign="top" align="center">wo</td> 8932 <td valign="top" align="center">0x0</td> 8933 <td valign="top">The memory to DIN DMA done interrupt clear.</td> 8934 </tr> 8935 <tr> 8936 <td valign="top" align="center"><a name="1.9.3.5"></a>7:7 8937 </td> 8938 <td valign="top">DOUT_TO_MEM_CLEAR</td> 8939 <td valign="top" align="center">wo</td> 8940 <td valign="top" align="center">0x0</td> 8941 <td valign="top">The DOUT to memory DMA done interrupt clear.</td> 8942 </tr> 8943 <tr> 8944 <td valign="top" align="center"><a name="1.9.3.6"></a>8:8 8945 </td> 8946 <td valign="top">AXI_ERR_CLEAR</td> 8947 <td valign="top" align="center">wo</td> 8948 <td valign="top" align="center">0x0</td> 8949 <td valign="top">The AXI error interrupt clear.</td> 8950 </tr> 8951 <tr> 8952 <td valign="top" align="center"><a name="1.9.3.7"></a>9:9 8953 </td> 8954 <td valign="top">PKA_EXP_CLEAR</td> 8955 <td valign="top" align="center">wo</td> 8956 <td valign="top" align="center">0x0</td> 8957 <td valign="top">The PKA end of operation interrupt clear.</td> 8958 </tr> 8959 <tr> 8960 <td valign="top" align="center"><a name="1.9.3.8"></a>10:10 8961 </td> 8962 <td valign="top">RNG_INT_CLEAR</td> 8963 <td valign="top" align="center">wo</td> 8964 <td valign="top" align="center">0x0</td> 8965 <td valign="top">The RNG interrupt clear.</td> 8966 </tr> 8967 <tr> 8968 <td valign="top" align="center"><a name="1.9.3.9"></a>11:11 8969 </td> 8970 <td valign="top">SYM_DMA_COMPLETED_CLEAR</td> 8971 <td valign="top" align="center">wo</td> 8972 <td valign="top" align="center">0x0</td> 8973 <td valign="top">The GPR interrupt clear.</td> 8974 </tr> 8975 <tr> 8976 <td valign="top" align="center"><a name="1.9.3.10"></a>31:12 8977 </td> 8978 <td valign="top">RESERVED2</td> 8979 <td valign="top" align="center">wo</td> 8980 <td valign="top" align="center">0x0</td> 8981 <td valign="top">Reserved</td> 8982 </tr> 8983</table><a name="1.9.4"></a><br>1.9.4 : <b>Reg : HOST_RGF_ENDIAN</b> : 0x000000A0C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines the endianness of the Host-accessible registers.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 8984 <tr> 8985 <td colspan="32" align="center">HOST_RGF_ENDIAN</td> 8986 </tr> 8987 <tr></tr> 8988</table> 8989<table border="1" width="800"> 8990 <tr> 8991 <td width="40"><b>bits</b></td> 8992 <td width="100"><b>Field name</b></td> 8993 <td width="20"><b>permission</b></td> 8994 <td width="40"><b>default</b></td> 8995 <td width="600"><b>Description</b></td> 8996 </tr> 8997 <tr> 8998 <td valign="top" align="center"><a name="1.9.4.1"></a>2:0 8999 </td> 9000 <td valign="top">RESERVED0</td> 9001 <td valign="top" align="center">rw1</td> 9002 <td valign="top" align="center">0x0</td> 9003 <td valign="top">Reserved</td> 9004 </tr> 9005 <tr> 9006 <td valign="top" align="center"><a name="1.9.4.2"></a>3:3 9007 </td> 9008 <td valign="top">DOUT_WR_BG</td> 9009 <td valign="top" align="center">rw1</td> 9010 <td valign="top" align="center">0x0</td> 9011 <td valign="top">DOUT write endianness:<br>@1'b0 - little endian <br>@1'b1 - big endian 9012 </td> 9013 </tr> 9014 <tr> 9015 <td valign="top" align="center"><a name="1.9.4.3"></a>6:4 9016 </td> 9017 <td valign="top">RESERVED1</td> 9018 <td valign="top" align="center">rw1</td> 9019 <td valign="top" align="center">0x0</td> 9020 <td valign="top">Reserved</td> 9021 </tr> 9022 <tr> 9023 <td valign="top" align="center"><a name="1.9.4.4"></a>7:7 9024 </td> 9025 <td valign="top">DIN_RD_BG</td> 9026 <td valign="top" align="center">rw1</td> 9027 <td valign="top" align="center">0x0</td> 9028 <td valign="top">DIN write endianness:<br>@1'b0 - little endian <br>@1'b1 - big endian 9029 </td> 9030 </tr> 9031 <tr> 9032 <td valign="top" align="center"><a name="1.9.4.5"></a>10:8 9033 </td> 9034 <td valign="top">RESERVED2</td> 9035 <td valign="top" align="center">rw1</td> 9036 <td valign="top" align="center">0x0</td> 9037 <td valign="top">Reserved</td> 9038 </tr> 9039 <tr> 9040 <td valign="top" align="center"><a name="1.9.4.6"></a>11:11 9041 </td> 9042 <td valign="top">DOUT_WR_WBG</td> 9043 <td valign="top" align="center">rw1</td> 9044 <td valign="top" align="center">0x0</td> 9045 <td valign="top">DOUT write word endianness:<br>@1'b0 - little endian <br>@1'b1 - big endian 9046 </td> 9047 </tr> 9048 <tr> 9049 <td valign="top" align="center"><a name="1.9.4.7"></a>14:12 9050 </td> 9051 <td valign="top">RESERVED3</td> 9052 <td valign="top" align="center">rw1</td> 9053 <td valign="top" align="center">0x0</td> 9054 <td valign="top">Reserved</td> 9055 </tr> 9056 <tr> 9057 <td valign="top" align="center"><a name="1.9.4.8"></a>15:15 9058 </td> 9059 <td valign="top">DIN_RD_WBG</td> 9060 <td valign="top" align="center">rw1</td> 9061 <td valign="top" align="center">0x0</td> 9062 <td valign="top">DIN write word endianness:<br>@1'b0 - little endian <br>@1'b1 - big endian 9063 </td> 9064 </tr> 9065 <tr> 9066 <td valign="top" align="center"><a name="1.9.4.9"></a>31:16 9067 </td> 9068 <td valign="top">RESERVED4</td> 9069 <td valign="top" align="center">rw1</td> 9070 <td valign="top" align="center">0x0</td> 9071 <td valign="top">Reserved</td> 9072 </tr> 9073</table><a name="1.9.5"></a><br>1.9.5 : <b>Reg : HOST_RGF_SIGNATURE</b> : 0x000000A24<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the CryptoCell product signature.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9074 <tr> 9075 <td colspan="32" align="center">HOST_RGF_SIGNATURE</td> 9076 </tr> 9077 <tr></tr> 9078</table> 9079<table border="1" width="800"> 9080 <tr> 9081 <td width="40"><b>bits</b></td> 9082 <td width="100"><b>Field name</b></td> 9083 <td width="20"><b>permission</b></td> 9084 <td width="40"><b>default</b></td> 9085 <td width="600"><b>Description</b></td> 9086 </tr> 9087 <tr> 9088 <td valign="top" align="center"><a name="1.9.5.1"></a>31:0 9089 </td> 9090 <td valign="top">HOST_SIGNATURE</td> 9091 <td valign="top" align="center">ro</td> 9092 <td valign="top" align="center">0x</td> 9093 <td valign="top">Identification “signature”: always returns a fixed value, used by Host driver to verify CryptoCell presence at this address.</td> 9094 </tr> 9095</table><a name="1.9.6"></a><br>1.9.6 : <b>Reg : HOST_BOOT</b> : 0x000000A28<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the values of CryptoCell's pre-synthesis flags<br><table border="1" bgcolor="#EEEEEE" width="800"> 9096 <tr> 9097 <td colspan="32" align="center">HOST_BOOT</td> 9098 </tr> 9099 <tr></tr> 9100</table> 9101<table border="1" width="800"> 9102 <tr> 9103 <td width="40"><b>bits</b></td> 9104 <td width="100"><b>Field name</b></td> 9105 <td width="20"><b>permission</b></td> 9106 <td width="40"><b>default</b></td> 9107 <td width="600"><b>Description</b></td> 9108 </tr> 9109 <tr> 9110 <td valign="top" align="center"><a name="1.9.6.1"></a>0:0 9111 </td> 9112 <td valign="top">SYNTHESIS_CONFIG</td> 9113 <td valign="top" align="center">ro</td> 9114 <td valign="top" align="center">0x0</td> 9115 <td valign="top">POWER_GATING_EXISTS_LOCAL</td> 9116 </tr> 9117 <tr> 9118 <td valign="top" align="center"><a name="1.9.6.2"></a>1:1 9119 </td> 9120 <td valign="top">LARGE_RKEK_LOCAL</td> 9121 <td valign="top" align="center">ro</td> 9122 <td valign="top" align="center">0x1</td> 9123 <td valign="top">LARGE_RKEK_LOCAL</td> 9124 </tr> 9125 <tr> 9126 <td valign="top" align="center"><a name="1.9.6.3"></a>2:2 9127 </td> 9128 <td valign="top">HASH_IN_FUSES_LOCAL</td> 9129 <td valign="top" align="center">ro</td> 9130 <td valign="top" align="center">0x1</td> 9131 <td valign="top">HASH_IN_FUSES_LOCAL</td> 9132 </tr> 9133 <tr> 9134 <td valign="top" align="center"><a name="1.9.6.4"></a>3:3 9135 </td> 9136 <td valign="top">EXT_MEM_SECURED_LOCAL</td> 9137 <td valign="top" align="center">ro</td> 9138 <td valign="top" align="center">0x1</td> 9139 <td valign="top">EXT_MEM_SECURED_LOCAL</td> 9140 </tr> 9141 <tr> 9142 <td valign="top" align="center"><a name="1.9.6.5"></a>4:4 9143 </td> 9144 <td valign="top">Reserved</td> 9145 <td valign="top" align="center">ro</td> 9146 <td valign="top" align="center">0x0</td> 9147 <td valign="top">Reserved</td> 9148 </tr> 9149 <tr> 9150 <td valign="top" align="center"><a name="1.9.6.6"></a>5:5 9151 </td> 9152 <td valign="top">RKEK_ECC_EXISTS_LOCAL_N</td> 9153 <td valign="top" align="center">ro</td> 9154 <td valign="top" align="center">0x1</td> 9155 <td valign="top">RKEK_ECC_EXISTS_LOCAL_N</td> 9156 </tr> 9157 <tr> 9158 <td valign="top" align="center"><a name="1.9.6.7"></a>8:6 9159 </td> 9160 <td valign="top">SRAM_SIZE_LOCAL</td> 9161 <td valign="top" align="center">ro</td> 9162 <td valign="top" align="center">0x0</td> 9163 <td valign="top">SRAM_SIZE_LOCAL</td> 9164 </tr> 9165 <tr> 9166 <td valign="top" align="center"><a name="1.9.6.8"></a>9:9 9167 </td> 9168 <td valign="top">DSCRPTR_EXISTS_LOCAL</td> 9169 <td valign="top" align="center">ro</td> 9170 <td valign="top" align="center">0x0</td> 9171 <td valign="top">DSCRPTR_EXISTS_LOCAL</td> 9172 </tr> 9173 <tr> 9174 <td valign="top" align="center"><a name="1.9.6.9"></a>10:10 9175 </td> 9176 <td valign="top">PAU_EXISTS_LOCAL</td> 9177 <td valign="top" align="center">ro</td> 9178 <td valign="top" align="center">0x0</td> 9179 <td valign="top">PAU_EXISTS_LOCAL</td> 9180 </tr> 9181 <tr> 9182 <td valign="top" align="center"><a name="1.9.6.10"></a>11:11 9183 </td> 9184 <td valign="top">RNG_EXISTS_LOCAL</td> 9185 <td valign="top" align="center">ro</td> 9186 <td valign="top" align="center">0x1</td> 9187 <td valign="top">RNG_EXISTS_LOCAL</td> 9188 </tr> 9189 <tr> 9190 <td valign="top" align="center"><a name="1.9.6.11"></a>12:12 9191 </td> 9192 <td valign="top">PKA_EXISTS_LOCAL</td> 9193 <td valign="top" align="center">ro</td> 9194 <td valign="top" align="center">0x1</td> 9195 <td valign="top">PKA_EXISTS_LOCAL</td> 9196 </tr> 9197 <tr> 9198 <td valign="top" align="center"><a name="1.9.6.12"></a>13:13 9199 </td> 9200 <td valign="top">RC4_EXISTS_LOCAL</td> 9201 <td valign="top" align="center">ro</td> 9202 <td valign="top" align="center">0x0</td> 9203 <td valign="top">RC4_EXISTS_LOCAL</td> 9204 </tr> 9205 <tr> 9206 <td valign="top" align="center"><a name="1.9.6.13"></a>14:14 9207 </td> 9208 <td valign="top">SHA_512_PRSNT_LOCAL</td> 9209 <td valign="top" align="center">ro</td> 9210 <td valign="top" align="center">0x0</td> 9211 <td valign="top">SHA_512_PRSNT_LOCAL</td> 9212 </tr> 9213 <tr> 9214 <td valign="top" align="center"><a name="1.9.6.14"></a>15:15 9215 </td> 9216 <td valign="top">SHA_256_PRSNT_LOCAL</td> 9217 <td valign="top" align="center">ro</td> 9218 <td valign="top" align="center">0x1</td> 9219 <td valign="top">SHA_256_PRSNT_LOCAL</td> 9220 </tr> 9221 <tr> 9222 <td valign="top" align="center"><a name="1.9.6.15"></a>16:16 9223 </td> 9224 <td valign="top">MD5_PRSNT_LOCAL</td> 9225 <td valign="top" align="center">ro</td> 9226 <td valign="top" align="center">0x0</td> 9227 <td valign="top">MD5_PRSNT_LOCAL</td> 9228 </tr> 9229 <tr> 9230 <td valign="top" align="center"><a name="1.9.6.16"></a>17:17 9231 </td> 9232 <td valign="top">HASH_EXISTS_LOCAL</td> 9233 <td valign="top" align="center">ro</td> 9234 <td valign="top" align="center">0x1</td> 9235 <td valign="top">HASH_EXISTS_LOCAL</td> 9236 </tr> 9237 <tr> 9238 <td valign="top" align="center"><a name="1.9.6.17"></a>18:18 9239 </td> 9240 <td valign="top">C2_EXISTS_LOCAL</td> 9241 <td valign="top" align="center">ro</td> 9242 <td valign="top" align="center">0x0</td> 9243 <td valign="top">C2_EXISTS_LOCAL</td> 9244 </tr> 9245 <tr> 9246 <td valign="top" align="center"><a name="1.9.6.18"></a>19:19 9247 </td> 9248 <td valign="top">DES_EXISTS_LOCAL</td> 9249 <td valign="top" align="center">ro</td> 9250 <td valign="top" align="center">0x0</td> 9251 <td valign="top">DES_EXISTS_LOCAL</td> 9252 </tr> 9253 <tr> 9254 <td valign="top" align="center"><a name="1.9.6.19"></a>20:20 9255 </td> 9256 <td valign="top">AES_XCBC_MAC_EXISTS_LOCAL</td> 9257 <td valign="top" align="center">ro</td> 9258 <td valign="top" align="center">0x0</td> 9259 <td valign="top">AES_XCBC_MAC_EXISTS_LOCAL</td> 9260 </tr> 9261 <tr> 9262 <td valign="top" align="center"><a name="1.9.6.20"></a>21:21 9263 </td> 9264 <td valign="top">AES_CMAC_EXISTS_LOCAL</td> 9265 <td valign="top" align="center">ro</td> 9266 <td valign="top" align="center">0x1</td> 9267 <td valign="top">AES_CMAC_EXISTS_LOCAL</td> 9268 </tr> 9269 <tr> 9270 <td valign="top" align="center"><a name="1.9.6.21"></a>22:22 9271 </td> 9272 <td valign="top">AES_CCM_EXISTS_LOCAL</td> 9273 <td valign="top" align="center">ro</td> 9274 <td valign="top" align="center">0x1</td> 9275 <td valign="top">AES_CCM_EXISTS_LOCAL</td> 9276 </tr> 9277 <tr> 9278 <td valign="top" align="center"><a name="1.9.6.22"></a>23:23 9279 </td> 9280 <td valign="top">AES_XEX_HW_T_CALC_LOCAL</td> 9281 <td valign="top" align="center">ro</td> 9282 <td valign="top" align="center">0x0</td> 9283 <td valign="top">AES_XEX_HW_T_CALC_LOCAL</td> 9284 </tr> 9285 <tr> 9286 <td valign="top" align="center"><a name="1.9.6.23"></a>24:24 9287 </td> 9288 <td valign="top">AES_XEX_EXISTS_LOCAL</td> 9289 <td valign="top" align="center">ro</td> 9290 <td valign="top" align="center">0x0</td> 9291 <td valign="top">AES_XEX_EXISTS_LOCAL</td> 9292 </tr> 9293 <tr> 9294 <td valign="top" align="center"><a name="1.9.6.24"></a>25:25 9295 </td> 9296 <td valign="top">CTR_EXISTS_LOCAL</td> 9297 <td valign="top" align="center">ro</td> 9298 <td valign="top" align="center">0x1</td> 9299 <td valign="top">CTR_EXISTS_LOCAL</td> 9300 </tr> 9301 <tr> 9302 <td valign="top" align="center"><a name="1.9.6.25"></a>26:26 9303 </td> 9304 <td valign="top">AES_DIN_BYTE_RESOLUTION_LOCAL</td> 9305 <td valign="top" align="center">ro</td> 9306 <td valign="top" align="center">0x1</td> 9307 <td valign="top">AES_DIN_BYTE_RESOLUTION_LOCAL</td> 9308 </tr> 9309 <tr> 9310 <td valign="top" align="center"><a name="1.9.6.26"></a>27:27 9311 </td> 9312 <td valign="top">TUNNELING_ENB_LOCAL</td> 9313 <td valign="top" align="center">ro</td> 9314 <td valign="top" align="center">0x1</td> 9315 <td valign="top">TUNNELING_ENB_LOCAL</td> 9316 </tr> 9317 <tr> 9318 <td valign="top" align="center"><a name="1.9.6.27"></a>28:28 9319 </td> 9320 <td valign="top">SUPPORT_256_192_KEY_LOCAL</td> 9321 <td valign="top" align="center">ro</td> 9322 <td valign="top" align="center">0x1</td> 9323 <td valign="top">SUPPORT_256_192_KEY_LOCAL</td> 9324 </tr> 9325 <tr> 9326 <td valign="top" align="center"><a name="1.9.6.28"></a>29:29 9327 </td> 9328 <td valign="top">ONLY_ENCRYPT_LOCAL</td> 9329 <td valign="top" align="center">ro</td> 9330 <td valign="top" align="center">0x0</td> 9331 <td valign="top">ONLY_ENCRYPT_LOCAL</td> 9332 </tr> 9333 <tr> 9334 <td valign="top" align="center"><a name="1.9.6.29"></a>30:30 9335 </td> 9336 <td valign="top">AES_EXISTS_LOCAL</td> 9337 <td valign="top" align="center">ro</td> 9338 <td valign="top" align="center">0x1</td> 9339 <td valign="top">AES_EXISTS_LOCAL</td> 9340 </tr> 9341 <tr> 9342 <td valign="top" align="center"><a name="1.9.6.30"></a>31:31 9343 </td> 9344 <td valign="top">RESERVED</td> 9345 <td valign="top" align="center">ro</td> 9346 <td valign="top" align="center">0x0</td> 9347 <td valign="top">Reserved</td> 9348 </tr> 9349</table><a name="1.9.7"></a><br>1.9.7 : <b>Reg : HOST_CRYPTOKEY_SEL</b> : 0x000000A38<br><b>reg sep address</b> : <b> reg host address</b> : <br>AES hardware key select.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9350 <tr> 9351 <td colspan="32" align="center">HOST_CRYPTOKEY_SEL</td> 9352 </tr> 9353 <tr></tr> 9354</table> 9355<table border="1" width="800"> 9356 <tr> 9357 <td width="40"><b>bits</b></td> 9358 <td width="100"><b>Field name</b></td> 9359 <td width="20"><b>permission</b></td> 9360 <td width="40"><b>default</b></td> 9361 <td width="600"><b>Description</b></td> 9362 </tr> 9363 <tr> 9364 <td valign="top" align="center"><a name="1.9.7.1"></a>2:0 9365 </td> 9366 <td valign="top">SEL_CRYPTO_KEY</td> 9367 <td valign="top" align="center">rw</td> 9368 <td valign="top" align="center">0x0</td> 9369 <td valign="top">Select the source of the HW key that is used by the AES engine: <br>@3'h0 - RKEK<br>@3'h1 -the Krtl.<br>@3'h2 - the provision key KCP.<br>@3'h3 - the code encryption key KCE. <br>@3'h4 - the KPICV, The ICV provisioning key .<br>@3'h5 - the code encryption key KCEICV<br>NOTE:<br>When "kprtl_lock" is set - kprtl will be masked (trying to load it will load zeros to the AES key register.<br>When "kcertl_lock" is set - kcertl will be masked (trying to load it will load zeros to the AES key register.<br>When scan_mode is asserted – all the RTL keys (Krtll) will be masked. 9370 </td> 9371 </tr> 9372 <tr> 9373 <td valign="top" align="center"><a name="1.9.7.2"></a>31:3 9374 </td> 9375 <td valign="top">RESERVED</td> 9376 <td valign="top" align="center">rw</td> 9377 <td valign="top" align="center">0x0</td> 9378 <td valign="top">Reserved</td> 9379 </tr> 9380</table><a name="1.9.8"></a><br>1.9.8 : <b>Reg : HOST_CORE_CLK_GATING_ENABLE</b> : 0x000000A78<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register enables the core clk gating by masking/enabling the cc_idle_state output signal.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9381 <tr> 9382 <td colspan="32" align="center">HOST_CORE_CLK_GATING_ENABLE</td> 9383 </tr> 9384 <tr></tr> 9385</table> 9386<table border="1" width="800"> 9387 <tr> 9388 <td width="40"><b>bits</b></td> 9389 <td width="100"><b>Field name</b></td> 9390 <td width="20"><b>permission</b></td> 9391 <td width="40"><b>default</b></td> 9392 <td width="600"><b>Description</b></td> 9393 </tr> 9394 <tr> 9395 <td valign="top" align="center"><a name="1.9.8.1"></a>0:0 9396 </td> 9397 <td valign="top">HOST_CORE_CLK_GATING_ENABLE</td> 9398 <td valign="top" align="center">rw</td> 9399 <td valign="top" align="center">0x0</td> 9400 <td valign="top">Enable the core clk gating,</td> 9401 </tr> 9402 <tr> 9403 <td valign="top" align="center"><a name="1.9.8.2"></a>31:1 9404 </td> 9405 <td valign="top">RESERVED</td> 9406 <td valign="top" align="center">rw</td> 9407 <td valign="top" align="center">0x0</td> 9408 <td valign="top">Reserved<br>Note: This is a special register, this registers 9409 </td> 9410 </tr> 9411</table><a name="1.9.9"></a><br>1.9.9 : <b>Reg : HOST_CC_IS_IDLE</b> : 0x000000A7C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the idle indication of CC . Note: This is a special register, affected by internal logic. Test result 9412of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9413 <tr> 9414 <td colspan="32" align="center">HOST_CC_IS_IDLE</td> 9415 </tr> 9416 <tr></tr> 9417</table> 9418<table border="1" width="800"> 9419 <tr> 9420 <td width="40"><b>bits</b></td> 9421 <td width="100"><b>Field name</b></td> 9422 <td width="20"><b>permission</b></td> 9423 <td width="40"><b>default</b></td> 9424 <td width="600"><b>Description</b></td> 9425 </tr> 9426 <tr> 9427 <td valign="top" align="center"><a name="1.9.9.1"></a>0:0 9428 </td> 9429 <td valign="top">HOST_CC_IS_IDLE</td> 9430 <td valign="top" align="center">ro</td> 9431 <td valign="top" align="center">0x0</td> 9432 <td valign="top">Read if CC is idle.</td> 9433 </tr> 9434 <tr> 9435 <td valign="top" align="center"><a name="1.9.9.2"></a>1:1 9436 </td> 9437 <td valign="top">HOST_CC_IS_IDLE_EVENT</td> 9438 <td valign="top" align="center">ro</td> 9439 <td valign="top" align="center">0x0</td> 9440 <td valign="top">The event that indicates that CC is idle.</td> 9441 </tr> 9442 <tr> 9443 <td valign="top" align="center"><a name="1.9.9.3"></a>2:2 9444 </td> 9445 <td valign="top">SYM_IS_BUSY</td> 9446 <td valign="top" align="center">ro</td> 9447 <td valign="top" align="center">0x0</td> 9448 <td valign="top">symetric flow is busy</td> 9449 </tr> 9450 <tr> 9451 <td valign="top" align="center"><a name="1.9.9.4"></a>3:3 9452 </td> 9453 <td valign="top">AHB_IS_IDLE</td> 9454 <td valign="top" align="center">ro</td> 9455 <td valign="top" align="center">0x0</td> 9456 <td valign="top">ahb stste machine is idle</td> 9457 </tr> 9458 <tr> 9459 <td valign="top" align="center"><a name="1.9.9.5"></a>4:4 9460 </td> 9461 <td valign="top">NVM_ARB_IS_IDLE</td> 9462 <td valign="top" align="center">ro</td> 9463 <td valign="top" align="center">0x0</td> 9464 <td valign="top">nvm arbiter is idle</td> 9465 </tr> 9466 <tr> 9467 <td valign="top" align="center"><a name="1.9.9.6"></a>5:5 9468 </td> 9469 <td valign="top">NVM_IS_IDLE</td> 9470 <td valign="top" align="center">ro</td> 9471 <td valign="top" align="center">0x0</td> 9472 <td valign="top">nvm is idle</td> 9473 </tr> 9474 <tr> 9475 <td valign="top" align="center"><a name="1.9.9.7"></a>6:6 9476 </td> 9477 <td valign="top">FATAL_WR</td> 9478 <td valign="top" align="center">ro</td> 9479 <td valign="top" align="center">0x0</td> 9480 <td valign="top">fatal write</td> 9481 </tr> 9482 <tr> 9483 <td valign="top" align="center"><a name="1.9.9.8"></a>7:7 9484 </td> 9485 <td valign="top">RNG_IS_IDLE</td> 9486 <td valign="top" align="center">ro</td> 9487 <td valign="top" align="center">0x0</td> 9488 <td valign="top">rng is idle</td> 9489 </tr> 9490 <tr> 9491 <td valign="top" align="center"><a name="1.9.9.9"></a>8:8 9492 </td> 9493 <td valign="top">PKA_IS_IDLE</td> 9494 <td valign="top" align="center">ro</td> 9495 <td valign="top" align="center">0x0</td> 9496 <td valign="top">pka is idle</td> 9497 </tr> 9498 <tr> 9499 <td valign="top" align="center"><a name="1.9.9.10"></a>9:9 9500 </td> 9501 <td valign="top">CRYPTO_IS_IDLE</td> 9502 <td valign="top" align="center">ro</td> 9503 <td valign="top" align="center">0x0</td> 9504 <td valign="top">crypto flow is done</td> 9505 </tr> 9506 <tr> 9507 <td valign="top" align="center"><a name="1.9.9.11"></a>31:10 9508 </td> 9509 <td valign="top">RESERVED</td> 9510 <td valign="top" align="center">ro</td> 9511 <td valign="top" align="center">0x0</td> 9512 <td valign="top">Reserved<br>Note: This is a special register, this registers 9513 </td> 9514 </tr> 9515</table><a name="1.9.10"></a><br>1.9.10 : <b>Reg : HOST_POWERDOWN</b> : 0x000000A80<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register start the power-down sequence.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9516 <tr> 9517 <td colspan="32" align="center">HOST_POWERDOWN</td> 9518 </tr> 9519 <tr></tr> 9520</table> 9521<table border="1" width="800"> 9522 <tr> 9523 <td width="40"><b>bits</b></td> 9524 <td width="100"><b>Field name</b></td> 9525 <td width="20"><b>permission</b></td> 9526 <td width="40"><b>default</b></td> 9527 <td width="600"><b>Description</b></td> 9528 </tr> 9529 <tr> 9530 <td valign="top" align="center"><a name="1.9.10.1"></a>0:0 9531 </td> 9532 <td valign="top">HOST_POWERDOWN</td> 9533 <td valign="top" align="center">rw</td> 9534 <td valign="top" align="center">0x0</td> 9535 <td valign="top">Power down enable register.</td> 9536 </tr> 9537 <tr> 9538 <td valign="top" align="center"><a name="1.9.10.2"></a>31:1 9539 </td> 9540 <td valign="top">RESERVED</td> 9541 <td valign="top" align="center">rw</td> 9542 <td valign="top" align="center">0x0</td> 9543 <td valign="top">Reserved<br>Note: This is a special register, this registers 9544 </td> 9545 </tr> 9546</table><a name="1.9.11"></a><br>1.9.11 : <b>Reg : HOST_REMOVE_GHASH_ENGINE</b> : 0x000000A84<br><b>reg sep address</b> : <b> reg host address</b> : <br>These inputs are to be statically tied to 0 or 1 by the customers. When such an input is set, the matching engines inputs 9547are tied to zero and its outputs are disconnected, so that the engine will be entirely removed by Synthesis<br><table border="1" bgcolor="#EEEEEE" width="800"> 9548 <tr> 9549 <td colspan="32" align="center">HOST_REMOVE_GHASH_ENGINE</td> 9550 </tr> 9551 <tr></tr> 9552</table> 9553<table border="1" width="800"> 9554 <tr> 9555 <td width="40"><b>bits</b></td> 9556 <td width="100"><b>Field name</b></td> 9557 <td width="20"><b>permission</b></td> 9558 <td width="40"><b>default</b></td> 9559 <td width="600"><b>Description</b></td> 9560 </tr> 9561 <tr> 9562 <td valign="top" align="center"><a name="1.9.11.1"></a>0:0 9563 </td> 9564 <td valign="top">HOST_REMOVE_GHASH_ENGINE</td> 9565 <td valign="top" align="center">ro</td> 9566 <td valign="top" align="center">0x0</td> 9567 <td valign="top">Read the Remove_chacha_engine input</td> 9568 </tr> 9569 <tr> 9570 <td valign="top" align="center"><a name="1.9.11.2"></a>31:1 9571 </td> 9572 <td valign="top">RESERVED</td> 9573 <td valign="top" align="center">ro</td> 9574 <td valign="top" align="center">0x0</td> 9575 <td valign="top">Reserved<br>Note: This is a special register, this registers 9576 </td> 9577 </tr> 9578</table><a name="1.9.12"></a><br>1.9.12 : <b>Reg : HOST_REMOVE_CHACHA_ENGINE</b> : 0x000000A88<br><b>reg sep address</b> : <b> reg host address</b> : <br>These inputs are to be statically tied to 0 or 1 by the customers. When such an input is set, the matching engines inputs 9579are tied to zero and its outputs are disconnected, so that the engine will be entirely removed by Synthesis<br><table border="1" bgcolor="#EEEEEE" width="800"> 9580 <tr> 9581 <td colspan="32" align="center">HOST_REMOVE_CHACHA_ENGINE</td> 9582 </tr> 9583 <tr></tr> 9584</table> 9585<table border="1" width="800"> 9586 <tr> 9587 <td width="40"><b>bits</b></td> 9588 <td width="100"><b>Field name</b></td> 9589 <td width="20"><b>permission</b></td> 9590 <td width="40"><b>default</b></td> 9591 <td width="600"><b>Description</b></td> 9592 </tr> 9593 <tr> 9594 <td valign="top" align="center"><a name="1.9.12.1"></a>0:0 9595 </td> 9596 <td valign="top">HOST_REMOVE_CHACHA_ENGINE</td> 9597 <td valign="top" align="center">ro</td> 9598 <td valign="top" align="center">0x0</td> 9599 <td valign="top">Read the Remove_ghash_engine input</td> 9600 </tr> 9601 <tr> 9602 <td valign="top" align="center"><a name="1.9.12.2"></a>31:1 9603 </td> 9604 <td valign="top">RESERVED</td> 9605 <td valign="top" align="center">ro</td> 9606 <td valign="top" align="center">0x0</td> 9607 <td valign="top">Reserved<br>Note: This is a special register, this registers 9608 </td> 9609 </tr> 9610</table><a href="#1.9">(top of block)</a><a name="1.10"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 9611 <td><b><font color="#000000">1.10 : Block: AHB</font></b></td> 9612 <td align="right"><font color="#000000">0x000000B00</font></td> 9613</table><br><a name="1.10.1"></a><br>1.10.1 : <b>Reg : AHBM_SINGLES</b> : 0x000000B00<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register forces the ahb transactions to be always singles.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9614 <tr> 9615 <td colspan="32" align="center">AHBM_SINGLES</td> 9616 </tr> 9617 <tr></tr> 9618</table> 9619<table border="1" width="800"> 9620 <tr> 9621 <td width="40"><b>bits</b></td> 9622 <td width="100"><b>Field name</b></td> 9623 <td width="20"><b>permission</b></td> 9624 <td width="40"><b>default</b></td> 9625 <td width="600"><b>Description</b></td> 9626 </tr> 9627 <tr> 9628 <td valign="top" align="center"><a name="1.10.1.1"></a>0:0 9629 </td> 9630 <td valign="top">AHB_SINGLES</td> 9631 <td valign="top" align="center">rw</td> 9632 <td valign="top" align="center">0x0</td> 9633 <td valign="top">Force ahb singles</td> 9634 </tr> 9635 <tr> 9636 <td valign="top" align="center"><a name="1.10.1.2"></a>31:1 9637 </td> 9638 <td valign="top">RESERVED</td> 9639 <td valign="top" align="center">rw</td> 9640 <td valign="top" align="center">0x0</td> 9641 <td valign="top">Reserved</td> 9642 </tr> 9643</table><a name="1.10.2"></a><br>1.10.2 : <b>Reg : AHBM_HPROT</b> : 0x000000B04<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the ahb prot value<br><table border="1" bgcolor="#EEEEEE" width="800"> 9644 <tr> 9645 <td colspan="32" align="center">AHBM_HPROT</td> 9646 </tr> 9647 <tr></tr> 9648</table> 9649<table border="1" width="800"> 9650 <tr> 9651 <td width="40"><b>bits</b></td> 9652 <td width="100"><b>Field name</b></td> 9653 <td width="20"><b>permission</b></td> 9654 <td width="40"><b>default</b></td> 9655 <td width="600"><b>Description</b></td> 9656 </tr> 9657 <tr> 9658 <td valign="top" align="center"><a name="1.10.2.1"></a>3:0 9659 </td> 9660 <td valign="top">AHB_PROT</td> 9661 <td valign="top" align="center">rw</td> 9662 <td valign="top" align="center">0x0</td> 9663 <td valign="top">The ahb prot value</td> 9664 </tr> 9665 <tr> 9666 <td valign="top" align="center"><a name="1.10.2.2"></a>31:4 9667 </td> 9668 <td valign="top">RESERVED</td> 9669 <td valign="top" align="center">rw</td> 9670 <td valign="top" align="center">0x0</td> 9671 <td valign="top">Reserved</td> 9672 </tr> 9673</table><a name="1.10.3"></a><br>1.10.3 : <b>Reg : AHBM_HMASTLOCK</b> : 0x000000B08<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds ahb hmastlock value<br><table border="1" bgcolor="#EEEEEE" width="800"> 9674 <tr> 9675 <td colspan="32" align="center">AHBM_HMASTLOCK</td> 9676 </tr> 9677 <tr></tr> 9678</table> 9679<table border="1" width="800"> 9680 <tr> 9681 <td width="40"><b>bits</b></td> 9682 <td width="100"><b>Field name</b></td> 9683 <td width="20"><b>permission</b></td> 9684 <td width="40"><b>default</b></td> 9685 <td width="600"><b>Description</b></td> 9686 </tr> 9687 <tr> 9688 <td valign="top" align="center"><a name="1.10.3.1"></a>0:0 9689 </td> 9690 <td valign="top">AHB_HMASTLOCK</td> 9691 <td valign="top" align="center">rw</td> 9692 <td valign="top" align="center">0x0</td> 9693 <td valign="top">The hmastlock value.</td> 9694 </tr> 9695 <tr> 9696 <td valign="top" align="center"><a name="1.10.3.2"></a>31:1 9697 </td> 9698 <td valign="top">RESERVED</td> 9699 <td valign="top" align="center">rw</td> 9700 <td valign="top" align="center">0x0</td> 9701 <td valign="top">Reserved</td> 9702 </tr> 9703</table><a name="1.10.4"></a><br>1.10.4 : <b>Reg : AHBM_HNONSEC</b> : 0x000000B0C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds ahb hnonsec value<br><table border="1" bgcolor="#EEEEEE" width="800"> 9704 <tr> 9705 <td colspan="32" align="center">AHBM_HNONSEC</td> 9706 </tr> 9707 <tr></tr> 9708</table> 9709<table border="1" width="800"> 9710 <tr> 9711 <td width="40"><b>bits</b></td> 9712 <td width="100"><b>Field name</b></td> 9713 <td width="20"><b>permission</b></td> 9714 <td width="40"><b>default</b></td> 9715 <td width="600"><b>Description</b></td> 9716 </tr> 9717 <tr> 9718 <td valign="top" align="center"><a name="1.10.4.1"></a>0:0 9719 </td> 9720 <td valign="top">AHB_WRITE_HNONSEC</td> 9721 <td valign="top" align="center">rw</td> 9722 <td valign="top" align="center">0x0</td> 9723 <td valign="top">The hnonsec value for write transaction.</td> 9724 </tr> 9725 <tr> 9726 <td valign="top" align="center"><a name="1.10.4.2"></a>1:1 9727 </td> 9728 <td valign="top">AHB_READ_HNONSEC</td> 9729 <td valign="top" align="center">rw</td> 9730 <td valign="top" align="center">0x0</td> 9731 <td valign="top">The hnonsec value for read transaction.</td> 9732 </tr> 9733 <tr> 9734 <td valign="top" align="center"><a name="1.10.4.3"></a>31:2 9735 </td> 9736 <td valign="top">RESERVED</td> 9737 <td valign="top" align="center">rw</td> 9738 <td valign="top" align="center">0x0</td> 9739 <td valign="top">Reserved</td> 9740 </tr> 9741</table><a href="#1.10">(top of block)</a><a name="1.11"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 9742 <td><b><font color="#000000">1.11 : Block: DIN</font></b></td> 9743 <td align="right"><font color="#000000">0x000000C00</font></td> 9744</table><br><a name="1.11.1"></a><br>1.11.1 : <b>Reg : DIN_BUFFER</b> : 0x000000C00<br><b>reg sep address</b> : <b> reg host address</b> : <br>This address can be used by the CPU to write data directly to the DIN buffer to be sent to engines.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9745 <tr> 9746 <td colspan="32" align="center">DIN_BUFFER</td> 9747 </tr> 9748 <tr></tr> 9749</table> 9750<table border="1" width="800"> 9751 <tr> 9752 <td width="40"><b>bits</b></td> 9753 <td width="100"><b>Field name</b></td> 9754 <td width="20"><b>permission</b></td> 9755 <td width="40"><b>default</b></td> 9756 <td width="600"><b>Description</b></td> 9757 </tr> 9758 <tr> 9759 <td valign="top" align="center"><a name="1.11.1.1"></a>31:0 9760 </td> 9761 <td valign="top">DIN_BUFFER_DATA</td> 9762 <td valign="top" align="center">wo</td> 9763 <td valign="top" align="center">0x0</td> 9764 <td valign="top">This register is mapped into 8 addresses in order to enable a CPU burst.</td> 9765 </tr> 9766</table><a name="1.11.2"></a><br>1.11.2 : <b>Reg : DIN_MEM_DMA_BUSY</b> : 0x000000C20<br><b>reg sep address</b> : <b> reg host address</b> : <br>Indicates whether memory (AXI) source DMA (DIN) is busy.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9767 <tr> 9768 <td colspan="32" align="center">DIN_MEM_DMA_BUSY</td> 9769 </tr> 9770 <tr></tr> 9771</table> 9772<table border="1" width="800"> 9773 <tr> 9774 <td width="40"><b>bits</b></td> 9775 <td width="100"><b>Field name</b></td> 9776 <td width="20"><b>permission</b></td> 9777 <td width="40"><b>default</b></td> 9778 <td width="600"><b>Description</b></td> 9779 </tr> 9780 <tr> 9781 <td valign="top" align="center"><a name="1.11.2.1"></a>0:0 9782 </td> 9783 <td valign="top">DIN_MEM_DMA_BUSY</td> 9784 <td valign="top" align="center">ro</td> 9785 <td valign="top" align="center">0x0</td> 9786 <td valign="top">DIN memory DMA busy:<br>@1'b1 - busy<br>@1'b0 - not busy 9787 </td> 9788 </tr> 9789 <tr> 9790 <td valign="top" align="center"><a name="1.11.2.2"></a>31:1 9791 </td> 9792 <td valign="top">RESERVED</td> 9793 <td valign="top" align="center">ro</td> 9794 <td valign="top" align="center">0x0</td> 9795 <td valign="top">Reserved</td> 9796 </tr> 9797</table><a name="1.11.3"></a><br>1.11.3 : <b>Reg : SRC_LLI_WORD0</b> : 0x000000C28<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is used in direct LLI mode - holds the location of the data source in the memory (AXI).<br><table border="1" bgcolor="#EEEEEE" width="800"> 9798 <tr> 9799 <td colspan="32" align="center">SRC_LLI_WORD0</td> 9800 </tr> 9801 <tr></tr> 9802</table> 9803<table border="1" width="800"> 9804 <tr> 9805 <td width="40"><b>bits</b></td> 9806 <td width="100"><b>Field name</b></td> 9807 <td width="20"><b>permission</b></td> 9808 <td width="40"><b>default</b></td> 9809 <td width="600"><b>Description</b></td> 9810 </tr> 9811 <tr> 9812 <td valign="top" align="center"><a name="1.11.3.1"></a>31:0 9813 </td> 9814 <td valign="top">SRC_LLI_WORD0</td> 9815 <td valign="top" align="center">wo</td> 9816 <td valign="top" align="center">0x0</td> 9817 <td valign="top">Source address within memory.</td> 9818 </tr> 9819</table><a name="1.11.4"></a><br>1.11.4 : <b>Reg : SRC_LLI_WORD1</b> : 0x000000C2C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is used in direct LLI mode - holds the number of bytes to be read from the memory (AXI). Writing to this register 9820triggers the DMA.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9821 <tr> 9822 <td colspan="32" align="center">SRC_LLI_WORD1</td> 9823 </tr> 9824 <tr></tr> 9825</table> 9826<table border="1" width="800"> 9827 <tr> 9828 <td width="40"><b>bits</b></td> 9829 <td width="100"><b>Field name</b></td> 9830 <td width="20"><b>permission</b></td> 9831 <td width="40"><b>default</b></td> 9832 <td width="600"><b>Description</b></td> 9833 </tr> 9834 <tr> 9835 <td valign="top" align="center"><a name="1.11.4.1"></a>29:0 9836 </td> 9837 <td valign="top">BYTES_NUM</td> 9838 <td valign="top" align="center">wo</td> 9839 <td valign="top" align="center">0x0</td> 9840 <td valign="top">Total number of bytes to read using DMA in this entry</td> 9841 </tr> 9842 <tr> 9843 <td valign="top" align="center"><a name="1.11.4.2"></a>30:30 9844 </td> 9845 <td valign="top">FIRST</td> 9846 <td valign="top" align="center">wo</td> 9847 <td valign="top" align="center">0x0</td> 9848 <td valign="top">1'b1 - Indicates the first LLI entry</td> 9849 </tr> 9850 <tr> 9851 <td valign="top" align="center"><a name="1.11.4.3"></a>31:31 9852 </td> 9853 <td valign="top">LAST</td> 9854 <td valign="top" align="center">wo</td> 9855 <td valign="top" align="center">0x0</td> 9856 <td valign="top">1'b1 - Indicates the last LLI entry</td> 9857 </tr> 9858</table><a name="1.11.5"></a><br>1.11.5 : <b>Reg : SRAM_SRC_ADDR</b> : 0x000000C30<br><b>reg sep address</b> : <b> reg host address</b> : <br>Location of data (start address) to be read from SRAM.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9859 <tr> 9860 <td colspan="32" align="center">SRAM_SRC_ADDR</td> 9861 </tr> 9862 <tr></tr> 9863</table> 9864<table border="1" width="800"> 9865 <tr> 9866 <td width="40"><b>bits</b></td> 9867 <td width="100"><b>Field name</b></td> 9868 <td width="20"><b>permission</b></td> 9869 <td width="40"><b>default</b></td> 9870 <td width="600"><b>Description</b></td> 9871 </tr> 9872 <tr> 9873 <td valign="top" align="center"><a name="1.11.5.1"></a>31:0 9874 </td> 9875 <td valign="top">SRAM_SOURCE</td> 9876 <td valign="top" align="center">rw</td> 9877 <td valign="top" align="center">0x0</td> 9878 <td valign="top">SRAM source base address of data</td> 9879 </tr> 9880</table><a name="1.11.6"></a><br>1.11.6 : <b>Reg : DIN_SRAM_BYTES_LEN</b> : 0x000000C34<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the size of the data (in bytes) to be read from the SRAM.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9881 <tr> 9882 <td colspan="32" align="center">DIN_SRAM_BYTES_LEN</td> 9883 </tr> 9884 <tr></tr> 9885</table> 9886<table border="1" width="800"> 9887 <tr> 9888 <td width="40"><b>bits</b></td> 9889 <td width="100"><b>Field name</b></td> 9890 <td width="20"><b>permission</b></td> 9891 <td width="40"><b>default</b></td> 9892 <td width="600"><b>Description</b></td> 9893 </tr> 9894 <tr> 9895 <td valign="top" align="center"><a name="1.11.6.1"></a>31:0 9896 </td> 9897 <td valign="top">BYTES_LEN</td> 9898 <td valign="top" align="center">r/wc</td> 9899 <td valign="top" align="center">0x0</td> 9900 <td valign="top">Size of data to read from SRAM (bytes). This is the trigger to the SRAM SRC DMA.</td> 9901 </tr> 9902</table><a name="1.11.7"></a><br>1.11.7 : <b>Reg : DIN_SRAM_DMA_BUSY</b> : 0x000000C38<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the status of the SRAM DMA DIN.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9903 <tr> 9904 <td colspan="32" align="center">DIN_SRAM_DMA_BUSY</td> 9905 </tr> 9906 <tr></tr> 9907</table> 9908<table border="1" width="800"> 9909 <tr> 9910 <td width="40"><b>bits</b></td> 9911 <td width="100"><b>Field name</b></td> 9912 <td width="20"><b>permission</b></td> 9913 <td width="40"><b>default</b></td> 9914 <td width="600"><b>Description</b></td> 9915 </tr> 9916 <tr> 9917 <td valign="top" align="center"><a name="1.11.7.1"></a>0:0 9918 </td> 9919 <td valign="top">BUSY</td> 9920 <td valign="top" align="center">ro</td> 9921 <td valign="top" align="center">0x0</td> 9922 <td valign="top">DIN SRAM DMA busy:<br>@1'b1 - busy<br>@1'b0 - not busy 9923 </td> 9924 </tr> 9925 <tr> 9926 <td valign="top" align="center"><a name="1.11.7.2"></a>31:1 9927 </td> 9928 <td valign="top">RESERVED</td> 9929 <td valign="top" align="center">ro</td> 9930 <td valign="top" align="center">0x0</td> 9931 <td valign="top">Reserved</td> 9932 </tr> 9933</table><a name="1.11.8"></a><br>1.11.8 : <b>Reg : DIN_SRAM_ENDIANNESS</b> : 0x000000C3C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines the endianness of the DIN interface to SRAM.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9934 <tr> 9935 <td colspan="32" align="center">DIN_SRAM_ENDIANNESS</td> 9936 </tr> 9937 <tr></tr> 9938</table> 9939<table border="1" width="800"> 9940 <tr> 9941 <td width="40"><b>bits</b></td> 9942 <td width="100"><b>Field name</b></td> 9943 <td width="20"><b>permission</b></td> 9944 <td width="40"><b>default</b></td> 9945 <td width="600"><b>Description</b></td> 9946 </tr> 9947 <tr> 9948 <td valign="top" align="center"><a name="1.11.8.1"></a>0:0 9949 </td> 9950 <td valign="top">SRAM_DIN_ENDIANNESS</td> 9951 <td valign="top" align="center">rw</td> 9952 <td valign="top" align="center">0x0</td> 9953 <td valign="top">Defines the endianness of DIN interface to SRAM:<br>@1'b1 - big-endianness<br>@1'b0 - little endianness 9954 </td> 9955 </tr> 9956 <tr> 9957 <td valign="top" align="center"><a name="1.11.8.2"></a>31:1 9958 </td> 9959 <td valign="top">RESERVED</td> 9960 <td valign="top" align="center">rw</td> 9961 <td valign="top" align="center">0x0</td> 9962 <td valign="top">Reserved</td> 9963 </tr> 9964</table><a name="1.11.9"></a><br>1.11.9 : <b>Reg : DIN_CPU_DATA_SIZE</b> : 0x000000C48<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register hold the number of bytes to be transmited using external DMA<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 9965 <tr> 9966 <td colspan="32" align="center">DIN_CPU_DATA_SIZE</td> 9967 </tr> 9968 <tr></tr> 9969</table> 9970<table border="1" width="800"> 9971 <tr> 9972 <td width="40"><b>bits</b></td> 9973 <td width="100"><b>Field name</b></td> 9974 <td width="20"><b>permission</b></td> 9975 <td width="40"><b>default</b></td> 9976 <td width="600"><b>Description</b></td> 9977 </tr> 9978 <tr> 9979 <td valign="top" align="center"><a name="1.11.9.1"></a>15:0 9980 </td> 9981 <td valign="top">CPU_DIN_SIZE</td> 9982 <td valign="top" align="center">wo</td> 9983 <td valign="top" align="center">0x0</td> 9984 <td valign="top">When using external DMA, the size of transmited data in bytes should be written to this register.</td> 9985 </tr> 9986 <tr> 9987 <td valign="top" align="center"><a name="1.11.9.2"></a>31:16 9988 </td> 9989 <td valign="top">RESERVED</td> 9990 <td valign="top" align="center">wo</td> 9991 <td valign="top" align="center">0x0</td> 9992 <td valign="top">Reserved</td> 9993 </tr> 9994</table><a name="1.11.10"></a><br>1.11.10 : <b>Reg : FIFO_IN_EMPTY</b> : 0x000000C50<br><b>reg sep address</b> : <b> reg host address</b> : <br>DIN FIFO empty indication<br><table border="1" bgcolor="#EEEEEE" width="800"> 9995 <tr> 9996 <td colspan="32" align="center">FIFO_IN_EMPTY</td> 9997 </tr> 9998 <tr></tr> 9999</table> 10000<table border="1" width="800"> 10001 <tr> 10002 <td width="40"><b>bits</b></td> 10003 <td width="100"><b>Field name</b></td> 10004 <td width="20"><b>permission</b></td> 10005 <td width="40"><b>default</b></td> 10006 <td width="600"><b>Description</b></td> 10007 </tr> 10008 <tr> 10009 <td valign="top" align="center"><a name="1.11.10.1"></a>0:0 10010 </td> 10011 <td valign="top">EMPTY</td> 10012 <td valign="top" align="center">ro</td> 10013 <td valign="top" align="center">0x1</td> 10014 <td valign="top">1'b1 - FIFO empty</td> 10015 </tr> 10016 <tr> 10017 <td valign="top" align="center"><a name="1.11.10.2"></a>31:1 10018 </td> 10019 <td valign="top">RESERVED</td> 10020 <td valign="top" align="center">ro</td> 10021 <td valign="top" align="center">0x0</td> 10022 <td valign="top">Reserved</td> 10023 </tr> 10024</table><a name="1.11.11"></a><br>1.11.11 : <b>Reg : DIN_FIFO_RST_PNTR</b> : 0x000000C58<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this register resets the DIN_FIFO pointers.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10025 <tr> 10026 <td colspan="32" align="center">DIN_FIFO_RST_PNTR</td> 10027 </tr> 10028 <tr></tr> 10029</table> 10030<table border="1" width="800"> 10031 <tr> 10032 <td width="40"><b>bits</b></td> 10033 <td width="100"><b>Field name</b></td> 10034 <td width="20"><b>permission</b></td> 10035 <td width="40"><b>default</b></td> 10036 <td width="600"><b>Description</b></td> 10037 </tr> 10038 <tr> 10039 <td valign="top" align="center"><a name="1.11.11.1"></a>0:0 10040 </td> 10041 <td valign="top">RST</td> 10042 <td valign="top" align="center">wo</td> 10043 <td valign="top" align="center">0x0</td> 10044 <td valign="top">Writing any value to this address resets the DIN_FIFO pointers.</td> 10045 </tr> 10046 <tr> 10047 <td valign="top" align="center"><a name="1.11.11.2"></a>31:1 10048 </td> 10049 <td valign="top">RESERVED</td> 10050 <td valign="top" align="center">wo</td> 10051 <td valign="top" align="center">0x0</td> 10052 <td valign="top">Reserved</td> 10053 </tr> 10054</table><a href="#1.11">(top of block)</a><a name="1.12"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 10055 <td><b><font color="#000000">1.12 : Block: DOUT</font></b></td> 10056 <td align="right"><font color="#000000">0x000000D00</font></td> 10057</table><br><a name="1.12.1"></a><br>1.12.1 : <b>Reg : DOUT_BUFFER</b> : 0x000000D00<br><b>reg sep address</b> : <b> reg host address</b> : <br>Cryptographic result - CPU can directly access it.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10058 <tr> 10059 <td colspan="32" align="center">DOUT_BUFFER</td> 10060 </tr> 10061 <tr></tr> 10062</table> 10063<table border="1" width="800"> 10064 <tr> 10065 <td width="40"><b>bits</b></td> 10066 <td width="100"><b>Field name</b></td> 10067 <td width="20"><b>permission</b></td> 10068 <td width="40"><b>default</b></td> 10069 <td width="600"><b>Description</b></td> 10070 </tr> 10071 <tr> 10072 <td valign="top" align="center"><a name="1.12.1.1"></a>31:0 10073 </td> 10074 <td valign="top">DOUT_BUFFER_DATA</td> 10075 <td valign="top" align="center">ro</td> 10076 <td valign="top" align="center">0x0</td> 10077 <td valign="top">This address can be used by the CPU to read data directly from the DOUT buffer.</td> 10078 </tr> 10079</table><a name="1.12.2"></a><br>1.12.2 : <b>Reg : DOUT_MEM_DMA_BUSY</b> : 0x000000D20<br><b>reg sep address</b> : <b> reg host address</b> : <br>DOUT memory DMA busy - Indicates that memory (AXI) destination DMA (DOUT) is busy,<br><table border="1" bgcolor="#EEEEEE" width="800"> 10080 <tr> 10081 <td colspan="32" align="center">DOUT_MEM_DMA_BUSY</td> 10082 </tr> 10083 <tr></tr> 10084</table> 10085<table border="1" width="800"> 10086 <tr> 10087 <td width="40"><b>bits</b></td> 10088 <td width="100"><b>Field name</b></td> 10089 <td width="20"><b>permission</b></td> 10090 <td width="40"><b>default</b></td> 10091 <td width="600"><b>Description</b></td> 10092 </tr> 10093 <tr> 10094 <td valign="top" align="center"><a name="1.12.2.1"></a>0:0 10095 </td> 10096 <td valign="top">DOUT_MEM_DMA_BUSY</td> 10097 <td valign="top" align="center">ro</td> 10098 <td valign="top" align="center">0x0</td> 10099 <td valign="top">DOUT memory DMA busy:<br>@1'b1 - busy<br>@1'b0 - not busy 10100 </td> 10101 </tr> 10102 <tr> 10103 <td valign="top" align="center"><a name="1.12.2.2"></a>31:1 10104 </td> 10105 <td valign="top">RESERVED</td> 10106 <td valign="top" align="center">ro</td> 10107 <td valign="top" align="center">0x0</td> 10108 <td valign="top">Reserved</td> 10109 </tr> 10110</table><a name="1.12.3"></a><br>1.12.3 : <b>Reg : DST_LLI_WORD0</b> : 0x000000D28<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is used in direct LLI mode - holds the location of the data destination in the memory (AXI)<br><table border="1" bgcolor="#EEEEEE" width="800"> 10111 <tr> 10112 <td colspan="32" align="center">DST_LLI_WORD0</td> 10113 </tr> 10114 <tr></tr> 10115</table> 10116<table border="1" width="800"> 10117 <tr> 10118 <td width="40"><b>bits</b></td> 10119 <td width="100"><b>Field name</b></td> 10120 <td width="20"><b>permission</b></td> 10121 <td width="40"><b>default</b></td> 10122 <td width="600"><b>Description</b></td> 10123 </tr> 10124 <tr> 10125 <td valign="top" align="center"><a name="1.12.3.1"></a>31:0 10126 </td> 10127 <td valign="top">DST_LLI_WORD0</td> 10128 <td valign="top" align="center">wo</td> 10129 <td valign="top" align="center">0x0</td> 10130 <td valign="top">Destination address within memory</td> 10131 </tr> 10132</table><a name="1.12.4"></a><br>1.12.4 : <b>Reg : DST_LLI_WORD1</b> : 0x000000D2C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register is used in direct LLI mode - holds the number of bytes to be written to the memory (AXI). <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10133 <tr> 10134 <td colspan="32" align="center">DST_LLI_WORD1</td> 10135 </tr> 10136 <tr></tr> 10137</table> 10138<table border="1" width="800"> 10139 <tr> 10140 <td width="40"><b>bits</b></td> 10141 <td width="100"><b>Field name</b></td> 10142 <td width="20"><b>permission</b></td> 10143 <td width="40"><b>default</b></td> 10144 <td width="600"><b>Description</b></td> 10145 </tr> 10146 <tr> 10147 <td valign="top" align="center"><a name="1.12.4.1"></a>29:0 10148 </td> 10149 <td valign="top">BYTES_NUM</td> 10150 <td valign="top" align="center">r/wc</td> 10151 <td valign="top" align="center">0x0</td> 10152 <td valign="top">Total byte number to be written by DMA in this entry</td> 10153 </tr> 10154 <tr> 10155 <td valign="top" align="center"><a name="1.12.4.2"></a>30:30 10156 </td> 10157 <td valign="top">FIRST</td> 10158 <td valign="top" align="center">r/wc</td> 10159 <td valign="top" align="center">0x0</td> 10160 <td valign="top">1'b1 - Indicates the first LLI entry</td> 10161 </tr> 10162 <tr> 10163 <td valign="top" align="center"><a name="1.12.4.3"></a>31:31 10164 </td> 10165 <td valign="top">LAST</td> 10166 <td valign="top" align="center">r/wc</td> 10167 <td valign="top" align="center">0x0</td> 10168 <td valign="top">1'b1 - Indicates the last LLI entry</td> 10169 </tr> 10170</table><a name="1.12.5"></a><br>1.12.5 : <b>Reg : SRAM_DEST_ADDR</b> : 0x000000D30<br><b>reg sep address</b> : <b> reg host address</b> : <br>Location of result to be sent to in SRAM<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10171 <tr> 10172 <td colspan="32" align="center">SRAM_DEST_ADDR</td> 10173 </tr> 10174 <tr></tr> 10175</table> 10176<table border="1" width="800"> 10177 <tr> 10178 <td width="40"><b>bits</b></td> 10179 <td width="100"><b>Field name</b></td> 10180 <td width="20"><b>permission</b></td> 10181 <td width="40"><b>default</b></td> 10182 <td width="600"><b>Description</b></td> 10183 </tr> 10184 <tr> 10185 <td valign="top" align="center"><a name="1.12.5.1"></a>31:0 10186 </td> 10187 <td valign="top">SRAM_DEST</td> 10188 <td valign="top" align="center">rw</td> 10189 <td valign="top" align="center">0x0</td> 10190 <td valign="top">SRAM destination base address for data.</td> 10191 </tr> 10192</table><a name="1.12.6"></a><br>1.12.6 : <b>Reg : DOUT_SRAM_BYTES_LEN</b> : 0x000000D34<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the size of the data (in bytes) to be written to the SRAM.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10193 <tr> 10194 <td colspan="32" align="center">DOUT_SRAM_BYTES_LEN</td> 10195 </tr> 10196 <tr></tr> 10197</table> 10198<table border="1" width="800"> 10199 <tr> 10200 <td width="40"><b>bits</b></td> 10201 <td width="100"><b>Field name</b></td> 10202 <td width="20"><b>permission</b></td> 10203 <td width="40"><b>default</b></td> 10204 <td width="600"><b>Description</b></td> 10205 </tr> 10206 <tr> 10207 <td valign="top" align="center"><a name="1.12.6.1"></a>31:0 10208 </td> 10209 <td valign="top">BYTES_LEN</td> 10210 <td valign="top" align="center">r/wc</td> 10211 <td valign="top" align="center">0x0</td> 10212 <td valign="top">Size of data to write to SRAM (bytes). This is the trigger to the SRAM DST DMA.</td> 10213 </tr> 10214</table><a name="1.12.7"></a><br>1.12.7 : <b>Reg : DOUT_SRAM_DMA_BUSY</b> : 0x000000D38<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the status of the SRAM DMA DOUT.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10215 <tr> 10216 <td colspan="32" align="center">DOUT_SRAM_DMA_BUSY</td> 10217 </tr> 10218 <tr></tr> 10219</table> 10220<table border="1" width="800"> 10221 <tr> 10222 <td width="40"><b>bits</b></td> 10223 <td width="100"><b>Field name</b></td> 10224 <td width="20"><b>permission</b></td> 10225 <td width="40"><b>default</b></td> 10226 <td width="600"><b>Description</b></td> 10227 </tr> 10228 <tr> 10229 <td valign="top" align="center"><a name="1.12.7.1"></a>0:0 10230 </td> 10231 <td valign="top">BUSY</td> 10232 <td valign="top" align="center">ro</td> 10233 <td valign="top" align="center">0x0</td> 10234 <td valign="top">@1'b0 - all data was written to SRAM.<br>@1'b1 - DOUT SRAM DMA busy. 10235 </td> 10236 </tr> 10237 <tr> 10238 <td valign="top" align="center"><a name="1.12.7.2"></a>31:1 10239 </td> 10240 <td valign="top">RESERVED</td> 10241 <td valign="top" align="center">ro</td> 10242 <td valign="top" align="center">0x0</td> 10243 <td valign="top">Reserved</td> 10244 </tr> 10245</table><a name="1.12.8"></a><br>1.12.8 : <b>Reg : DOUT_SRAM_ENDIANNESS</b> : 0x000000D3C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register defines the endianness of the DOUT interface from SRAM.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10246 <tr> 10247 <td colspan="32" align="center">DOUT_SRAM_ENDIANNESS</td> 10248 </tr> 10249 <tr></tr> 10250</table> 10251<table border="1" width="800"> 10252 <tr> 10253 <td width="40"><b>bits</b></td> 10254 <td width="100"><b>Field name</b></td> 10255 <td width="20"><b>permission</b></td> 10256 <td width="40"><b>default</b></td> 10257 <td width="600"><b>Description</b></td> 10258 </tr> 10259 <tr> 10260 <td valign="top" align="center"><a name="1.12.8.1"></a>0:0 10261 </td> 10262 <td valign="top">DOUT_SRAM_ENDIANNESS</td> 10263 <td valign="top" align="center">rw</td> 10264 <td valign="top" align="center">0x0</td> 10265 <td valign="top">Defines the endianness of DOUT interface from SRAM:<br>@1'b1 - big-endianness<br>@1'b0 - little endianness 10266 </td> 10267 </tr> 10268 <tr> 10269 <td valign="top" align="center"><a name="1.12.8.2"></a>31:1 10270 </td> 10271 <td valign="top">RESERVED</td> 10272 <td valign="top" align="center">rw</td> 10273 <td valign="top" align="center">0x0</td> 10274 <td valign="top">Reserved</td> 10275 </tr> 10276</table><a name="1.12.9"></a><br>1.12.9 : <b>Reg : READ_ALIGN_LAST</b> : 0x000000D44<br><b>reg sep address</b> : <b> reg host address</b> : <br>Indication that the next read from the CPU is the last one. This is needed only when the data size is NOT modulo 4 (e.g. HASH 10277padding).<br><table border="1" bgcolor="#EEEEEE" width="800"> 10278 <tr> 10279 <td colspan="32" align="center">READ_ALIGN_LAST</td> 10280 </tr> 10281 <tr></tr> 10282</table> 10283<table border="1" width="800"> 10284 <tr> 10285 <td width="40"><b>bits</b></td> 10286 <td width="100"><b>Field name</b></td> 10287 <td width="20"><b>permission</b></td> 10288 <td width="40"><b>default</b></td> 10289 <td width="600"><b>Description</b></td> 10290 </tr> 10291 <tr> 10292 <td valign="top" align="center"><a name="1.12.9.1"></a>0:0 10293 </td> 10294 <td valign="top">LAST</td> 10295 <td valign="top" align="center">wo</td> 10296 <td valign="top" align="center">0x0</td> 10297 <td valign="top">1'b1 - Flush the read aligner content (used for reading the last data).</td> 10298 </tr> 10299 <tr> 10300 <td valign="top" align="center"><a name="1.12.9.2"></a>31:1 10301 </td> 10302 <td valign="top">RESERVED</td> 10303 <td valign="top" align="center">wo</td> 10304 <td valign="top" align="center">0x0</td> 10305 <td valign="top">Reserved</td> 10306 </tr> 10307</table><a name="1.12.10"></a><br>1.12.10 : <b>Reg : DOUT_FIFO_EMPTY</b> : 0x000000D50<br><b>reg sep address</b> : <b> reg host address</b> : <br>DOUT_FIFO_EMPTY Register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10308 <tr> 10309 <td colspan="32" align="center">DOUT_FIFO_EMPTY</td> 10310 </tr> 10311 <tr></tr> 10312</table> 10313<table border="1" width="800"> 10314 <tr> 10315 <td width="40"><b>bits</b></td> 10316 <td width="100"><b>Field name</b></td> 10317 <td width="20"><b>permission</b></td> 10318 <td width="40"><b>default</b></td> 10319 <td width="600"><b>Description</b></td> 10320 </tr> 10321 <tr> 10322 <td valign="top" align="center"><a name="1.12.10.1"></a>0:0 10323 </td> 10324 <td valign="top">DOUT_FIFO_EMPTY</td> 10325 <td valign="top" align="center">ro</td> 10326 <td valign="top" align="center">0x1</td> 10327 <td valign="top">@1'b0 - DOUT FIFO is not empty <br>@1'b1 - DOUT FIFO is empty 10328 </td> 10329 </tr> 10330 <tr> 10331 <td valign="top" align="center"><a name="1.12.10.2"></a>31:1 10332 </td> 10333 <td valign="top">RESERVED</td> 10334 <td valign="top" align="center">ro</td> 10335 <td valign="top" align="center">0x0</td> 10336 <td valign="top">Reserved</td> 10337 </tr> 10338</table><a href="#1.12">(top of block)</a><a name="1.13"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 10339 <td><b><font color="#000000">1.13 : Block: HOST_SRAM</font></b></td> 10340 <td align="right"><font color="#000000">0x000000F00</font></td> 10341</table><br><a name="1.13.1"></a><br>1.13.1 : <b>Reg : SRAM_DATA</b> : 0x000000F00<br><b>reg sep address</b> : <b> reg host address</b> : <br>READ WRITE DATA FROM SRAM<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10342 <tr> 10343 <td colspan="32" align="center">SRAM_DATA</td> 10344 </tr> 10345 <tr></tr> 10346</table> 10347<table border="1" width="800"> 10348 <tr> 10349 <td width="40"><b>bits</b></td> 10350 <td width="100"><b>Field name</b></td> 10351 <td width="20"><b>permission</b></td> 10352 <td width="40"><b>default</b></td> 10353 <td width="600"><b>Description</b></td> 10354 </tr> 10355 <tr> 10356 <td valign="top" align="center"><a name="1.13.1.1"></a>31:0 10357 </td> 10358 <td valign="top">SRAM_DATA</td> 10359 <td valign="top" align="center">rw</td> 10360 <td valign="top" align="center">0x0</td> 10361 <td valign="top">32 bit write or read from SRAM: read - triggers the SRAM read DMA address automatically incremented write - triggers the SRAM 10362 write DMA address automatically incremented 10363 </td> 10364 </tr> 10365</table><a name="1.13.2"></a><br>1.13.2 : <b>Reg : SRAM_ADDR</b> : 0x000000F04<br><b>reg sep address</b> : <b> reg host address</b> : <br>first address given to SRAM DMA for read/write transactions from SRAM<br><table border="1" bgcolor="#EEEEEE" width="800"> 10366 <tr> 10367 <td colspan="32" align="center">SRAM_ADDR</td> 10368 </tr> 10369 <tr></tr> 10370</table> 10371<table border="1" width="800"> 10372 <tr> 10373 <td width="40"><b>bits</b></td> 10374 <td width="100"><b>Field name</b></td> 10375 <td width="20"><b>permission</b></td> 10376 <td width="40"><b>default</b></td> 10377 <td width="600"><b>Description</b></td> 10378 </tr> 10379 <tr> 10380 <td valign="top" align="center"><a name="1.13.2.1"></a>14:0 10381 </td> 10382 <td valign="top">SRAM_ADDR</td> 10383 <td valign="top" align="center">wo</td> 10384 <td valign="top" align="center">0x0</td> 10385 <td valign="top">SRAM starting address</td> 10386 </tr> 10387 <tr> 10388 <td valign="top" align="center"><a name="1.13.2.2"></a>31:15 10389 </td> 10390 <td valign="top">RESERVED</td> 10391 <td valign="top" align="center">wo</td> 10392 <td valign="top" align="center">0x0</td> 10393 <td valign="top">17'b0</td> 10394 </tr> 10395</table><a name="1.13.3"></a><br>1.13.3 : <b>Reg : SRAM_DATA_READY</b> : 0x000000F08<br><b>reg sep address</b> : <b> reg host address</b> : <br>The SRAM content is ready for read in SRAM_DATA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10396 <tr> 10397 <td colspan="32" align="center">SRAM_DATA_READY</td> 10398 </tr> 10399 <tr></tr> 10400</table> 10401<table border="1" width="800"> 10402 <tr> 10403 <td width="40"><b>bits</b></td> 10404 <td width="100"><b>Field name</b></td> 10405 <td width="20"><b>permission</b></td> 10406 <td width="40"><b>default</b></td> 10407 <td width="600"><b>Description</b></td> 10408 </tr> 10409 <tr> 10410 <td valign="top" align="center"><a name="1.13.3.1"></a>0:0 10411 </td> 10412 <td valign="top">SRAM_READY</td> 10413 <td valign="top" align="center">ro</td> 10414 <td valign="top" align="center">0x1</td> 10415 <td valign="top">SRAM content is ready for read in SRAM_DATA.</td> 10416 </tr> 10417 <tr> 10418 <td valign="top" align="center"><a name="1.13.3.2"></a>31:1 10419 </td> 10420 <td valign="top">RESERVED</td> 10421 <td valign="top" align="center">ro</td> 10422 <td valign="top" align="center">0x0</td> 10423 <td valign="top">Reserved</td> 10424 </tr> 10425</table><a href="#1.13">(top of block)</a><a name="1.14"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 10426 <td><b><font color="#000000">1.14 : Block: ID_REGISTERS</font></b></td> 10427 <td align="right"><font color="#000000">0x000000F10</font></td> 10428</table><br><a name="1.14.1"></a><br>1.14.1 : <b>Reg : PERIPHERAL_ID_4</b> : 0x000000FD0<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10429 <tr> 10430 <td colspan="32" align="center">PERIPHERAL_ID_4</td> 10431 </tr> 10432 <tr></tr> 10433</table> 10434<table border="1" width="800"> 10435 <tr> 10436 <td width="40"><b>bits</b></td> 10437 <td width="100"><b>Field name</b></td> 10438 <td width="20"><b>permission</b></td> 10439 <td width="40"><b>default</b></td> 10440 <td width="600"><b>Description</b></td> 10441 </tr> 10442 <tr> 10443 <td valign="top" align="center"><a name="1.14.1.1"></a>3:0 10444 </td> 10445 <td valign="top">DES_2_JEP106</td> 10446 <td valign="top" align="center">ro</td> 10447 <td valign="top" align="center">0x</td> 10448 <td valign="top">Continuation Code. 0x4 for ARM products.</td> 10449 </tr> 10450 <tr> 10451 <td valign="top" align="center"><a name="1.14.1.2"></a>31:4 10452 </td> 10453 <td valign="top">RESERVED</td> 10454 <td valign="top" align="center">ro</td> 10455 <td valign="top" align="center">0x0</td> 10456 <td valign="top">Reserved<br>Note: This is a special register, this registers 10457 </td> 10458 </tr> 10459</table><a name="1.14.2"></a><br>1.14.2 : <b>Reg : PIDRESERVED0</b> : 0x000000FD4<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10460 <tr> 10461 <td colspan="32" align="center">PIDRESERVED0</td> 10462 </tr> 10463 <tr></tr> 10464</table> 10465<table border="1" width="800"> 10466 <tr> 10467 <td width="40"><b>bits</b></td> 10468 <td width="100"><b>Field name</b></td> 10469 <td width="20"><b>permission</b></td> 10470 <td width="40"><b>default</b></td> 10471 <td width="600"><b>Description</b></td> 10472 </tr> 10473 <tr> 10474 <td valign="top" align="center"><a name="1.14.2.1"></a>31:0 10475 </td> 10476 <td valign="top">RESERVED</td> 10477 <td valign="top" align="center">ro</td> 10478 <td valign="top" align="center">0x0</td> 10479 <td valign="top">Reserved<br>Note: This is a special register, this registers 10480 </td> 10481 </tr> 10482</table><a name="1.14.3"></a><br>1.14.3 : <b>Reg : PIDRESERVED1</b> : 0x000000FD8<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10483 <tr> 10484 <td colspan="32" align="center">PIDRESERVED1</td> 10485 </tr> 10486 <tr></tr> 10487</table> 10488<table border="1" width="800"> 10489 <tr> 10490 <td width="40"><b>bits</b></td> 10491 <td width="100"><b>Field name</b></td> 10492 <td width="20"><b>permission</b></td> 10493 <td width="40"><b>default</b></td> 10494 <td width="600"><b>Description</b></td> 10495 </tr> 10496 <tr> 10497 <td valign="top" align="center"><a name="1.14.3.1"></a>31:0 10498 </td> 10499 <td valign="top">RESERVED</td> 10500 <td valign="top" align="center">ro</td> 10501 <td valign="top" align="center">0x0</td> 10502 <td valign="top">Reserved<br>Note: This is a special register, this registers 10503 </td> 10504 </tr> 10505</table><a name="1.14.4"></a><br>1.14.4 : <b>Reg : PIDRESERVED2</b> : 0x000000FDC<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10506 <tr> 10507 <td colspan="32" align="center">PIDRESERVED2</td> 10508 </tr> 10509 <tr></tr> 10510</table> 10511<table border="1" width="800"> 10512 <tr> 10513 <td width="40"><b>bits</b></td> 10514 <td width="100"><b>Field name</b></td> 10515 <td width="20"><b>permission</b></td> 10516 <td width="40"><b>default</b></td> 10517 <td width="600"><b>Description</b></td> 10518 </tr> 10519 <tr> 10520 <td valign="top" align="center"><a name="1.14.4.1"></a>31:0 10521 </td> 10522 <td valign="top">RESERVED</td> 10523 <td valign="top" align="center">ro</td> 10524 <td valign="top" align="center">0x0</td> 10525 <td valign="top">Reserved<br>Note: This is a special register, this registers 10526 </td> 10527 </tr> 10528</table><a name="1.14.5"></a><br>1.14.5 : <b>Reg : PERIPHERAL_ID_0</b> : 0x000000FE0<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10529 <tr> 10530 <td colspan="32" align="center">PERIPHERAL_ID_0</td> 10531 </tr> 10532 <tr></tr> 10533</table> 10534<table border="1" width="800"> 10535 <tr> 10536 <td width="40"><b>bits</b></td> 10537 <td width="100"><b>Field name</b></td> 10538 <td width="20"><b>permission</b></td> 10539 <td width="40"><b>default</b></td> 10540 <td width="600"><b>Description</b></td> 10541 </tr> 10542 <tr> 10543 <td valign="top" align="center"><a name="1.14.5.1"></a>7:0 10544 </td> 10545 <td valign="top">PART_0</td> 10546 <td valign="top" align="center">ro</td> 10547 <td valign="top" align="center">0x</td> 10548 <td valign="top">Identification register part number, bits[7:0]</td> 10549 </tr> 10550 <tr> 10551 <td valign="top" align="center"><a name="1.14.5.2"></a>31:8 10552 </td> 10553 <td valign="top">RESERVED</td> 10554 <td valign="top" align="center">ro</td> 10555 <td valign="top" align="center">0x0</td> 10556 <td valign="top">Reserved<br>Note: This is a special register, this registers 10557 </td> 10558 </tr> 10559</table><a name="1.14.6"></a><br>1.14.6 : <b>Reg : PERIPHERAL_ID_1</b> : 0x000000FE4<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10560 <tr> 10561 <td colspan="32" align="center">PERIPHERAL_ID_1</td> 10562 </tr> 10563 <tr></tr> 10564</table> 10565<table border="1" width="800"> 10566 <tr> 10567 <td width="40"><b>bits</b></td> 10568 <td width="100"><b>Field name</b></td> 10569 <td width="20"><b>permission</b></td> 10570 <td width="40"><b>default</b></td> 10571 <td width="600"><b>Description</b></td> 10572 </tr> 10573 <tr> 10574 <td valign="top" align="center"><a name="1.14.6.1"></a>3:0 10575 </td> 10576 <td valign="top">PART_1</td> 10577 <td valign="top" align="center">ro</td> 10578 <td valign="top" align="center">0x0</td> 10579 <td valign="top">Identification register part number, bits[11:8]</td> 10580 </tr> 10581 <tr> 10582 <td valign="top" align="center"><a name="1.14.6.2"></a>7:4 10583 </td> 10584 <td valign="top">DES_0_JEP106</td> 10585 <td valign="top" align="center">ro</td> 10586 <td valign="top" align="center">0x3</td> 10587 <td valign="top">identification code, bits[3:0]. 0x3B for ARM products.</td> 10588 </tr> 10589 <tr> 10590 <td valign="top" align="center"><a name="1.14.6.3"></a>31:8 10591 </td> 10592 <td valign="top">RESERVED</td> 10593 <td valign="top" align="center">ro</td> 10594 <td valign="top" align="center">0x0</td> 10595 <td valign="top">Reserved<br>Note: This is a special register, this registers 10596 </td> 10597 </tr> 10598</table><a name="1.14.7"></a><br>1.14.7 : <b>Reg : PERIPHERAL_ID_2</b> : 0x000000FE8<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10599 <tr> 10600 <td colspan="32" align="center">PERIPHERAL_ID_2</td> 10601 </tr> 10602 <tr></tr> 10603</table> 10604<table border="1" width="800"> 10605 <tr> 10606 <td width="40"><b>bits</b></td> 10607 <td width="100"><b>Field name</b></td> 10608 <td width="20"><b>permission</b></td> 10609 <td width="40"><b>default</b></td> 10610 <td width="600"><b>Description</b></td> 10611 </tr> 10612 <tr> 10613 <td valign="top" align="center"><a name="1.14.7.1"></a>2:0 10614 </td> 10615 <td valign="top">DES_1_JEP106</td> 10616 <td valign="top" align="center">ro</td> 10617 <td valign="top" align="center">0x</td> 10618 <td valign="top">identification code, bits[6:4]. 0x3B for ARM products.</td> 10619 </tr> 10620 <tr> 10621 <td valign="top" align="center"><a name="1.14.7.2"></a>3 10622 </td> 10623 <td valign="top">JEDEC</td> 10624 <td valign="top" align="center">ro</td> 10625 <td valign="top" align="center">0x1</td> 10626 <td valign="top">constant 0x1. Indicates that a JEDEC assigned value is used.</td> 10627 </tr> 10628 <tr> 10629 <td valign="top" align="center"><a name="1.14.7.3"></a>7:4 10630 </td> 10631 <td valign="top">REVISION</td> 10632 <td valign="top" align="center">ro</td> 10633 <td valign="top" align="center">0x0</td> 10634 <td valign="top">starts at zero and increments for every new IP release.</td> 10635 </tr> 10636 <tr> 10637 <td valign="top" align="center"><a name="1.14.7.4"></a>31:8 10638 </td> 10639 <td valign="top">RESERVED</td> 10640 <td valign="top" align="center">ro</td> 10641 <td valign="top" align="center">0x0</td> 10642 <td valign="top">Reserved<br>Note: This is a special register, this registers 10643 </td> 10644 </tr> 10645</table><a name="1.14.8"></a><br>1.14.8 : <b>Reg : PERIPHERAL_ID_3</b> : 0x000000FEC<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10646 <tr> 10647 <td colspan="32" align="center">PERIPHERAL_ID_3</td> 10648 </tr> 10649 <tr></tr> 10650</table> 10651<table border="1" width="800"> 10652 <tr> 10653 <td width="40"><b>bits</b></td> 10654 <td width="100"><b>Field name</b></td> 10655 <td width="20"><b>permission</b></td> 10656 <td width="40"><b>default</b></td> 10657 <td width="600"><b>Description</b></td> 10658 </tr> 10659 <tr> 10660 <td valign="top" align="center"><a name="1.14.8.1"></a>3:0 10661 </td> 10662 <td valign="top">CMOD</td> 10663 <td valign="top" align="center">ro</td> 10664 <td valign="top" align="center">0x0</td> 10665 <td valign="top">Customer Modified, normally zero, but if a partner applies any changes themselves, they must change this value.</td> 10666 </tr> 10667 <tr> 10668 <td valign="top" align="center"><a name="1.14.8.2"></a>7:4 10669 </td> 10670 <td valign="top">REVAND</td> 10671 <td valign="top" align="center">ro</td> 10672 <td valign="top" align="center">0x0</td> 10673 <td valign="top">starts at zero for every Revision, and increments if metal fixes are applied between 2 IP releases.</td> 10674 </tr> 10675 <tr> 10676 <td valign="top" align="center"><a name="1.14.8.3"></a>31:8 10677 </td> 10678 <td valign="top">RESERVED</td> 10679 <td valign="top" align="center">ro</td> 10680 <td valign="top" align="center">0x0</td> 10681 <td valign="top">Reserved<br>Note: This is a special register, this registers 10682 </td> 10683 </tr> 10684</table><a name="1.14.9"></a><br>1.14.9 : <b>Reg : COMPONENT_ID_0</b> : 0x000000FF0<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10685 <tr> 10686 <td colspan="32" align="center">COMPONENT_ID_0</td> 10687 </tr> 10688 <tr></tr> 10689</table> 10690<table border="1" width="800"> 10691 <tr> 10692 <td width="40"><b>bits</b></td> 10693 <td width="100"><b>Field name</b></td> 10694 <td width="20"><b>permission</b></td> 10695 <td width="40"><b>default</b></td> 10696 <td width="600"><b>Description</b></td> 10697 </tr> 10698 <tr> 10699 <td valign="top" align="center"><a name="1.14.9.1"></a>7:0 10700 </td> 10701 <td valign="top">PRMBL_0</td> 10702 <td valign="top" align="center">ro</td> 10703 <td valign="top" align="center">0x</td> 10704 <td valign="top">constant 0xD</td> 10705 </tr> 10706 <tr> 10707 <td valign="top" align="center"><a name="1.14.9.2"></a>31:8 10708 </td> 10709 <td valign="top">RESERVED</td> 10710 <td valign="top" align="center">ro</td> 10711 <td valign="top" align="center">0x0</td> 10712 <td valign="top">Reserved<br>Note: This is a special register, this registers 10713 </td> 10714 </tr> 10715</table><a name="1.14.10"></a><br>1.14.10 : <b>Reg : COMPONENT_ID_1</b> : 0x000000FF4<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10716 <tr> 10717 <td colspan="32" align="center">COMPONENT_ID_1</td> 10718 </tr> 10719 <tr></tr> 10720</table> 10721<table border="1" width="800"> 10722 <tr> 10723 <td width="40"><b>bits</b></td> 10724 <td width="100"><b>Field name</b></td> 10725 <td width="20"><b>permission</b></td> 10726 <td width="40"><b>default</b></td> 10727 <td width="600"><b>Description</b></td> 10728 </tr> 10729 <tr> 10730 <td valign="top" align="center"><a name="1.14.10.1"></a>3:0 10731 </td> 10732 <td valign="top">PRMBL_1</td> 10733 <td valign="top" align="center">ro</td> 10734 <td valign="top" align="center">0x0</td> 10735 <td valign="top">constant 0x0</td> 10736 </tr> 10737 <tr> 10738 <td valign="top" align="center"><a name="1.14.10.2"></a>7:4 10739 </td> 10740 <td valign="top">CLASS</td> 10741 <td valign="top" align="center">ro</td> 10742 <td valign="top" align="center">0x</td> 10743 <td valign="top">component type 0 0xF for Cryptocell</td> 10744 </tr> 10745 <tr> 10746 <td valign="top" align="center"><a name="1.14.10.3"></a>31:8 10747 </td> 10748 <td valign="top">RESERVED</td> 10749 <td valign="top" align="center">ro</td> 10750 <td valign="top" align="center">0x0</td> 10751 <td valign="top">Reserved<br>Note: This is a special register, this registers 10752 </td> 10753 </tr> 10754</table><a name="1.14.11"></a><br>1.14.11 : <b>Reg : COMPONENT_ID_2</b> : 0x000000FF8<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10755 <tr> 10756 <td colspan="32" align="center">COMPONENT_ID_2</td> 10757 </tr> 10758 <tr></tr> 10759</table> 10760<table border="1" width="800"> 10761 <tr> 10762 <td width="40"><b>bits</b></td> 10763 <td width="100"><b>Field name</b></td> 10764 <td width="20"><b>permission</b></td> 10765 <td width="40"><b>default</b></td> 10766 <td width="600"><b>Description</b></td> 10767 </tr> 10768 <tr> 10769 <td valign="top" align="center"><a name="1.14.11.1"></a>7:0 10770 </td> 10771 <td valign="top">PRMBL_2</td> 10772 <td valign="top" align="center">ro</td> 10773 <td valign="top" align="center">0x</td> 10774 <td valign="top">constant 0x5</td> 10775 </tr> 10776 <tr> 10777 <td valign="top" align="center"><a name="1.14.11.2"></a>31:8 10778 </td> 10779 <td valign="top">RESERVED</td> 10780 <td valign="top" align="center">ro</td> 10781 <td valign="top" align="center">0x0</td> 10782 <td valign="top">Reserved<br>Note: This is a special register, this registers 10783 </td> 10784 </tr> 10785</table><a name="1.14.12"></a><br>1.14.12 : <b>Reg : COMPONENT_ID_3</b> : 0x000000FFC<br><b>reg sep address</b> : <b> reg host address</b> : <br><br><table border="1" bgcolor="#EEEEEE" width="800"> 10786 <tr> 10787 <td colspan="32" align="center">COMPONENT_ID_3</td> 10788 </tr> 10789 <tr></tr> 10790</table> 10791<table border="1" width="800"> 10792 <tr> 10793 <td width="40"><b>bits</b></td> 10794 <td width="100"><b>Field name</b></td> 10795 <td width="20"><b>permission</b></td> 10796 <td width="40"><b>default</b></td> 10797 <td width="600"><b>Description</b></td> 10798 </tr> 10799 <tr> 10800 <td valign="top" align="center"><a name="1.14.12.1"></a>7:0 10801 </td> 10802 <td valign="top">PRMBL_3</td> 10803 <td valign="top" align="center">ro</td> 10804 <td valign="top" align="center">0x</td> 10805 <td valign="top">constant 0xB1</td> 10806 </tr> 10807 <tr> 10808 <td valign="top" align="center"><a name="1.14.12.2"></a>31:8 10809 </td> 10810 <td valign="top">RESERVED</td> 10811 <td valign="top" align="center">ro</td> 10812 <td valign="top" align="center">0x0</td> 10813 <td valign="top">Reserved<br>Note: This is a special register, this registers 10814 </td> 10815 </tr> 10816</table><a href="#1.14">(top of block)</a><a name="1.15"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 10817 <td><b><font color="#000000">1.15 : Block: AO</font></b></td> 10818 <td align="right"><font color="#000000">0x000001E00</font></td> 10819</table><br><a name="1.15.1"></a><br>1.15.1 : <b>Reg : HOST_DCU_EN0</b> : 0x000001E00<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU [31:0] enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10820 <tr> 10821 <td colspan="32" align="center">HOST_DCU_EN0</td> 10822 </tr> 10823 <tr></tr> 10824</table> 10825<table border="1" width="800"> 10826 <tr> 10827 <td width="40"><b>bits</b></td> 10828 <td width="100"><b>Field name</b></td> 10829 <td width="20"><b>permission</b></td> 10830 <td width="40"><b>default</b></td> 10831 <td width="600"><b>Description</b></td> 10832 </tr> 10833 <tr> 10834 <td valign="top" align="center"><a name="1.15.1.1"></a>31:0 10835 </td> 10836 <td valign="top">HOST_DCU_EN0</td> 10837 <td valign="top" align="center">rw</td> 10838 <td valign="top" align="center">0x0</td> 10839 <td valign="top">Debug Control Unit (DCU) Enable bits.</td> 10840 </tr> 10841</table><a name="1.15.2"></a><br>1.15.2 : <b>Reg : HOST_DCU_EN1</b> : 0x000001E04<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU [63:32] enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10842 <tr> 10843 <td colspan="32" align="center">HOST_DCU_EN1</td> 10844 </tr> 10845 <tr></tr> 10846</table> 10847<table border="1" width="800"> 10848 <tr> 10849 <td width="40"><b>bits</b></td> 10850 <td width="100"><b>Field name</b></td> 10851 <td width="20"><b>permission</b></td> 10852 <td width="40"><b>default</b></td> 10853 <td width="600"><b>Description</b></td> 10854 </tr> 10855 <tr> 10856 <td valign="top" align="center"><a name="1.15.2.1"></a>31:0 10857 </td> 10858 <td valign="top">HOST_DCU_EN1</td> 10859 <td valign="top" align="center">rw</td> 10860 <td valign="top" align="center">0x0</td> 10861 <td valign="top">Debug Control Unit (DCU) Enable bits.</td> 10862 </tr> 10863</table><a name="1.15.3"></a><br>1.15.3 : <b>Reg : HOST_DCU_EN2</b> : 0x000001E08<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU [95:64] enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10864 <tr> 10865 <td colspan="32" align="center">HOST_DCU_EN2</td> 10866 </tr> 10867 <tr></tr> 10868</table> 10869<table border="1" width="800"> 10870 <tr> 10871 <td width="40"><b>bits</b></td> 10872 <td width="100"><b>Field name</b></td> 10873 <td width="20"><b>permission</b></td> 10874 <td width="40"><b>default</b></td> 10875 <td width="600"><b>Description</b></td> 10876 </tr> 10877 <tr> 10878 <td valign="top" align="center"><a name="1.15.3.1"></a>31:0 10879 </td> 10880 <td valign="top">HOST_DCU_EN2</td> 10881 <td valign="top" align="center">rw</td> 10882 <td valign="top" align="center">0x0</td> 10883 <td valign="top">Debug Control Unit (DCU) Enable bits.</td> 10884 </tr> 10885</table><a name="1.15.4"></a><br>1.15.4 : <b>Reg : HOST_DCU_EN3</b> : 0x000001E0C<br><b>reg sep address</b> : <b> reg host address</b> : 1E0C<br>The DCU [1271:96] enable register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10886 <tr> 10887 <td colspan="32" align="center">HOST_DCU_EN3</td> 10888 </tr> 10889 <tr></tr> 10890</table> 10891<table border="1" width="800"> 10892 <tr> 10893 <td width="40"><b>bits</b></td> 10894 <td width="100"><b>Field name</b></td> 10895 <td width="20"><b>permission</b></td> 10896 <td width="40"><b>default</b></td> 10897 <td width="600"><b>Description</b></td> 10898 </tr> 10899 <tr> 10900 <td valign="top" align="center"><a name="1.15.4.1"></a>31:0 10901 </td> 10902 <td valign="top">HOST_DCU_EN3</td> 10903 <td valign="top" align="center">rw</td> 10904 <td valign="top" align="center">0x0</td> 10905 <td valign="top">Debug Control Unit (DCU) Enable bits.</td> 10906 </tr> 10907</table><a name="1.15.5"></a><br>1.15.5 : <b>Reg : HOST_DCU_LOCK0</b> : 0x000001E10<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10908 <tr> 10909 <td colspan="32" align="center">HOST_DCU_LOCK0</td> 10910 </tr> 10911 <tr></tr> 10912</table> 10913<table border="1" width="800"> 10914 <tr> 10915 <td width="40"><b>bits</b></td> 10916 <td width="100"><b>Field name</b></td> 10917 <td width="20"><b>permission</b></td> 10918 <td width="40"><b>default</b></td> 10919 <td width="600"><b>Description</b></td> 10920 </tr> 10921 <tr> 10922 <td valign="top" align="center"><a name="1.15.5.1"></a>31:0 10923 </td> 10924 <td valign="top">HOST_DCU_LOCK0</td> 10925 <td valign="top" align="center">rw</td> 10926 <td valign="top" align="center">0x0</td> 10927 <td valign="top">DCU_lock [31:0] register (a dedicated lock register per DCU bit).</td> 10928 </tr> 10929</table><a name="1.15.6"></a><br>1.15.6 : <b>Reg : HOST_DCU_LOCK1</b> : 0x000001E14<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10930 <tr> 10931 <td colspan="32" align="center">HOST_DCU_LOCK1</td> 10932 </tr> 10933 <tr></tr> 10934</table> 10935<table border="1" width="800"> 10936 <tr> 10937 <td width="40"><b>bits</b></td> 10938 <td width="100"><b>Field name</b></td> 10939 <td width="20"><b>permission</b></td> 10940 <td width="40"><b>default</b></td> 10941 <td width="600"><b>Description</b></td> 10942 </tr> 10943 <tr> 10944 <td valign="top" align="center"><a name="1.15.6.1"></a>31:0 10945 </td> 10946 <td valign="top">HOST_DCU_LOCK1</td> 10947 <td valign="top" align="center">rw</td> 10948 <td valign="top" align="center">0x0</td> 10949 <td valign="top">DCU_lock [63:32] register (a dedicated lock register per DCU bit).</td> 10950 </tr> 10951</table><a name="1.15.7"></a><br>1.15.7 : <b>Reg : HOST_DCU_LOCK2</b> : 0x000001E18<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10952 <tr> 10953 <td colspan="32" align="center">HOST_DCU_LOCK2</td> 10954 </tr> 10955 <tr></tr> 10956</table> 10957<table border="1" width="800"> 10958 <tr> 10959 <td width="40"><b>bits</b></td> 10960 <td width="100"><b>Field name</b></td> 10961 <td width="20"><b>permission</b></td> 10962 <td width="40"><b>default</b></td> 10963 <td width="600"><b>Description</b></td> 10964 </tr> 10965 <tr> 10966 <td valign="top" align="center"><a name="1.15.7.1"></a>31:0 10967 </td> 10968 <td valign="top">HOST_DCU_LOCK2</td> 10969 <td valign="top" align="center">rw</td> 10970 <td valign="top" align="center">0x0</td> 10971 <td valign="top">DCU_lock [95:64] register (a dedicated lock register per DCU bit).</td> 10972 </tr> 10973</table><a name="1.15.8"></a><br>1.15.8 : <b>Reg : HOST_DCU_LOCK3</b> : 0x000001E1C<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10974 <tr> 10975 <td colspan="32" align="center">HOST_DCU_LOCK3</td> 10976 </tr> 10977 <tr></tr> 10978</table> 10979<table border="1" width="800"> 10980 <tr> 10981 <td width="40"><b>bits</b></td> 10982 <td width="100"><b>Field name</b></td> 10983 <td width="20"><b>permission</b></td> 10984 <td width="40"><b>default</b></td> 10985 <td width="600"><b>Description</b></td> 10986 </tr> 10987 <tr> 10988 <td valign="top" align="center"><a name="1.15.8.1"></a>31:0 10989 </td> 10990 <td valign="top">HOST_DCU_LOCK3</td> 10991 <td valign="top" align="center">rw</td> 10992 <td valign="top" align="center">0x0</td> 10993 <td valign="top">DCU_lock [127:96] register (a dedicated lock register per DCU bit).</td> 10994 </tr> 10995</table><a name="1.15.9"></a><br>1.15.9 : <b>Reg : AO_ICV_DCU_RESTRICTION_MASK0</b> : 0x000001E20<br><b>reg sep address</b> : <b> reg host address</b> : <br>The DCU lock register.<br><table border="1" bgcolor="#EEEEEE" width="800"> 10996 <tr> 10997 <td colspan="32" align="center">AO_ICV_DCU_RESTRICTION_MASK0</td> 10998 </tr> 10999 <tr></tr> 11000</table> 11001<table border="1" width="800"> 11002 <tr> 11003 <td width="40"><b>bits</b></td> 11004 <td width="100"><b>Field name</b></td> 11005 <td width="20"><b>permission</b></td> 11006 <td width="40"><b>default</b></td> 11007 <td width="600"><b>Description</b></td> 11008 </tr> 11009 <tr> 11010 <td valign="top" align="center"><a name="1.15.9.1"></a>31:0 11011 </td> 11012 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK0</td> 11013 <td valign="top" align="center">ro</td> 11014 <td valign="top" align="center">0x</td> 11015 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter, that will be a customer modifiable.</td> 11016 </tr> 11017</table><a name="1.15.10"></a><br>1.15.10 : <b>Reg : AO_ICV_DCU_RESTRICTION_MASK1</b> : 0x000001E24<br><b>reg sep address</b> : <b> reg host address</b> : <br>The "ICV_DCU_restriction_mask" parameter is read by FW during the secure debug verification to prevent OEM from setting specific 11018DCUs that protect ICV secrets<br><table border="1" bgcolor="#EEEEEE" width="800"> 11019 <tr> 11020 <td colspan="32" align="center">AO_ICV_DCU_RESTRICTION_MASK1</td> 11021 </tr> 11022 <tr></tr> 11023</table> 11024<table border="1" width="800"> 11025 <tr> 11026 <td width="40"><b>bits</b></td> 11027 <td width="100"><b>Field name</b></td> 11028 <td width="20"><b>permission</b></td> 11029 <td width="40"><b>default</b></td> 11030 <td width="600"><b>Description</b></td> 11031 </tr> 11032 <tr> 11033 <td valign="top" align="center"><a name="1.15.10.1"></a>31:0 11034 </td> 11035 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK1</td> 11036 <td valign="top" align="center">ro</td> 11037 <td valign="top" align="center">0x</td> 11038 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter, that will be a customer modifiable.</td> 11039 </tr> 11040</table><a name="1.15.11"></a><br>1.15.11 : <b>Reg : AO_ICV_DCU_RESTRICTION_MASK2</b> : 0x000001E28<br><b>reg sep address</b> : <b> reg host address</b> : <br>The "ICV_DCU_restriction_mask" parameter is read by FW during the secure debug verification to prevent OEM from setting specific 11041DCUs that protect ICV secrets<br><table border="1" bgcolor="#EEEEEE" width="800"> 11042 <tr> 11043 <td colspan="32" align="center">AO_ICV_DCU_RESTRICTION_MASK2</td> 11044 </tr> 11045 <tr></tr> 11046</table> 11047<table border="1" width="800"> 11048 <tr> 11049 <td width="40"><b>bits</b></td> 11050 <td width="100"><b>Field name</b></td> 11051 <td width="20"><b>permission</b></td> 11052 <td width="40"><b>default</b></td> 11053 <td width="600"><b>Description</b></td> 11054 </tr> 11055 <tr> 11056 <td valign="top" align="center"><a name="1.15.11.1"></a>31:0 11057 </td> 11058 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK2</td> 11059 <td valign="top" align="center">ro</td> 11060 <td valign="top" align="center">0x0</td> 11061 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter, that will be a customer modifiable.</td> 11062 </tr> 11063</table><a name="1.15.12"></a><br>1.15.12 : <b>Reg : AO_ICV_DCU_RESTRICTION_MASK3</b> : 0x000001E2C<br><b>reg sep address</b> : <b> reg host address</b> : <br>The "ICV_DCU_restriction_mask" parameter is read by FW during the secure debug verification to prevent OEM from setting specific 11064DCUs that protect ICV secrets<br><table border="1" bgcolor="#EEEEEE" width="800"> 11065 <tr> 11066 <td colspan="32" align="center">AO_ICV_DCU_RESTRICTION_MASK3</td> 11067 </tr> 11068 <tr></tr> 11069</table> 11070<table border="1" width="800"> 11071 <tr> 11072 <td width="40"><b>bits</b></td> 11073 <td width="100"><b>Field name</b></td> 11074 <td width="20"><b>permission</b></td> 11075 <td width="40"><b>default</b></td> 11076 <td width="600"><b>Description</b></td> 11077 </tr> 11078 <tr> 11079 <td valign="top" align="center"><a name="1.15.12.1"></a>31:0 11080 </td> 11081 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK3</td> 11082 <td valign="top" align="center">ro</td> 11083 <td valign="top" align="center">0x0</td> 11084 <td valign="top">AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter, that will be a customer modifiable.</td> 11085 </tr> 11086</table><a name="1.15.13"></a><br>1.15.13 : <b>Reg : AO_CC_SEC_DEBUG_RESET</b> : 0x000001E30<br><b>reg sep address</b> : <b> reg host address</b> : <br>The reset-upon-debug indication<br><table border="1" bgcolor="#EEEEEE" width="800"> 11087 <tr> 11088 <td colspan="32" align="center">AO_CC_SEC_DEBUG_RESET</td> 11089 </tr> 11090 <tr></tr> 11091</table> 11092<table border="1" width="800"> 11093 <tr> 11094 <td width="40"><b>bits</b></td> 11095 <td width="100"><b>Field name</b></td> 11096 <td width="20"><b>permission</b></td> 11097 <td width="40"><b>default</b></td> 11098 <td width="600"><b>Description</b></td> 11099 </tr> 11100 <tr> 11101 <td valign="top" align="center"><a name="1.15.13.1"></a>0:0 11102 </td> 11103 <td valign="top">AO_CC_SEC_DEBUG_RESET</td> 11104 <td valign="top" align="center">ro</td> 11105 <td valign="top" align="center">0x0</td> 11106 <td valign="top">For resets Cerberus, and prevents loading the HW keys after that reset</td> 11107 </tr> 11108 <tr> 11109 <td valign="top" align="center"><a name="1.15.13.2"></a>31:1 11110 </td> 11111 <td valign="top">RESERVED</td> 11112 <td valign="top" align="center">ro</td> 11113 <td valign="top" align="center">0x0</td> 11114 <td valign="top">Reserved</td> 11115 </tr> 11116</table><a name="1.15.14"></a><br>1.15.14 : <b>Reg : HOST_AO_LOCK_BITS</b> : 0x000001E34<br><b>reg sep address</b> : <b> reg host address</b> : <br>These masks will define, per LCS, which DCU bits will be tied to zero, even if the Host tries to set them. Note: This is a 11117special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11118 <tr> 11119 <td colspan="32" align="center">HOST_AO_LOCK_BITS</td> 11120 </tr> 11121 <tr></tr> 11122</table> 11123<table border="1" width="800"> 11124 <tr> 11125 <td width="40"><b>bits</b></td> 11126 <td width="100"><b>Field name</b></td> 11127 <td width="20"><b>permission</b></td> 11128 <td width="40"><b>default</b></td> 11129 <td width="600"><b>Description</b></td> 11130 </tr> 11131 <tr> 11132 <td valign="top" align="center"><a name="1.15.14.1"></a>0:0 11133 </td> 11134 <td valign="top">HOST_FATAL_ERR</td> 11135 <td valign="top" align="center">rw</td> 11136 <td valign="top" align="center">0x0</td> 11137 <td valign="top">When the "FATAL_ERROR" register is asserted - HW keys will not be copied from OTP</td> 11138 </tr> 11139 <tr> 11140 <td valign="top" align="center"><a name="1.15.14.2"></a>1:1 11141 </td> 11142 <td valign="top">HOST_KPICV_LOCK</td> 11143 <td valign="top" align="center">rw</td> 11144 <td valign="top" align="center">0x0</td> 11145 <td valign="top">When this FW controlled register is set, the Kpicv HW key is masked (to zero).</td> 11146 </tr> 11147 <tr> 11148 <td valign="top" align="center"><a name="1.15.14.3"></a>2:2 11149 </td> 11150 <td valign="top">HOST_KCEICV_LOCK</td> 11151 <td valign="top" align="center">rw</td> 11152 <td valign="top" align="center">0x0</td> 11153 <td valign="top">When this FW controlled register is set, the Kceicv HW key is masked (to zero).</td> 11154 </tr> 11155 <tr> 11156 <td valign="top" align="center"><a name="1.15.14.4"></a>3:3 11157 </td> 11158 <td valign="top">HOST_KCP_LOCK</td> 11159 <td valign="top" align="center">rw</td> 11160 <td valign="top" align="center">0x0</td> 11161 <td valign="top">When this FW controlled register is set, the Kcp HW key is masked (to zero).</td> 11162 </tr> 11163 <tr> 11164 <td valign="top" align="center"><a name="1.15.14.5"></a>4:4 11165 </td> 11166 <td valign="top">HOST_KCE_LOCK</td> 11167 <td valign="top" align="center">rw</td> 11168 <td valign="top" align="center">0x0</td> 11169 <td valign="top">When this FW controlled register is set, the Kce HW key is masked (to zero).</td> 11170 </tr> 11171 <tr> 11172 <td valign="top" align="center"><a name="1.15.14.6"></a>5:5 11173 </td> 11174 <td valign="top">HOST_ICV_RMA_LOCK</td> 11175 <td valign="top" align="center">rw</td> 11176 <td valign="top" align="center">0x0</td> 11177 <td valign="top">The ICV_RMA_LOCK register is set-once (per POR).</td> 11178 </tr> 11179 <tr> 11180 <td valign="top" align="center"><a name="1.15.14.7"></a>6:6 11181 </td> 11182 <td valign="top">RESET_UPON_DEBUG_DISABLE</td> 11183 <td valign="top" align="center">rw</td> 11184 <td valign="top" align="center">0x0</td> 11185 <td valign="top">The RESET_UPON_DEBUG_DISABLE register is set-once (per POR).</td> 11186 </tr> 11187 <tr> 11188 <td valign="top" align="center"><a name="1.15.14.8"></a>7:7 11189 </td> 11190 <td valign="top">HOST_FORCE_DFA_ENABLE</td> 11191 <td valign="top" align="center">rw</td> 11192 <td valign="top" align="center">0x1</td> 11193 <td valign="top">When this FW controlled register is set, the AES DFA countermeasures are enabled/disabled (regardless of the AES_DFA_IS_ON 11194 register value). 11195 </td> 11196 </tr> 11197 <tr> 11198 <td valign="top" align="center"><a name="1.15.14.9"></a>8:8 11199 </td> 11200 <td valign="top">HOST_DFA_ENABLE_LOCK</td> 11201 <td valign="top" align="center">rw</td> 11202 <td valign="top" align="center">0x0</td> 11203 <td valign="top">When this FW control is set, the DFA_ENABLE register can't be written until the next POR. The DFA_ENABLE_LOCK register is 11204 set-once (per POR). 11205 </td> 11206 </tr> 11207 <tr> 11208 <td valign="top" align="center"><a name="1.15.14.10"></a>31:9 11209 </td> 11210 <td valign="top">RESERVED</td> 11211 <td valign="top" align="center">rw</td> 11212 <td valign="top" align="center">0x0</td> 11213 <td valign="top">Reserved</td> 11214 </tr> 11215</table><a name="1.15.15"></a><br>1.15.15 : <b>Reg : AO_APB_FILTERING</b> : 0x000001E38<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register holds the AO_APB_FILTERING data. Note: This is a special register, affected by internal logic. Test result of 11216this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11217 <tr> 11218 <td colspan="32" align="center">AO_APB_FILTERING</td> 11219 </tr> 11220 <tr></tr> 11221</table> 11222<table border="1" width="800"> 11223 <tr> 11224 <td width="40"><b>bits</b></td> 11225 <td width="100"><b>Field name</b></td> 11226 <td width="20"><b>permission</b></td> 11227 <td width="40"><b>default</b></td> 11228 <td width="600"><b>Description</b></td> 11229 </tr> 11230 <tr> 11231 <td valign="top" align="center"><a name="1.15.15.1"></a>0:0 11232 </td> 11233 <td valign="top">ONLY_SEC_ACCESS_ALLOW</td> 11234 <td valign="top" align="center">rw</td> 11235 <td valign="top" align="center">0x1</td> 11236 <td valign="top">when this FW controlled register is set, the APB slave accepts only secure accesses</td> 11237 </tr> 11238 <tr> 11239 <td valign="top" align="center"><a name="1.15.15.2"></a>1:1 11240 </td> 11241 <td valign="top">ONLY_SEC_ACCESS_ALLOW_LOCK</td> 11242 <td valign="top" align="center">rw</td> 11243 <td valign="top" align="center">0x0</td> 11244 <td valign="top">when this FW controlled register is set, the ONLY_SEC_ACCESS_ALLOWED register can't be modified (until the next POR).</td> 11245 </tr> 11246 <tr> 11247 <td valign="top" align="center"><a name="1.15.15.3"></a>2:2 11248 </td> 11249 <td valign="top">ONLY_PRIV_ACCESS_ALLOW</td> 11250 <td valign="top" align="center">rw</td> 11251 <td valign="top" align="center">0x1</td> 11252 <td valign="top">when this FW controlled register is set, the APB slave accepts only privileged accesses</td> 11253 </tr> 11254 <tr> 11255 <td valign="top" align="center"><a name="1.15.15.4"></a>3:3 11256 </td> 11257 <td valign="top">ONLY_PRIV_ACCESS_ALLOW_LOCK</td> 11258 <td valign="top" align="center">rw</td> 11259 <td valign="top" align="center">0x0</td> 11260 <td valign="top">when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLOWED register can't be modified (until the next POR)</td> 11261 </tr> 11262 <tr> 11263 <td valign="top" align="center"><a name="1.15.15.5"></a>4:4 11264 </td> 11265 <td valign="top">APBC_ONLY_SEC_ACCESS_ALLOW</td> 11266 <td valign="top" align="center">rw</td> 11267 <td valign="top" align="center">0x1</td> 11268 <td valign="top">when this FW controlled register is set, the APB-C slave accepts only secure accesses</td> 11269 </tr> 11270 <tr> 11271 <td valign="top" align="center"><a name="1.15.15.6"></a>5:5 11272 </td> 11273 <td valign="top">APBC_ONLY_SEC_ACCESS_ALLOW_LOCK</td> 11274 <td valign="top" align="center">rw</td> 11275 <td valign="top" align="center">0x0</td> 11276 <td valign="top">when this FW controlled register is set, the APBC_ONLY_SEC_ACCESS_ALLOWED register can't be modified (until the next POR).</td> 11277 </tr> 11278 <tr> 11279 <td valign="top" align="center"><a name="1.15.15.7"></a>6:6 11280 </td> 11281 <td valign="top">APBC_ONLY_PRIV_ACCESS_ALLOW</td> 11282 <td valign="top" align="center">rw</td> 11283 <td valign="top" align="center">0x1</td> 11284 <td valign="top">when this FW controlled register is set, the APB-C slave accepts only privileged accesses</td> 11285 </tr> 11286 <tr> 11287 <td valign="top" align="center"><a name="1.15.15.8"></a>7:7 11288 </td> 11289 <td valign="top">APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK</td> 11290 <td valign="top" align="center">rw</td> 11291 <td valign="top" align="center">0x0</td> 11292 <td valign="top">when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLOWED register can't be modified (until the next POR)</td> 11293 </tr> 11294 <tr> 11295 <td valign="top" align="center"><a name="1.15.15.9"></a>8:8 11296 </td> 11297 <td valign="top">APBC_ONLY_INST_ACCESS_ALLOW</td> 11298 <td valign="top" align="center">rw</td> 11299 <td valign="top" align="center">0x0</td> 11300 <td valign="top">when this FW controlled register is set, the APB-C slave accepts only instruction accesses</td> 11301 </tr> 11302 <tr> 11303 <td valign="top" align="center"><a name="1.15.15.10"></a>9:9 11304 </td> 11305 <td valign="top">APBC_ONLY_INST_ACCESS_ALLOW_LOCK</td> 11306 <td valign="top" align="center">rw</td> 11307 <td valign="top" align="center">0x0</td> 11308 <td valign="top">when this FW controlled register is set, the APBC_ONLY_INST_ACCESS_ALLOWED register can't be modified (until the next POR)</td> 11309 </tr> 11310 <tr> 11311 <td valign="top" align="center"><a name="1.15.15.11"></a>31:10 11312 </td> 11313 <td valign="top">RESERVED</td> 11314 <td valign="top" align="center">rw</td> 11315 <td valign="top" align="center">0x0</td> 11316 <td valign="top">Reserved</td> 11317 </tr> 11318</table><a name="1.15.16"></a><br>1.15.16 : <b>Reg : AO_CC_GPPC</b> : 0x000001E3C<br><b>reg sep address</b> : <b> reg host address</b> : <br>holds the AO_CC_GPPC value from AO<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11319 <tr> 11320 <td colspan="32" align="center">AO_CC_GPPC</td> 11321 </tr> 11322 <tr></tr> 11323</table> 11324<table border="1" width="800"> 11325 <tr> 11326 <td width="40"><b>bits</b></td> 11327 <td width="100"><b>Field name</b></td> 11328 <td width="20"><b>permission</b></td> 11329 <td width="40"><b>default</b></td> 11330 <td width="600"><b>Description</b></td> 11331 </tr> 11332 <tr> 11333 <td valign="top" align="center"><a name="1.15.16.1"></a>7:0 11334 </td> 11335 <td valign="top">AO_CC_GPPC</td> 11336 <td valign="top" align="center">ro</td> 11337 <td valign="top" align="center">0x0</td> 11338 <td valign="top">The AO_CC_GPPC value</td> 11339 </tr> 11340 <tr> 11341 <td valign="top" align="center"><a name="1.15.16.2"></a>31:8 11342 </td> 11343 <td valign="top">RESERVED</td> 11344 <td valign="top" align="center">ro</td> 11345 <td valign="top" align="center">0x0</td> 11346 <td valign="top">reserved</td> 11347 </tr> 11348</table><a name="1.15.17"></a><br>1.15.17 : <b>Reg : HOST_RGF_CC_SW_RST</b> : 0x000001E40<br><b>reg sep address</b> : <b> reg host address</b> : <br>Writing to this register generates a general reset to CryptoCell. This reset takes about 4 core clock cycles.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11349 <tr> 11350 <td colspan="32" align="center">HOST_RGF_CC_SW_RST</td> 11351 </tr> 11352 <tr></tr> 11353</table> 11354<table border="1" width="800"> 11355 <tr> 11356 <td width="40"><b>bits</b></td> 11357 <td width="100"><b>Field name</b></td> 11358 <td width="20"><b>permission</b></td> 11359 <td width="40"><b>default</b></td> 11360 <td width="600"><b>Description</b></td> 11361 </tr> 11362 <tr> 11363 <td valign="top" align="center"><a name="1.15.17.1"></a>0:0 11364 </td> 11365 <td valign="top">HOST_RGF_CC_SW_RST</td> 11366 <td valign="top" align="center">wo</td> 11367 <td valign="top" align="center">0x0</td> 11368 <td valign="top">Writing '1' to this field generates a general reset to CryptoCell.</td> 11369 </tr> 11370 <tr> 11371 <td valign="top" align="center"><a name="1.15.17.2"></a>31:1 11372 </td> 11373 <td valign="top">RESERVED</td> 11374 <td valign="top" align="center">wo</td> 11375 <td valign="top" align="center">0x0</td> 11376 <td valign="top">Reserved</td> 11377 </tr> 11378</table><a href="#1.15">(top of block)</a><a name="1.16"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 11379 <td><b><font color="#000000">1.16 : Block: NVM</font></b></td> 11380 <td align="right"><font color="#000000">0x000001F00</font></td> 11381</table><br><a name="1.16.1"></a><br>1.16.1 : <b>Reg : AIB_FUSE_PROG_COMPLETED</b> : 0x000001F04<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register reflects the fuse_aib_prog_completed input, which indicates that the fuse programming was completed.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11382 <tr> 11383 <td colspan="32" align="center">AIB_FUSE_PROG_COMPLETED</td> 11384 </tr> 11385 <tr></tr> 11386</table> 11387<table border="1" width="800"> 11388 <tr> 11389 <td width="40"><b>bits</b></td> 11390 <td width="100"><b>Field name</b></td> 11391 <td width="20"><b>permission</b></td> 11392 <td width="40"><b>default</b></td> 11393 <td width="600"><b>Description</b></td> 11394 </tr> 11395 <tr> 11396 <td valign="top" align="center"><a name="1.16.1.1"></a>0:0 11397 </td> 11398 <td valign="top">AIB_FUSE_PROG_COMPLETED</td> 11399 <td valign="top" align="center">ro</td> 11400 <td valign="top" align="center">0x0</td> 11401 <td valign="top">Indicates if the fuse programming operation has been completed.</td> 11402 </tr> 11403 <tr> 11404 <td valign="top" align="center"><a name="1.16.1.2"></a>31:1 11405 </td> 11406 <td valign="top">RESERVED</td> 11407 <td valign="top" align="center">ro</td> 11408 <td valign="top" align="center">0x0</td> 11409 <td valign="top">Reserved</td> 11410 </tr> 11411</table><a name="1.16.2"></a><br>1.16.2 : <b>Reg : NVM_DEBUG_STATUS</b> : 0x000001F08<br><b>reg sep address</b> : <b> reg host address</b> : <br>AIB debug status register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11412 <tr> 11413 <td colspan="32" align="center">NVM_DEBUG_STATUS</td> 11414 </tr> 11415 <tr></tr> 11416</table> 11417<table border="1" width="800"> 11418 <tr> 11419 <td width="40"><b>bits</b></td> 11420 <td width="100"><b>Field name</b></td> 11421 <td width="20"><b>permission</b></td> 11422 <td width="40"><b>default</b></td> 11423 <td width="600"><b>Description</b></td> 11424 </tr> 11425 <tr> 11426 <td valign="top" align="center"><a name="1.16.2.1"></a>0:0 11427 </td> 11428 <td valign="top">RESERVED0</td> 11429 <td valign="top" align="center">ro</td> 11430 <td valign="top" align="center">0x0</td> 11431 <td valign="top">Reserved</td> 11432 </tr> 11433 <tr> 11434 <td valign="top" align="center"><a name="1.16.2.2"></a>3:1 11435 </td> 11436 <td valign="top">NVM_SM</td> 11437 <td valign="top" align="center">ro</td> 11438 <td valign="top" align="center">0x0</td> 11439 <td valign="top">Main nvm fsm<br>3'b000 - IDLE<br>3'b001 - READ_DUMMY<br>3'b010 - READ_MAN_FLAG<br>3'b011 - READ_OEM_FLAG<br>3'b100 - READ_GPPC<br>3'b101 - DECODE<br>3'b110 - OTP_LCS_VALID<br>3'b111 - LCS_IS_VALID 11440 </td> 11441 </tr> 11442 <tr> 11443 <td valign="top" align="center"><a name="1.16.2.3"></a>31:4 11444 </td> 11445 <td valign="top">RESERVED1</td> 11446 <td valign="top" align="center">ro</td> 11447 <td valign="top" align="center">0x0</td> 11448 <td valign="top">Reserved</td> 11449 </tr> 11450</table><a name="1.16.3"></a><br>1.16.3 : <b>Reg : LCS_IS_VALID</b> : 0x000001F0C<br><b>reg sep address</b> : <b> reg host address</b> : <br>Indicates that the LCS register holds a valid value.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11451 <tr> 11452 <td colspan="32" align="center">LCS_IS_VALID</td> 11453 </tr> 11454 <tr></tr> 11455</table> 11456<table border="1" width="800"> 11457 <tr> 11458 <td width="40"><b>bits</b></td> 11459 <td width="100"><b>Field name</b></td> 11460 <td width="20"><b>permission</b></td> 11461 <td width="40"><b>default</b></td> 11462 <td width="600"><b>Description</b></td> 11463 </tr> 11464 <tr> 11465 <td valign="top" align="center"><a name="1.16.3.1"></a>0:0 11466 </td> 11467 <td valign="top">LCS_IS_VALID_REG</td> 11468 <td valign="top" align="center">ro</td> 11469 <td valign="top" align="center">0x0</td> 11470 <td valign="top">Indicates whether LCS is valid.</td> 11471 </tr> 11472 <tr> 11473 <td valign="top" align="center"><a name="1.16.3.2"></a>31:1 11474 </td> 11475 <td valign="top">RESERVED</td> 11476 <td valign="top" align="center">ro</td> 11477 <td valign="top" align="center">0x0</td> 11478 <td valign="top">Reserved</td> 11479 </tr> 11480</table><a name="1.16.4"></a><br>1.16.4 : <b>Reg : NVM_IS_IDLE</b> : 0x000001F10<br><b>reg sep address</b> : <b> reg host address</b> : <br>Indicates that the LCS register holds a valid value.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11481 <tr> 11482 <td colspan="32" align="center">NVM_IS_IDLE</td> 11483 </tr> 11484 <tr></tr> 11485</table> 11486<table border="1" width="800"> 11487 <tr> 11488 <td width="40"><b>bits</b></td> 11489 <td width="100"><b>Field name</b></td> 11490 <td width="20"><b>permission</b></td> 11491 <td width="40"><b>default</b></td> 11492 <td width="600"><b>Description</b></td> 11493 </tr> 11494 <tr> 11495 <td valign="top" align="center"><a name="1.16.4.1"></a>0:0 11496 </td> 11497 <td valign="top">NVM_IS_IDLE_REG</td> 11498 <td valign="top" align="center">ro</td> 11499 <td valign="top" align="center">0x0</td> 11500 <td valign="top">Indicates whether the NVM manager finishes its operation, calculates the LCS, reads the HW keys, compares the number of zeros 11501 and clears the keys 11502 </td> 11503 </tr> 11504 <tr> 11505 <td valign="top" align="center"><a name="1.16.4.2"></a>31:1 11506 </td> 11507 <td valign="top">RESERVED</td> 11508 <td valign="top" align="center">ro</td> 11509 <td valign="top" align="center">0x0</td> 11510 <td valign="top">Reserved</td> 11511 </tr> 11512</table><a name="1.16.5"></a><br>1.16.5 : <b>Reg : LCS_REG</b> : 0x000001F14<br><b>reg sep address</b> : <b> reg host address</b> : <br>The lifecycle state register.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11513 <tr> 11514 <td colspan="32" align="center">LCS_REG</td> 11515 </tr> 11516 <tr></tr> 11517</table> 11518<table border="1" width="800"> 11519 <tr> 11520 <td width="40"><b>bits</b></td> 11521 <td width="100"><b>Field name</b></td> 11522 <td width="20"><b>permission</b></td> 11523 <td width="40"><b>default</b></td> 11524 <td width="600"><b>Description</b></td> 11525 </tr> 11526 <tr> 11527 <td valign="top" align="center"><a name="1.16.5.1"></a>2:0 11528 </td> 11529 <td valign="top">LCS_REG</td> 11530 <td valign="top" align="center">ro</td> 11531 <td valign="top" align="center">0x</td> 11532 <td valign="top">Indicates the LCS (Lifecycle State) value.<br>3'b000 - CM<br>3'b001 - DM<br>3'b101 - SE<br>3'b111 - RMA 11533 </td> 11534 </tr> 11535 <tr> 11536 <td valign="top" align="center"><a name="1.16.5.2"></a>7:3 11537 </td> 11538 <td valign="top">RESERVED0</td> 11539 <td valign="top" align="center">ro</td> 11540 <td valign="top" align="center">0x0</td> 11541 <td valign="top">Reserved</td> 11542 </tr> 11543 <tr> 11544 <td valign="top" align="center"><a name="1.16.5.3"></a>8:8 11545 </td> 11546 <td valign="top">ERROR_KDR_ZERO_CNT</td> 11547 <td valign="top" align="center">ro</td> 11548 <td valign="top" align="center">0x0</td> 11549 <td valign="top">Indication that the number of zeroes in the loaded KDR is not equal to the value set in the manufacture flag.</td> 11550 </tr> 11551 <tr> 11552 <td valign="top" align="center"><a name="1.16.5.4"></a>9:9 11553 </td> 11554 <td valign="top">ERROR_PROV_ZERO_CNT</td> 11555 <td valign="top" align="center">ro</td> 11556 <td valign="top" align="center">0x0</td> 11557 <td valign="top">Indication that the number of zeroes in the loaded KCP is not equal to the value set in the OEM flag.</td> 11558 </tr> 11559 <tr> 11560 <td valign="top" align="center"><a name="1.16.5.5"></a>10:10 11561 </td> 11562 <td valign="top">ERROR_KCE_ZERO_CNT</td> 11563 <td valign="top" align="center">ro</td> 11564 <td valign="top" align="center">0x0</td> 11565 <td valign="top">Indication that the number of zeroes in the loaded KCE is not equal to the value set in the OEM flag.</td> 11566 </tr> 11567 <tr> 11568 <td valign="top" align="center"><a name="1.16.5.6"></a>11:11 11569 </td> 11570 <td valign="top">ERROR_KPICV_ZERO_CNT</td> 11571 <td valign="top" align="center">ro</td> 11572 <td valign="top" align="center">0x0</td> 11573 <td valign="top">Indication that the number of zeroes in the loaded KPICV is not equal to the value set in the manufacture flag.</td> 11574 </tr> 11575 <tr> 11576 <td valign="top" align="center"><a name="1.16.5.7"></a>12:12 11577 </td> 11578 <td valign="top">ERROR_KCEICV_ZERO_CNT</td> 11579 <td valign="top" align="center">ro</td> 11580 <td valign="top" align="center">0x0</td> 11581 <td valign="top">Indication that the number of zeroes in the loaded KCEICV is not equal to the value set in the manufacture flag.</td> 11582 </tr> 11583 <tr> 11584 <td valign="top" align="center"><a name="1.16.5.8"></a>31:13 11585 </td> 11586 <td valign="top">RESERVED1</td> 11587 <td valign="top" align="center">ro</td> 11588 <td valign="top" align="center">0x0</td> 11589 <td valign="top">Reserved</td> 11590 </tr> 11591</table><a name="1.16.6"></a><br>1.16.6 : <b>Reg : HOST_SHADOW_KDR_REG</b> : 0x000001F18<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register interface is used to update the RKEK(KDR) registers when the device is in CM or DM mode , it is Write-once 11592(per warm boot) in RMA LCS, The RKEK is updated by shifting .<br><table border="1" bgcolor="#EEEEEE" width="800"> 11593 <tr> 11594 <td colspan="32" align="center">HOST_SHADOW_KDR_REG</td> 11595 </tr> 11596 <tr></tr> 11597</table> 11598<table border="1" width="800"> 11599 <tr> 11600 <td width="40"><b>bits</b></td> 11601 <td width="100"><b>Field name</b></td> 11602 <td width="20"><b>permission</b></td> 11603 <td width="40"><b>default</b></td> 11604 <td width="600"><b>Description</b></td> 11605 </tr> 11606 <tr> 11607 <td valign="top" align="center"><a name="1.16.6.1"></a>0:0 11608 </td> 11609 <td valign="top">HOST_SHADOW_KDR_REG</td> 11610 <td valign="top" align="center">wo</td> 11611 <td valign="top" align="center">0x0</td> 11612 <td valign="top">This field is used to update the KDR registers when the device is in CM , DM or RMA mode, The KDR is updated by shifting .</td> 11613 </tr> 11614 <tr> 11615 <td valign="top" align="center"><a name="1.16.6.2"></a>31:1 11616 </td> 11617 <td valign="top">RESERVED</td> 11618 <td valign="top" align="center">wo</td> 11619 <td valign="top" align="center">0x0</td> 11620 <td valign="top">Reserved</td> 11621 </tr> 11622</table><a name="1.16.7"></a><br>1.16.7 : <b>Reg : HOST_SHADOW_KCP_REG</b> : 0x000001F1C<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register interface is used to update the KCP registers when the device is in CM or DM mode, The KCP is updated by shifting<br><table border="1" bgcolor="#EEEEEE" width="800"> 11623 <tr> 11624 <td colspan="32" align="center">HOST_SHADOW_KCP_REG</td> 11625 </tr> 11626 <tr></tr> 11627</table> 11628<table border="1" width="800"> 11629 <tr> 11630 <td width="40"><b>bits</b></td> 11631 <td width="100"><b>Field name</b></td> 11632 <td width="20"><b>permission</b></td> 11633 <td width="40"><b>default</b></td> 11634 <td width="600"><b>Description</b></td> 11635 </tr> 11636 <tr> 11637 <td valign="top" align="center"><a name="1.16.7.1"></a>0:0 11638 </td> 11639 <td valign="top">HOST_SHADOW_KCP_REG</td> 11640 <td valign="top" align="center">wo</td> 11641 <td valign="top" align="center">0x0</td> 11642 <td valign="top">This field is used to update the KCP registers when the device is in CM or DM mode, The KCP is updated by shifting</td> 11643 </tr> 11644 <tr> 11645 <td valign="top" align="center"><a name="1.16.7.2"></a>31:1 11646 </td> 11647 <td valign="top">RESERVED</td> 11648 <td valign="top" align="center">wo</td> 11649 <td valign="top" align="center">0x0</td> 11650 <td valign="top">Reserved</td> 11651 </tr> 11652</table><a name="1.16.8"></a><br>1.16.8 : <b>Reg : HOST_SHADOW_KCE_REG</b> : 0x000001F20<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register interface is used to update the KCE registers when the device is in CM or DM mode, The KCE is updated by shifting<br><table border="1" bgcolor="#EEEEEE" width="800"> 11653 <tr> 11654 <td colspan="32" align="center">HOST_SHADOW_KCE_REG</td> 11655 </tr> 11656 <tr></tr> 11657</table> 11658<table border="1" width="800"> 11659 <tr> 11660 <td width="40"><b>bits</b></td> 11661 <td width="100"><b>Field name</b></td> 11662 <td width="20"><b>permission</b></td> 11663 <td width="40"><b>default</b></td> 11664 <td width="600"><b>Description</b></td> 11665 </tr> 11666 <tr> 11667 <td valign="top" align="center"><a name="1.16.8.1"></a>0:0 11668 </td> 11669 <td valign="top">HOST_SHADOW_KCE_REG</td> 11670 <td valign="top" align="center">wo</td> 11671 <td valign="top" align="center">0x0</td> 11672 <td valign="top">This field is used to update the KCE registers when the device is in CM or DM mode, The KCE is updated by shifting</td> 11673 </tr> 11674 <tr> 11675 <td valign="top" align="center"><a name="1.16.8.2"></a>31:1 11676 </td> 11677 <td valign="top">RESERVED</td> 11678 <td valign="top" align="center">wo</td> 11679 <td valign="top" align="center">0x0</td> 11680 <td valign="top">Reserved</td> 11681 </tr> 11682</table><a name="1.16.9"></a><br>1.16.9 : <b>Reg : HOST_SHADOW_KPICV_REG</b> : 0x000001F24<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register interface is used to update the KPICV registers when the device is in CM or DM mode, The KPICV is updated by 11683shifting<br><table border="1" bgcolor="#EEEEEE" width="800"> 11684 <tr> 11685 <td colspan="32" align="center">HOST_SHADOW_KPICV_REG</td> 11686 </tr> 11687 <tr></tr> 11688</table> 11689<table border="1" width="800"> 11690 <tr> 11691 <td width="40"><b>bits</b></td> 11692 <td width="100"><b>Field name</b></td> 11693 <td width="20"><b>permission</b></td> 11694 <td width="40"><b>default</b></td> 11695 <td width="600"><b>Description</b></td> 11696 </tr> 11697 <tr> 11698 <td valign="top" align="center"><a name="1.16.9.1"></a>0:0 11699 </td> 11700 <td valign="top">HOST_SHADOW_KPICV_REG</td> 11701 <td valign="top" align="center">wo</td> 11702 <td valign="top" align="center">0x0</td> 11703 <td valign="top">This field is used to update the KPICV registers when the device is in CM or DM mode, The KPICV is updated by shifting</td> 11704 </tr> 11705 <tr> 11706 <td valign="top" align="center"><a name="1.16.9.2"></a>31:1 11707 </td> 11708 <td valign="top">RESERVED</td> 11709 <td valign="top" align="center">wo</td> 11710 <td valign="top" align="center">0x0</td> 11711 <td valign="top">Reserved</td> 11712 </tr> 11713</table><a name="1.16.10"></a><br>1.16.10 : <b>Reg : HOST_SHADOW_KCEICV_REG</b> : 0x000001F28<br><b>reg sep address</b> : <b> reg host address</b> : <br>This register interface is used to update the KCEICV registers when the device is in CM or DM mode, The KCEICV is updated 11714by shifting<br><table border="1" bgcolor="#EEEEEE" width="800"> 11715 <tr> 11716 <td colspan="32" align="center">HOST_SHADOW_KCEICV_REG</td> 11717 </tr> 11718 <tr></tr> 11719</table> 11720<table border="1" width="800"> 11721 <tr> 11722 <td width="40"><b>bits</b></td> 11723 <td width="100"><b>Field name</b></td> 11724 <td width="20"><b>permission</b></td> 11725 <td width="40"><b>default</b></td> 11726 <td width="600"><b>Description</b></td> 11727 </tr> 11728 <tr> 11729 <td valign="top" align="center"><a name="1.16.10.1"></a>0:0 11730 </td> 11731 <td valign="top">HOST_SHADOW_KCEICV_REG</td> 11732 <td valign="top" align="center">wo</td> 11733 <td valign="top" align="center">0x0</td> 11734 <td valign="top">This field is used to update the KCEICV registers when the device is in CM or DM mode, The KCEICV is updated by shifting</td> 11735 </tr> 11736 <tr> 11737 <td valign="top" align="center"><a name="1.16.10.2"></a>31:1 11738 </td> 11739 <td valign="top">RESERVED</td> 11740 <td valign="top" align="center">wo</td> 11741 <td valign="top" align="center">0x0</td> 11742 <td valign="top">Reserved</td> 11743 </tr> 11744</table><a name="1.16.11"></a><br>1.16.11 : <b>Reg : OTP_ADDR_WIDTH_DEF</b> : 0x000001F2C<br><b>reg sep address</b> : <b> reg host address</b> : <br>OTP_ADDR_WIDTH parameter, that will define the integrated OTP address width (address in words). The supported sizes are 6 11745(for 2 Kbits),7,8,9,11 (for 64 Kbits). The default value in the provided RTL will be 6.<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11746 <tr> 11747 <td colspan="32" align="center">OTP_ADDR_WIDTH_DEF</td> 11748 </tr> 11749 <tr></tr> 11750</table> 11751<table border="1" width="800"> 11752 <tr> 11753 <td width="40"><b>bits</b></td> 11754 <td width="100"><b>Field name</b></td> 11755 <td width="20"><b>permission</b></td> 11756 <td width="40"><b>default</b></td> 11757 <td width="600"><b>Description</b></td> 11758 </tr> 11759 <tr> 11760 <td valign="top" align="center"><a name="1.16.11.1"></a>3:0 11761 </td> 11762 <td valign="top">OTP_ADDR_WIDTH_DEF</td> 11763 <td valign="top" align="center">ro</td> 11764 <td valign="top" align="center">0x</td> 11765 <td valign="top">Holds the OTP_ADDR_WIDTH_DEF value.</td> 11766 </tr> 11767 <tr> 11768 <td valign="top" align="center"><a name="1.16.11.2"></a>31:4 11769 </td> 11770 <td valign="top">RESERVED</td> 11771 <td valign="top" align="center">ro</td> 11772 <td valign="top" align="center">0x0</td> 11773 <td valign="top">Reserved</td> 11774 </tr> 11775</table><a href="#1.16">(top of block)</a><a name="1.17"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 11776 <td><b><font color="#000000">1.17 : Block: ENV_CC_MEMORIES</font></b></td> 11777 <td align="right"><font color="#000000">0x060004000</font></td> 11778</table><br><a name="1.17.1"></a><br>1.17.1 : <b>Reg : ENV_FUSE_READY</b> : 0x060004000<br><b>reg sep address</b> : <b> reg host address</b> : <br>keep FUSE ready de-asserted (used in Discretix internal DSM tests only)<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11779 <tr> 11780 <td colspan="32" align="center">ENV_FUSE_READY</td> 11781 </tr> 11782 <tr></tr> 11783</table> 11784<table border="1" width="800"> 11785 <tr> 11786 <td width="40"><b>bits</b></td> 11787 <td width="100"><b>Field name</b></td> 11788 <td width="20"><b>permission</b></td> 11789 <td width="40"><b>default</b></td> 11790 <td width="600"><b>Description</b></td> 11791 </tr> 11792 <tr> 11793 <td valign="top" align="center"><a name="1.17.1.1"></a>0:0 11794 </td> 11795 <td valign="top">FUSE_READY</td> 11796 <td valign="top" align="center">wo</td> 11797 <td valign="top" align="center">0x0</td> 11798 <td valign="top">1'0 - FUSE ready kept low , 1'1 - FUSE ready released</td> 11799 </tr> 11800 <tr> 11801 <td valign="top" align="center"><a name="1.17.1.2"></a>31:1 11802 </td> 11803 <td valign="top">RESERVED</td> 11804 <td valign="top" align="center">wo</td> 11805 <td valign="top" align="center">0x0</td> 11806 <td valign="top">31'b0</td> 11807 </tr> 11808</table><a name="1.17.2"></a><br>1.17.2 : <b>Reg : ENV_PERF_RAM_MASTER</b> : 0x0600040EC<br><b>reg sep address</b> : <b> reg host address</b> : <br>selects who's the Performance RAM master<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11809 <tr> 11810 <td colspan="32" align="center">ENV_PERF_RAM_MASTER</td> 11811 </tr> 11812 <tr></tr> 11813</table> 11814<table border="1" width="800"> 11815 <tr> 11816 <td width="40"><b>bits</b></td> 11817 <td width="100"><b>Field name</b></td> 11818 <td width="20"><b>permission</b></td> 11819 <td width="40"><b>default</b></td> 11820 <td width="600"><b>Description</b></td> 11821 </tr> 11822 <tr> 11823 <td valign="top" align="center"><a name="1.17.2.1"></a>0:0 11824 </td> 11825 <td valign="top">PERF_RAM_MASTER</td> 11826 <td valign="top" align="center">wo</td> 11827 <td valign="top" align="center">0x0</td> 11828 <td valign="top">1'b0 - sw_monitor_sni0er, 1'b1 - HOST</td> 11829 </tr> 11830 <tr> 11831 <td valign="top" align="center"><a name="1.17.2.2"></a>31:1 11832 </td> 11833 <td valign="top">RESERVED</td> 11834 <td valign="top" align="center">wo</td> 11835 <td valign="top" align="center">0x0</td> 11836 <td valign="top">selects who's the Performance RAM master</td> 11837 </tr> 11838</table><a name="1.17.3"></a><br>1.17.3 : <b>Reg : ENV_PERF_RAM_ADDR_HIGH4</b> : 0x0600040F0<br><b>reg sep address</b> : <b> reg host address</b> : <br>4 bits to concat with ENV_PERF_RAM_BASE[11]<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11839 <tr> 11840 <td colspan="32" align="center">ENV_PERF_RAM_ADDR_HIGH4</td> 11841 </tr> 11842 <tr></tr> 11843</table> 11844<table border="1" width="800"> 11845 <tr> 11846 <td width="40"><b>bits</b></td> 11847 <td width="100"><b>Field name</b></td> 11848 <td width="20"><b>permission</b></td> 11849 <td width="40"><b>default</b></td> 11850 <td width="600"><b>Description</b></td> 11851 </tr> 11852 <tr> 11853 <td valign="top" align="center"><a name="1.17.3.1"></a>1:0 11854 </td> 11855 <td valign="top">ADDR_HIGH_4</td> 11856 <td valign="top" align="center">wo</td> 11857 <td valign="top" align="center">0x0</td> 11858 <td valign="top">4 bits to concatenate: perf ram address = {ENV_PERF_RAM_ADDR_HIGH[3:0] ENV_PERF_RAM_BASE[11:2]}</td> 11859 </tr> 11860 <tr> 11861 <td valign="top" align="center"><a name="1.17.3.2"></a>31:2 11862 </td> 11863 <td valign="top">RESERVED</td> 11864 <td valign="top" align="center">wo</td> 11865 <td valign="top" align="center">0x0</td> 11866 <td valign="top">4 bits to concat with ENV_PERF_RAM_BASE[11</td> 11867 </tr> 11868</table><a name="1.17.4"></a><br>1.17.4 : <b>Reg : ENV_FUSES_RAM</b> : 0x0600043EC<br><b>reg sep address</b> : <b> reg host address</b> : <br>Using this address the HOST gains access to the aib_slave_model (fuses). (Actually there are 256 words hidden here.)<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11869 <tr> 11870 <td colspan="32" align="center">ENV_FUSES_RAM</td> 11871 </tr> 11872 <tr></tr> 11873</table> 11874<table border="1" width="800"> 11875 <tr> 11876 <td width="40"><b>bits</b></td> 11877 <td width="100"><b>Field name</b></td> 11878 <td width="20"><b>permission</b></td> 11879 <td width="40"><b>default</b></td> 11880 <td width="600"><b>Description</b></td> 11881 </tr> 11882 <tr> 11883 <td valign="top" align="center"><a name="1.17.4.1"></a>31:0 11884 </td> 11885 <td valign="top">FUSE_VAL</td> 11886 <td valign="top" align="center">r/wc</td> 11887 <td valign="top" align="center">0x0</td> 11888 <td valign="top">Fuse value</td> 11889 </tr> 11890</table><a href="#1.17">(top of block)</a><a name="1.18"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 11891 <td><b><font color="#000000">1.18 : Block: FPGA_ENV_REGS</font></b></td> 11892 <td align="right"><font color="#000000">0x060005000</font></td> 11893</table><br><a name="1.18.1"></a><br>1.18.1 : <b>Reg : ENV_FPGA_PKA_DEBUG_MODE</b> : 0x060005024<br><b>reg sep address</b> : <b> reg host address</b> : <br>Drive PKA debug mode <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11894 <tr> 11895 <td colspan="32" align="center">ENV_FPGA_PKA_DEBUG_MODE</td> 11896 </tr> 11897 <tr></tr> 11898</table> 11899<table border="1" width="800"> 11900 <tr> 11901 <td width="40"><b>bits</b></td> 11902 <td width="100"><b>Field name</b></td> 11903 <td width="20"><b>permission</b></td> 11904 <td width="40"><b>default</b></td> 11905 <td width="600"><b>Description</b></td> 11906 </tr> 11907 <tr> 11908 <td valign="top" align="center"><a name="1.18.1.1"></a>0:0 11909 </td> 11910 <td valign="top">PKA_DEBUG_MODE</td> 11911 <td valign="top" align="center">rw</td> 11912 <td valign="top" align="center">0x0</td> 11913 <td valign="top">1'b1 - PKA in debug mode</td> 11914 </tr> 11915 <tr> 11916 <td valign="top" align="center"><a name="1.18.1.2"></a>31:1 11917 </td> 11918 <td valign="top">RESERVED</td> 11919 <td valign="top" align="center">rw</td> 11920 <td valign="top" align="center">0x0</td> 11921 <td valign="top">0</td> 11922 </tr> 11923</table><a name="1.18.2"></a><br>1.18.2 : <b>Reg : ENV_FPGA_SCAN_MODE</b> : 0x060005030<br><b>reg sep address</b> : <b> reg host address</b> : <br>CryptoCell scan_mode input<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11924 <tr> 11925 <td colspan="32" align="center">ENV_FPGA_SCAN_MODE</td> 11926 </tr> 11927 <tr></tr> 11928</table> 11929<table border="1" width="800"> 11930 <tr> 11931 <td width="40"><b>bits</b></td> 11932 <td width="100"><b>Field name</b></td> 11933 <td width="20"><b>permission</b></td> 11934 <td width="40"><b>default</b></td> 11935 <td width="600"><b>Description</b></td> 11936 </tr> 11937 <tr> 11938 <td valign="top" align="center"><a name="1.18.2.1"></a>0:0 11939 </td> 11940 <td valign="top">SCAN_MODE</td> 11941 <td valign="top" align="center">wo</td> 11942 <td valign="top" align="center">0x0</td> 11943 <td valign="top">when Scan mode is set RKEKs are reset</td> 11944 </tr> 11945 <tr> 11946 <td valign="top" align="center"><a name="1.18.2.2"></a>31:1 11947 </td> 11948 <td valign="top">RESERVED</td> 11949 <td valign="top" align="center">wo</td> 11950 <td valign="top" align="center">0x0</td> 11951 <td valign="top">0</td> 11952 </tr> 11953</table><a name="1.18.3"></a><br>1.18.3 : <b>Reg : ENV_FPGA_CC_ALLOW_SCAN</b> : 0x060005034<br><b>reg sep address</b> : <b> reg host address</b> : <br>CryptoCell allow_scan output<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11954 <tr> 11955 <td colspan="32" align="center">ENV_FPGA_CC_ALLOW_SCAN</td> 11956 </tr> 11957 <tr></tr> 11958</table> 11959<table border="1" width="800"> 11960 <tr> 11961 <td width="40"><b>bits</b></td> 11962 <td width="100"><b>Field name</b></td> 11963 <td width="20"><b>permission</b></td> 11964 <td width="40"><b>default</b></td> 11965 <td width="600"><b>Description</b></td> 11966 </tr> 11967 <tr> 11968 <td valign="top" align="center"><a name="1.18.3.1"></a>0:0 11969 </td> 11970 <td valign="top">CC_ALLOW_SCAN</td> 11971 <td valign="top" align="center">ro</td> 11972 <td valign="top" align="center">0x1</td> 11973 <td valign="top">When low scan can not be performed. Reset value is: 1'b1</td> 11974 </tr> 11975 <tr> 11976 <td valign="top" align="center"><a name="1.18.3.2"></a>31:1 11977 </td> 11978 <td valign="top">RESERVED</td> 11979 <td valign="top" align="center">ro</td> 11980 <td valign="top" align="center">0x0</td> 11981 <td valign="top">0</td> 11982 </tr> 11983</table><a name="1.18.4"></a><br>1.18.4 : <b>Reg : ENV_FPGA_CC_HOST_INT</b> : 0x0600050A0<br><b>reg sep address</b> : <b> reg host address</b> : <br>CryptoCell interrupt value<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 11984 <tr> 11985 <td colspan="32" align="center">ENV_FPGA_CC_HOST_INT</td> 11986 </tr> 11987 <tr></tr> 11988</table> 11989<table border="1" width="800"> 11990 <tr> 11991 <td width="40"><b>bits</b></td> 11992 <td width="100"><b>Field name</b></td> 11993 <td width="20"><b>permission</b></td> 11994 <td width="40"><b>default</b></td> 11995 <td width="600"><b>Description</b></td> 11996 </tr> 11997 <tr> 11998 <td valign="top" align="center"><a name="1.18.4.1"></a>0:0 11999 </td> 12000 <td valign="top">CC_HOST_INT</td> 12001 <td valign="top" align="center">ro</td> 12002 <td valign="top" align="center">0x0</td> 12003 <td valign="top">CryptoCell interrupt to Host Active High</td> 12004 </tr> 12005 <tr> 12006 <td valign="top" align="center"><a name="1.18.4.2"></a>31:1 12007 </td> 12008 <td valign="top">RESERVED</td> 12009 <td valign="top" align="center">ro</td> 12010 <td valign="top" align="center">0x0</td> 12011 <td valign="top">0</td> 12012 </tr> 12013</table><a name="1.18.5"></a><br>1.18.5 : <b>Reg : ENV_FPGA_CC_PUB_HOST_INT</b> : 0x0600050A4<br><b>reg sep address</b> : <b> reg host address</b> : <br>CryptoCell public host interrupt value<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12014 <tr> 12015 <td colspan="32" align="center">ENV_FPGA_CC_PUB_HOST_INT</td> 12016 </tr> 12017 <tr></tr> 12018</table> 12019<table border="1" width="800"> 12020 <tr> 12021 <td width="40"><b>bits</b></td> 12022 <td width="100"><b>Field name</b></td> 12023 <td width="20"><b>permission</b></td> 12024 <td width="40"><b>default</b></td> 12025 <td width="600"><b>Description</b></td> 12026 </tr> 12027 <tr> 12028 <td valign="top" align="center"><a name="1.18.5.1"></a>0:0 12029 </td> 12030 <td valign="top">CC_PUB_HOST_INT</td> 12031 <td valign="top" align="center">ro</td> 12032 <td valign="top" align="center">0x0</td> 12033 <td valign="top">CryptoCell interrupt to public Host Active High</td> 12034 </tr> 12035 <tr> 12036 <td valign="top" align="center"><a name="1.18.5.2"></a>31:1 12037 </td> 12038 <td valign="top">RESERVED</td> 12039 <td valign="top" align="center">ro</td> 12040 <td valign="top" align="center">0x0</td> 12041 <td valign="top">0</td> 12042 </tr> 12043</table><a name="1.18.6"></a><br>1.18.6 : <b>Reg : ENV_FPGA_CC_RST_N</b> : 0x0600050A8<br><b>reg sep address</b> : <b> reg host address</b> : <br>generate reset cycle towards CryptoCell<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12044 <tr> 12045 <td colspan="32" align="center">ENV_FPGA_CC_RST_N</td> 12046 </tr> 12047 <tr></tr> 12048</table> 12049<table border="1" width="800"> 12050 <tr> 12051 <td width="40"><b>bits</b></td> 12052 <td width="100"><b>Field name</b></td> 12053 <td width="20"><b>permission</b></td> 12054 <td width="40"><b>default</b></td> 12055 <td width="600"><b>Description</b></td> 12056 </tr> 12057 <tr> 12058 <td valign="top" align="center"><a name="1.18.6.1"></a>0:0 12059 </td> 12060 <td valign="top">CC_RST_N</td> 12061 <td valign="top" align="center">wo</td> 12062 <td valign="top" align="center">0x0</td> 12063 <td valign="top">1'b1 - generate reset cycle towards CryptoCell</td> 12064 </tr> 12065 <tr> 12066 <td valign="top" align="center"><a name="1.18.6.2"></a>31:1 12067 </td> 12068 <td valign="top">RESERVED</td> 12069 <td valign="top" align="center">wo</td> 12070 <td valign="top" align="center">0x0</td> 12071 <td valign="top">generate reset cycle towards CryptoCell</td> 12072 </tr> 12073</table><a name="1.18.7"></a><br>1.18.7 : <b>Reg : ENV_FPGA_RST_OVERRIDE</b> : 0x0600050AC<br><b>reg sep address</b> : <b> reg host address</b> : <br>Force high all reset lines in CryptoCell<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12074 <tr> 12075 <td colspan="32" align="center">ENV_FPGA_RST_OVERRIDE</td> 12076 </tr> 12077 <tr></tr> 12078</table> 12079<table border="1" width="800"> 12080 <tr> 12081 <td width="40"><b>bits</b></td> 12082 <td width="100"><b>Field name</b></td> 12083 <td width="20"><b>permission</b></td> 12084 <td width="40"><b>default</b></td> 12085 <td width="600"><b>Description</b></td> 12086 </tr> 12087 <tr> 12088 <td valign="top" align="center"><a name="1.18.7.1"></a>0:0 12089 </td> 12090 <td valign="top">RST_OVERRIDE</td> 12091 <td valign="top" align="center">wo</td> 12092 <td valign="top" align="center">0x0</td> 12093 <td valign="top">1'b1 - doesn't permit SW_RST or SYS_RST to CryptoCell or any engine</td> 12094 </tr> 12095 <tr> 12096 <td valign="top" align="center"><a name="1.18.7.2"></a>31:1 12097 </td> 12098 <td valign="top">RESERVED</td> 12099 <td valign="top" align="center">wo</td> 12100 <td valign="top" align="center">0x0</td> 12101 <td valign="top">Force high all reset lines in CryptoCell<br>Note: This is a special register, affected by internal logic. Test result of this register is NA. 12102 </td> 12103 </tr> 12104</table><a name="1.18.8"></a><br>1.18.8 : <b>Reg : ENV_FPGA_CC_POR_N_ADDR</b> : 0x0600050E0<br><b>reg sep address</b> : <b> reg host address</b> : <br>CryptoCell power ON <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12105 <tr> 12106 <td colspan="32" align="center">ENV_FPGA_CC_POR_N_ADDR</td> 12107 </tr> 12108 <tr></tr> 12109</table> 12110<table border="1" width="800"> 12111 <tr> 12112 <td width="40"><b>bits</b></td> 12113 <td width="100"><b>Field name</b></td> 12114 <td width="20"><b>permission</b></td> 12115 <td width="40"><b>default</b></td> 12116 <td width="600"><b>Description</b></td> 12117 </tr> 12118 <tr> 12119 <td valign="top" align="center"><a name="1.18.8.1"></a>0:0 12120 </td> 12121 <td valign="top">CC_POR_N_ADDR</td> 12122 <td valign="top" align="center">wo</td> 12123 <td valign="top" align="center">0x1</td> 12124 <td valign="top">Active low. When asserted indicates that the entire system is powered on and not only the CryptoCell. If there's no potential 12125 powering down of the CryptoCell in the SoC this input must be connected to the SYS_RST_n input 12126 </td> 12127 </tr> 12128 <tr> 12129 <td valign="top" align="center"><a name="1.18.8.2"></a>31:1 12130 </td> 12131 <td valign="top">RESERVED</td> 12132 <td valign="top" align="center">wo</td> 12133 <td valign="top" align="center">0x0</td> 12134 <td valign="top">CryptoCell power ON</td> 12135 </tr> 12136</table><a name="1.18.9"></a><br>1.18.9 : <b>Reg : ENV_FPGA_CC_COLD_RST</b> : 0x0600050FC<br><b>reg sep address</b> : <b> reg host address</b> : <br>CryptoCell cold reset<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12137 <tr> 12138 <td colspan="32" align="center">ENV_FPGA_CC_COLD_RST</td> 12139 </tr> 12140 <tr></tr> 12141</table> 12142<table border="1" width="800"> 12143 <tr> 12144 <td width="40"><b>bits</b></td> 12145 <td width="100"><b>Field name</b></td> 12146 <td width="20"><b>permission</b></td> 12147 <td width="40"><b>default</b></td> 12148 <td width="600"><b>Description</b></td> 12149 </tr> 12150 <tr> 12151 <td valign="top" align="center"><a name="1.18.9.1"></a>0:0 12152 </td> 12153 <td valign="top">ENV_CC_COLD_RST</td> 12154 <td valign="top" align="center">wo</td> 12155 <td valign="top" align="center">0x0</td> 12156 <td valign="top">CryptoCell cold reset assertion</td> 12157 </tr> 12158 <tr> 12159 <td valign="top" align="center"><a name="1.18.9.2"></a>31:1 12160 </td> 12161 <td valign="top">RESERVED</td> 12162 <td valign="top" align="center">wo</td> 12163 <td valign="top" align="center">0x0</td> 12164 <td valign="top">CryptoCell cold reset</td> 12165 </tr> 12166</table><a name="1.18.10"></a><br>1.18.10 : <b>Reg : ENV_FPGA_DUMMY_ADDR</b> : 0x060005108<br><b>reg sep address</b> : <b> reg host address</b> : <br>dummy environment register <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12167 <tr> 12168 <td colspan="32" align="center">ENV_FPGA_DUMMY_ADDR</td> 12169 </tr> 12170 <tr></tr> 12171</table> 12172<table border="1" width="800"> 12173 <tr> 12174 <td width="40"><b>bits</b></td> 12175 <td width="100"><b>Field name</b></td> 12176 <td width="20"><b>permission</b></td> 12177 <td width="40"><b>default</b></td> 12178 <td width="600"><b>Description</b></td> 12179 </tr> 12180 <tr> 12181 <td valign="top" align="center"><a name="1.18.10.1"></a>31:0 12182 </td> 12183 <td valign="top">ENV_DUMMY_ADDR</td> 12184 <td valign="top" align="center">rw</td> 12185 <td valign="top" align="center">0x0</td> 12186 <td valign="top">0</td> 12187 </tr> 12188</table><a name="1.18.11"></a><br>1.18.11 : <b>Reg : ENV_FPGA_COUNTER_CLR</b> : 0x060005118<br><b>reg sep address</b> : <b> reg host address</b> : <br>clear and start the SW counter<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12189 <tr> 12190 <td colspan="32" align="center">ENV_FPGA_COUNTER_CLR</td> 12191 </tr> 12192 <tr></tr> 12193</table> 12194<table border="1" width="800"> 12195 <tr> 12196 <td width="40"><b>bits</b></td> 12197 <td width="100"><b>Field name</b></td> 12198 <td width="20"><b>permission</b></td> 12199 <td width="40"><b>default</b></td> 12200 <td width="600"><b>Description</b></td> 12201 </tr> 12202 <tr> 12203 <td valign="top" align="center"><a name="1.18.11.1"></a>0:0 12204 </td> 12205 <td valign="top">COUNTER_CLR</td> 12206 <td valign="top" align="center">wo</td> 12207 <td valign="top" align="center">0x0</td> 12208 <td valign="top">1'b1 - clear/start counter</td> 12209 </tr> 12210 <tr> 12211 <td valign="top" align="center"><a name="1.18.11.2"></a>31:1 12212 </td> 12213 <td valign="top">RESERVED</td> 12214 <td valign="top" align="center">wo</td> 12215 <td valign="top" align="center">0x0</td> 12216 <td valign="top">clear and start the SW counter</td> 12217 </tr> 12218</table><a name="1.18.12"></a><br>1.18.12 : <b>Reg : ENV_FPGA_COUNTER_RD</b> : 0x06000511C<br><b>reg sep address</b> : <b> reg host address</b> : <br>clear and start the SW counter<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12219 <tr> 12220 <td colspan="32" align="center">ENV_FPGA_COUNTER_RD</td> 12221 </tr> 12222 <tr></tr> 12223</table> 12224<table border="1" width="800"> 12225 <tr> 12226 <td width="40"><b>bits</b></td> 12227 <td width="100"><b>Field name</b></td> 12228 <td width="20"><b>permission</b></td> 12229 <td width="40"><b>default</b></td> 12230 <td width="600"><b>Description</b></td> 12231 </tr> 12232 <tr> 12233 <td valign="top" align="center"><a name="1.18.12.1"></a>31:0 12234 </td> 12235 <td valign="top">COUNTER_VAL</td> 12236 <td valign="top" align="center">ro</td> 12237 <td valign="top" align="center">0x0</td> 12238 <td valign="top">SW counter value</td> 12239 </tr> 12240</table><a name="1.18.13"></a><br>1.18.13 : <b>Reg : ENV_FPGA_RNG_DEBUG_ENABLE</b> : 0x060005430<br><b>reg sep address</b> : <b> reg host address</b> : <br>set RNG debug port<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12241 <tr> 12242 <td colspan="32" align="center">ENV_FPGA_RNG_DEBUG_ENABLE</td> 12243 </tr> 12244 <tr></tr> 12245</table> 12246<table border="1" width="800"> 12247 <tr> 12248 <td width="40"><b>bits</b></td> 12249 <td width="100"><b>Field name</b></td> 12250 <td width="20"><b>permission</b></td> 12251 <td width="40"><b>default</b></td> 12252 <td width="600"><b>Description</b></td> 12253 </tr> 12254 <tr> 12255 <td valign="top" align="center"><a name="1.18.13.1"></a>0:0 12256 </td> 12257 <td valign="top">DEBUG_EN</td> 12258 <td valign="top" align="center">wo</td> 12259 <td valign="top" align="center">0x0</td> 12260 <td valign="top">1'b1 - RNG debug port asserted</td> 12261 </tr> 12262 <tr> 12263 <td valign="top" align="center"><a name="1.18.13.2"></a>31:1 12264 </td> 12265 <td valign="top">RESERVED</td> 12266 <td valign="top" align="center">wo</td> 12267 <td valign="top" align="center">0x0</td> 12268 <td valign="top">31'b0</td> 12269 </tr> 12270</table><a name="1.18.14"></a><br>1.18.14 : <b>Reg : ENV_FPGA_CC_LCS</b> : 0x06000543C<br><b>reg sep address</b> : <b> reg host address</b> : <br>LCS register value<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12271 <tr> 12272 <td colspan="32" align="center">ENV_FPGA_CC_LCS</td> 12273 </tr> 12274 <tr></tr> 12275</table> 12276<table border="1" width="800"> 12277 <tr> 12278 <td width="40"><b>bits</b></td> 12279 <td width="100"><b>Field name</b></td> 12280 <td width="20"><b>permission</b></td> 12281 <td width="40"><b>default</b></td> 12282 <td width="600"><b>Description</b></td> 12283 </tr> 12284 <tr> 12285 <td valign="top" align="center"><a name="1.18.14.1"></a>7:0 12286 </td> 12287 <td valign="top">LCS</td> 12288 <td valign="top" align="center">ro</td> 12289 <td valign="top" align="center">0x0</td> 12290 <td valign="top">LCS data</td> 12291 </tr> 12292 <tr> 12293 <td valign="top" align="center"><a name="1.18.14.2"></a>31:8 12294 </td> 12295 <td valign="top">RESERVED</td> 12296 <td valign="top" align="center">ro</td> 12297 <td valign="top" align="center">0x0</td> 12298 <td valign="top">24'b0</td> 12299 </tr> 12300</table><a name="1.18.15"></a><br>1.18.15 : <b>Reg : ENV_FPGA_CC_IS_CM_DM_SECURE_RMA</b> : 0x060005440<br><b>reg sep address</b> : <b> reg host address</b> : <br>read the lcs states if it is CM DM SECURED or RMA<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12301 <tr> 12302 <td colspan="32" align="center">ENV_FPGA_CC_IS_CM_DM_SECURE_RMA</td> 12303 </tr> 12304 <tr></tr> 12305</table> 12306<table border="1" width="800"> 12307 <tr> 12308 <td width="40"><b>bits</b></td> 12309 <td width="100"><b>Field name</b></td> 12310 <td width="20"><b>permission</b></td> 12311 <td width="40"><b>default</b></td> 12312 <td width="600"><b>Description</b></td> 12313 </tr> 12314 <tr> 12315 <td valign="top" align="center"><a name="1.18.15.1"></a>0:0 12316 </td> 12317 <td valign="top">IS_CM</td> 12318 <td valign="top" align="center">ro</td> 12319 <td valign="top" align="center">0x0</td> 12320 <td valign="top">1'b1 - lcs state is CM 1'b0 - not</td> 12321 </tr> 12322 <tr> 12323 <td valign="top" align="center"><a name="1.18.15.2"></a>1:1 12324 </td> 12325 <td valign="top">IS_DM</td> 12326 <td valign="top" align="center">ro</td> 12327 <td valign="top" align="center">0x0</td> 12328 <td valign="top">1'b1 - lcs state is DM 1'b0 - not</td> 12329 </tr> 12330 <tr> 12331 <td valign="top" align="center"><a name="1.18.15.3"></a>2:2 12332 </td> 12333 <td valign="top">IS_SECURE</td> 12334 <td valign="top" align="center">ro</td> 12335 <td valign="top" align="center">0x0</td> 12336 <td valign="top">1'b1 - lcs state is SECURE 1'b0 - not</td> 12337 </tr> 12338 <tr> 12339 <td valign="top" align="center"><a name="1.18.15.4"></a>3:3 12340 </td> 12341 <td valign="top">IS_RMA</td> 12342 <td valign="top" align="center">ro</td> 12343 <td valign="top" align="center">0x0</td> 12344 <td valign="top">1'b1 - lcs state is RMA 1'b0 - not</td> 12345 </tr> 12346 <tr> 12347 <td valign="top" align="center"><a name="1.18.15.5"></a>31:4 12348 </td> 12349 <td valign="top">RESERVED</td> 12350 <td valign="top" align="center">ro</td> 12351 <td valign="top" align="center">0x0</td> 12352 <td valign="top">28'b0</td> 12353 </tr> 12354</table><a name="1.18.16"></a><br>1.18.16 : <b>Reg : ENV_FPGA_DCU_EN</b> : 0x060005444<br><b>reg sep address</b> : <b> reg host address</b> : <br>read the lcs states if it is CM DM SECURED or RMA <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12355 <tr> 12356 <td colspan="32" align="center">ENV_FPGA_DCU_EN</td> 12357 </tr> 12358 <tr></tr> 12359</table> 12360<table border="1" width="800"> 12361 <tr> 12362 <td width="40"><b>bits</b></td> 12363 <td width="100"><b>Field name</b></td> 12364 <td width="20"><b>permission</b></td> 12365 <td width="40"><b>default</b></td> 12366 <td width="600"><b>Description</b></td> 12367 </tr> 12368 <tr> 12369 <td valign="top" align="center"><a name="1.18.16.1"></a>31:0 12370 </td> 12371 <td valign="top">DCU_EN</td> 12372 <td valign="top" align="center">ro</td> 12373 <td valign="top" align="center">0x0</td> 12374 <td valign="top">Every bit in this sets of bits sets the matching dcu_en signal to a single dcu.</td> 12375 </tr> 12376</table><a name="1.18.17"></a><br>1.18.17 : <b>Reg : ENV_FPGA_CC_LCS_IS_VALID</b> : 0x060005448<br><b>reg sep address</b> : <b> reg host address</b> : <br>boot process finished reading LCS from NVM and write it to LCS register<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12377 <tr> 12378 <td colspan="32" align="center">ENV_FPGA_CC_LCS_IS_VALID</td> 12379 </tr> 12380 <tr></tr> 12381</table> 12382<table border="1" width="800"> 12383 <tr> 12384 <td width="40"><b>bits</b></td> 12385 <td width="100"><b>Field name</b></td> 12386 <td width="20"><b>permission</b></td> 12387 <td width="40"><b>default</b></td> 12388 <td width="600"><b>Description</b></td> 12389 </tr> 12390 <tr> 12391 <td valign="top" align="center"><a name="1.18.17.1"></a>0:0 12392 </td> 12393 <td valign="top">LCS_IS_VALID</td> 12394 <td valign="top" align="center">ro</td> 12395 <td valign="top" align="center">0x0</td> 12396 <td valign="top">LCS data is valid</td> 12397 </tr> 12398 <tr> 12399 <td valign="top" align="center"><a name="1.18.17.2"></a>31:1 12400 </td> 12401 <td valign="top">RESERVED</td> 12402 <td valign="top" align="center">ro</td> 12403 <td valign="top" align="center">0x0</td> 12404 <td valign="top">31'b0</td> 12405 </tr> 12406</table><a name="1.18.18"></a><br>1.18.18 : <b>Reg : ENV_FPGA_POWER_DOWN</b> : 0x060005478<br><b>reg sep address</b> : <b> reg host address</b> : <br>ENV_POWER_DOWN change bus to X's in DX simulations ONLY !<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12407 <tr> 12408 <td colspan="32" align="center">ENV_FPGA_POWER_DOWN</td> 12409 </tr> 12410 <tr></tr> 12411</table> 12412<table border="1" width="800"> 12413 <tr> 12414 <td width="40"><b>bits</b></td> 12415 <td width="100"><b>Field name</b></td> 12416 <td width="20"><b>permission</b></td> 12417 <td width="40"><b>default</b></td> 12418 <td width="600"><b>Description</b></td> 12419 </tr> 12420 <tr> 12421 <td valign="top" align="center"><a name="1.18.18.1"></a>31:0 12422 </td> 12423 <td valign="top">ENV_POWER_DOWN</td> 12424 <td valign="top" align="center">wo</td> 12425 <td valign="top" align="center">0x0</td> 12426 <td valign="top">write pulse of power down indication. Used for Internal DX simulations ONLY !</td> 12427 </tr> 12428</table><a name="1.18.19"></a><br>1.18.19 : <b>Reg : ENV_FPGA_DCU_H_EN</b> : 0x060005484<br><b>reg sep address</b> : <b> reg host address</b> : <br>read the lcs states if it is CM DM SECURED or RMA <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12429 <tr> 12430 <td colspan="32" align="center">ENV_FPGA_DCU_H_EN</td> 12431 </tr> 12432 <tr></tr> 12433</table> 12434<table border="1" width="800"> 12435 <tr> 12436 <td width="40"><b>bits</b></td> 12437 <td width="100"><b>Field name</b></td> 12438 <td width="20"><b>permission</b></td> 12439 <td width="40"><b>default</b></td> 12440 <td width="600"><b>Description</b></td> 12441 </tr> 12442 <tr> 12443 <td valign="top" align="center"><a name="1.18.19.1"></a>31:0 12444 </td> 12445 <td valign="top">DCU_EN</td> 12446 <td valign="top" align="center">ro</td> 12447 <td valign="top" align="center">0x0</td> 12448 <td valign="top">Every bit in this sets of bits sets the matching dcu_en signal to a single dcu.</td> 12449 </tr> 12450</table><a name="1.18.20"></a><br>1.18.20 : <b>Reg : ENV_FPGA_VERSION</b> : 0x060005488<br><b>reg sep address</b> : <b> reg host address</b> : <br>version of FPGA <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12451 <tr> 12452 <td colspan="32" align="center">ENV_FPGA_VERSION</td> 12453 </tr> 12454 <tr></tr> 12455</table> 12456<table border="1" width="800"> 12457 <tr> 12458 <td width="40"><b>bits</b></td> 12459 <td width="100"><b>Field name</b></td> 12460 <td width="20"><b>permission</b></td> 12461 <td width="40"><b>default</b></td> 12462 <td width="600"><b>Description</b></td> 12463 </tr> 12464 <tr> 12465 <td valign="top" align="center"><a name="1.18.20.1"></a>31:0 12466 </td> 12467 <td valign="top">FPGA_VERSION</td> 12468 <td valign="top" align="center">ro</td> 12469 <td valign="top" align="center">0x0</td> 12470 <td valign="top">Define the FPGA version.</td> 12471 </tr> 12472</table><a name="1.18.21"></a><br>1.18.21 : <b>Reg : ENV_FPGA_ROSC_WRITE</b> : 0x06000548C<br><b>reg sep address</b> : <b> reg host address</b> : <br>ROSC write select<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12473 <tr> 12474 <td colspan="32" align="center">ENV_FPGA_ROSC_WRITE</td> 12475 </tr> 12476 <tr></tr> 12477</table> 12478<table border="1" width="800"> 12479 <tr> 12480 <td width="40"><b>bits</b></td> 12481 <td width="100"><b>Field name</b></td> 12482 <td width="20"><b>permission</b></td> 12483 <td width="40"><b>default</b></td> 12484 <td width="600"><b>Description</b></td> 12485 </tr> 12486 <tr> 12487 <td valign="top" align="center"><a name="1.18.21.1"></a>0:0 12488 </td> 12489 <td valign="top">ROSC_PSEL</td> 12490 <td valign="top" align="center">wo</td> 12491 <td valign="top" align="center">0x0</td> 12492 <td valign="top">rosc psel</td> 12493 </tr> 12494 <tr> 12495 <td valign="top" align="center"><a name="1.18.21.2"></a>31:1 12496 </td> 12497 <td valign="top">RESERVED</td> 12498 <td valign="top" align="center">wo</td> 12499 <td valign="top" align="center">0x0</td> 12500 <td valign="top">31'b0</td> 12501 </tr> 12502</table><a name="1.18.22"></a><br>1.18.22 : <b>Reg : ENV_FPGA_ROSC_ADDR</b> : 0x060005490<br><b>reg sep address</b> : <b> reg host address</b> : <br>ROSC ADDRRESS<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12503 <tr> 12504 <td colspan="32" align="center">ENV_FPGA_ROSC_ADDR</td> 12505 </tr> 12506 <tr></tr> 12507</table> 12508<table border="1" width="800"> 12509 <tr> 12510 <td width="40"><b>bits</b></td> 12511 <td width="100"><b>Field name</b></td> 12512 <td width="20"><b>permission</b></td> 12513 <td width="40"><b>default</b></td> 12514 <td width="600"><b>Description</b></td> 12515 </tr> 12516 <tr> 12517 <td valign="top" align="center"><a name="1.18.22.1"></a>7:0 12518 </td> 12519 <td valign="top">ROSC_ADDR</td> 12520 <td valign="top" align="center">wo</td> 12521 <td valign="top" align="center">0x0</td> 12522 <td valign="top">rosc address</td> 12523 </tr> 12524 <tr> 12525 <td valign="top" align="center"><a name="1.18.22.2"></a>31:8 12526 </td> 12527 <td valign="top">RESERVED</td> 12528 <td valign="top" align="center">wo</td> 12529 <td valign="top" align="center">0x0</td> 12530 <td valign="top">24'b0</td> 12531 </tr> 12532</table><a name="1.18.23"></a><br>1.18.23 : <b>Reg : ENV_FPGA_RESET_SESSION_KEY</b> : 0x060005494<br><b>reg sep address</b> : <b> reg host address</b> : <br>Reset the session key<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12533 <tr> 12534 <td colspan="32" align="center">ENV_FPGA_RESET_SESSION_KEY</td> 12535 </tr> 12536 <tr></tr> 12537</table> 12538<table border="1" width="800"> 12539 <tr> 12540 <td width="40"><b>bits</b></td> 12541 <td width="100"><b>Field name</b></td> 12542 <td width="20"><b>permission</b></td> 12543 <td width="40"><b>default</b></td> 12544 <td width="600"><b>Description</b></td> 12545 </tr> 12546 <tr> 12547 <td valign="top" align="center"><a name="1.18.23.1"></a>0:0 12548 </td> 12549 <td valign="top">RESET_SESSION_KEY</td> 12550 <td valign="top" align="center">wo</td> 12551 <td valign="top" align="center">0x0</td> 12552 <td valign="top">async reset for the session key - (fpga env only)</td> 12553 </tr> 12554 <tr> 12555 <td valign="top" align="center"><a name="1.18.23.2"></a>31:1 12556 </td> 12557 <td valign="top">RESERVED</td> 12558 <td valign="top" align="center">wo</td> 12559 <td valign="top" align="center">0x0</td> 12560 <td valign="top">31'b0</td> 12561 </tr> 12562</table><a name="1.18.24"></a><br>1.18.24 : <b>Reg : ENV_FPGA_SESSION_KEY_0</b> : 0x0600054A0<br><b>reg sep address</b> : <b> reg host address</b> : <br>Session key 0<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12563 <tr> 12564 <td colspan="32" align="center">ENV_FPGA_SESSION_KEY_0</td> 12565 </tr> 12566 <tr></tr> 12567</table> 12568<table border="1" width="800"> 12569 <tr> 12570 <td width="40"><b>bits</b></td> 12571 <td width="100"><b>Field name</b></td> 12572 <td width="20"><b>permission</b></td> 12573 <td width="40"><b>default</b></td> 12574 <td width="600"><b>Description</b></td> 12575 </tr> 12576 <tr> 12577 <td valign="top" align="center"><a name="1.18.24.1"></a>31:0 12578 </td> 12579 <td valign="top">SESSION_KEY_0</td> 12580 <td valign="top" align="center">wo</td> 12581 <td valign="top" align="center">0x0</td> 12582 <td valign="top">Session key 0</td> 12583 </tr> 12584</table><a name="1.18.25"></a><br>1.18.25 : <b>Reg : ENV_FPGA_SESSION_KEY_1</b> : 0x0600054A4<br><b>reg sep address</b> : <b> reg host address</b> : <br>Session key 0<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12585 <tr> 12586 <td colspan="32" align="center">ENV_FPGA_SESSION_KEY_1</td> 12587 </tr> 12588 <tr></tr> 12589</table> 12590<table border="1" width="800"> 12591 <tr> 12592 <td width="40"><b>bits</b></td> 12593 <td width="100"><b>Field name</b></td> 12594 <td width="20"><b>permission</b></td> 12595 <td width="40"><b>default</b></td> 12596 <td width="600"><b>Description</b></td> 12597 </tr> 12598 <tr> 12599 <td valign="top" align="center"><a name="1.18.25.1"></a>31:0 12600 </td> 12601 <td valign="top">SESSION_KEY_1</td> 12602 <td valign="top" align="center">wo</td> 12603 <td valign="top" align="center">0x0</td> 12604 <td valign="top">Session key 1</td> 12605 </tr> 12606</table><a name="1.18.26"></a><br>1.18.26 : <b>Reg : ENV_FPGA_SESSION_KEY_2</b> : 0x0600054A8<br><b>reg sep address</b> : <b> reg host address</b> : <br>Session key 1<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12607 <tr> 12608 <td colspan="32" align="center">ENV_FPGA_SESSION_KEY_2</td> 12609 </tr> 12610 <tr></tr> 12611</table> 12612<table border="1" width="800"> 12613 <tr> 12614 <td width="40"><b>bits</b></td> 12615 <td width="100"><b>Field name</b></td> 12616 <td width="20"><b>permission</b></td> 12617 <td width="40"><b>default</b></td> 12618 <td width="600"><b>Description</b></td> 12619 </tr> 12620 <tr> 12621 <td valign="top" align="center"><a name="1.18.26.1"></a>31:0 12622 </td> 12623 <td valign="top">SESSION_KEY_2</td> 12624 <td valign="top" align="center">wo</td> 12625 <td valign="top" align="center">0x0</td> 12626 <td valign="top">Session key 2</td> 12627 </tr> 12628</table><a name="1.18.27"></a><br>1.18.27 : <b>Reg : ENV_FPGA_SESSION_KEY_3</b> : 0x0600054AC<br><b>reg sep address</b> : <b> reg host address</b> : <br>Session key 1<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12629 <tr> 12630 <td colspan="32" align="center">ENV_FPGA_SESSION_KEY_3</td> 12631 </tr> 12632 <tr></tr> 12633</table> 12634<table border="1" width="800"> 12635 <tr> 12636 <td width="40"><b>bits</b></td> 12637 <td width="100"><b>Field name</b></td> 12638 <td width="20"><b>permission</b></td> 12639 <td width="40"><b>default</b></td> 12640 <td width="600"><b>Description</b></td> 12641 </tr> 12642 <tr> 12643 <td valign="top" align="center"><a name="1.18.27.1"></a>31:0 12644 </td> 12645 <td valign="top">SESSION_KEY_3</td> 12646 <td valign="top" align="center">wo</td> 12647 <td valign="top" align="center">0x0</td> 12648 <td valign="top">Session key 3</td> 12649 </tr> 12650</table><a name="1.18.28"></a><br>1.18.28 : <b>Reg : ENV_FPGA_SESSION_KEY_VALID</b> : 0x0600054B0<br><b>reg sep address</b> : <b> reg host address</b> : <br>Session key valid<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12651 <tr> 12652 <td colspan="32" align="center">ENV_FPGA_SESSION_KEY_VALID</td> 12653 </tr> 12654 <tr></tr> 12655</table> 12656<table border="1" width="800"> 12657 <tr> 12658 <td width="40"><b>bits</b></td> 12659 <td width="100"><b>Field name</b></td> 12660 <td width="20"><b>permission</b></td> 12661 <td width="40"><b>default</b></td> 12662 <td width="600"><b>Description</b></td> 12663 </tr> 12664 <tr> 12665 <td valign="top" align="center"><a name="1.18.28.1"></a>0:0 12666 </td> 12667 <td valign="top">SESSION_KEY_VALID</td> 12668 <td valign="top" align="center">wo</td> 12669 <td valign="top" align="center">0x0</td> 12670 <td valign="top">Session key valid</td> 12671 </tr> 12672 <tr> 12673 <td valign="top" align="center"><a name="1.18.28.2"></a>31:1 12674 </td> 12675 <td valign="top">RESERVED</td> 12676 <td valign="top" align="center">wo</td> 12677 <td valign="top" align="center">0x0</td> 12678 <td valign="top">reserved</td> 12679 </tr> 12680</table><a name="1.18.29"></a><br>1.18.29 : <b>Reg : ENV_FPGA_SPIDEN</b> : 0x0600054D0<br><b>reg sep address</b> : <b> reg host address</b> : <br>spiden override<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12681 <tr> 12682 <td colspan="32" align="center">ENV_FPGA_SPIDEN</td> 12683 </tr> 12684 <tr></tr> 12685</table> 12686<table border="1" width="800"> 12687 <tr> 12688 <td width="40"><b>bits</b></td> 12689 <td width="100"><b>Field name</b></td> 12690 <td width="20"><b>permission</b></td> 12691 <td width="40"><b>default</b></td> 12692 <td width="600"><b>Description</b></td> 12693 </tr> 12694 <tr> 12695 <td valign="top" align="center"><a name="1.18.29.1"></a>0:0 12696 </td> 12697 <td valign="top">SPIDEN</td> 12698 <td valign="top" align="center">rw</td> 12699 <td valign="top" align="center">0x0</td> 12700 <td valign="top">spiden value</td> 12701 </tr> 12702 <tr> 12703 <td valign="top" align="center"><a name="1.18.29.2"></a>31:1 12704 </td> 12705 <td valign="top">RESERVED</td> 12706 <td valign="top" align="center">rw</td> 12707 <td valign="top" align="center">0x0</td> 12708 <td valign="top">reserved</td> 12709 </tr> 12710</table><a name="1.18.30"></a><br>1.18.30 : <b>Reg : ENV_FPGA_AXIM_USER_PARAMS</b> : 0x060005600<br><b>reg sep address</b> : <b> reg host address</b> : <br>axim master cache coherency configuration override<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12711 <tr> 12712 <td colspan="32" align="center">ENV_FPGA_AXIM_USER_PARAMS</td> 12713 </tr> 12714 <tr></tr> 12715</table> 12716<table border="1" width="800"> 12717 <tr> 12718 <td width="40"><b>bits</b></td> 12719 <td width="100"><b>Field name</b></td> 12720 <td width="20"><b>permission</b></td> 12721 <td width="40"><b>default</b></td> 12722 <td width="600"><b>Description</b></td> 12723 </tr> 12724 <tr> 12725 <td valign="top" align="center"><a name="1.18.30.1"></a>4:0 12726 </td> 12727 <td valign="top">ARUSER</td> 12728 <td valign="top" align="center">rw</td> 12729 <td valign="top" align="center">0x0</td> 12730 <td valign="top">aruser override value</td> 12731 </tr> 12732 <tr> 12733 <td valign="top" align="center"><a name="1.18.30.2"></a>9:5 12734 </td> 12735 <td valign="top">AWUSER</td> 12736 <td valign="top" align="center">rw</td> 12737 <td valign="top" align="center">0x0</td> 12738 <td valign="top">awuser override value</td> 12739 </tr> 12740 <tr> 12741 <td valign="top" align="center"><a name="1.18.30.3"></a>31:10 12742 </td> 12743 <td valign="top">RESERVED</td> 12744 <td valign="top" align="center">rw</td> 12745 <td valign="top" align="center">0x0</td> 12746 <td valign="top">reserved</td> 12747 </tr> 12748</table><a name="1.18.31"></a><br>1.18.31 : <b>Reg : ENV_FPGA_SECURITY_MODE_OVERRIDE</b> : 0x060005604<br><b>reg sep address</b> : <b> reg host address</b> : <br>axim master prot override <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12749 <tr> 12750 <td colspan="32" align="center">ENV_FPGA_SECURITY_MODE_OVERRIDE</td> 12751 </tr> 12752 <tr></tr> 12753</table> 12754<table border="1" width="800"> 12755 <tr> 12756 <td width="40"><b>bits</b></td> 12757 <td width="100"><b>Field name</b></td> 12758 <td width="20"><b>permission</b></td> 12759 <td width="40"><b>default</b></td> 12760 <td width="600"><b>Description</b></td> 12761 </tr> 12762 <tr> 12763 <td valign="top" align="center"><a name="1.18.31.1"></a>0:0 12764 </td> 12765 <td valign="top">AWPROT_NS_BIT</td> 12766 <td valign="top" align="center">rw</td> 12767 <td valign="top" align="center">0x0</td> 12768 <td valign="top">AWPROT override value</td> 12769 </tr> 12770 <tr> 12771 <td valign="top" align="center"><a name="1.18.31.2"></a>1:1 12772 </td> 12773 <td valign="top">AWPROT_NS_OVERRIDE</td> 12774 <td valign="top" align="center">rw</td> 12775 <td valign="top" align="center">0x0</td> 12776 <td valign="top">AWPROT override enable</td> 12777 </tr> 12778 <tr> 12779 <td valign="top" align="center"><a name="1.18.31.3"></a>2:2 12780 </td> 12781 <td valign="top">ARPROT_NS_BIT</td> 12782 <td valign="top" align="center">rw</td> 12783 <td valign="top" align="center">0x0</td> 12784 <td valign="top">ARPROT override value</td> 12785 </tr> 12786 <tr> 12787 <td valign="top" align="center"><a name="1.18.31.4"></a>3:3 12788 </td> 12789 <td valign="top">ARPROT_NS_OVERRIDE</td> 12790 <td valign="top" align="center">rw</td> 12791 <td valign="top" align="center">0x0</td> 12792 <td valign="top">ARPROT override enable</td> 12793 </tr> 12794 <tr> 12795 <td valign="top" align="center"><a name="1.18.31.5"></a>31:4 12796 </td> 12797 <td valign="top">RESERVED</td> 12798 <td valign="top" align="center">rw</td> 12799 <td valign="top" align="center">0x0</td> 12800 <td valign="top">reserved</td> 12801 </tr> 12802</table><a name="1.18.32"></a><br>1.18.32 : <b>Reg : ENV_FPGA_SRAM_ENABLE</b> : 0x060005608<br><b>reg sep address</b> : <b> reg host address</b> : <br>SRAM enable<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12803 <tr> 12804 <td colspan="32" align="center">ENV_FPGA_SRAM_ENABLE</td> 12805 </tr> 12806 <tr></tr> 12807</table> 12808<table border="1" width="800"> 12809 <tr> 12810 <td width="40"><b>bits</b></td> 12811 <td width="100"><b>Field name</b></td> 12812 <td width="20"><b>permission</b></td> 12813 <td width="40"><b>default</b></td> 12814 <td width="600"><b>Description</b></td> 12815 </tr> 12816 <tr> 12817 <td valign="top" align="center"><a name="1.18.32.1"></a>0:0 12818 </td> 12819 <td valign="top">SRAM_ENABLE</td> 12820 <td valign="top" align="center">wo</td> 12821 <td valign="top" align="center">0x0</td> 12822 <td valign="top">sram enable bit</td> 12823 </tr> 12824 <tr> 12825 <td valign="top" align="center"><a name="1.18.32.2"></a>31:1 12826 </td> 12827 <td valign="top">RESERVED</td> 12828 <td valign="top" align="center">wo</td> 12829 <td valign="top" align="center">0x0</td> 12830 <td valign="top">reserved</td> 12831 </tr> 12832</table><a name="1.18.33"></a><br>1.18.33 : <b>Reg : ENV_FPGA_APB_FIPS_ADDR</b> : 0x060005650<br><b>reg sep address</b> : <b> reg host address</b> : <br>the secure host register offset for fips access match<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12833 <tr> 12834 <td colspan="32" align="center">ENV_FPGA_APB_FIPS_ADDR</td> 12835 </tr> 12836 <tr></tr> 12837</table> 12838<table border="1" width="800"> 12839 <tr> 12840 <td width="40"><b>bits</b></td> 12841 <td width="100"><b>Field name</b></td> 12842 <td width="20"><b>permission</b></td> 12843 <td width="40"><b>default</b></td> 12844 <td width="600"><b>Description</b></td> 12845 </tr> 12846 <tr> 12847 <td valign="top" align="center"><a name="1.18.33.1"></a>11:0 12848 </td> 12849 <td valign="top">FIPS_ADDR</td> 12850 <td valign="top" align="center">wo</td> 12851 <td valign="top" align="center">0x0</td> 12852 <td valign="top">SECURE HOST FIPS register offset</td> 12853 </tr> 12854 <tr> 12855 <td valign="top" align="center"><a name="1.18.33.2"></a>31:12 12856 </td> 12857 <td valign="top">RESERVED</td> 12858 <td valign="top" align="center">wo</td> 12859 <td valign="top" align="center">0x0</td> 12860 <td valign="top">reserved</td> 12861 </tr> 12862</table><a name="1.18.34"></a><br>1.18.34 : <b>Reg : ENV_FPGA_APB_FIPS_VAL</b> : 0x060005654<br><b>reg sep address</b> : <b> reg host address</b> : <br>the secure host write data for fips access match<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12863 <tr> 12864 <td colspan="32" align="center">ENV_FPGA_APB_FIPS_VAL</td> 12865 </tr> 12866 <tr></tr> 12867</table> 12868<table border="1" width="800"> 12869 <tr> 12870 <td width="40"><b>bits</b></td> 12871 <td width="100"><b>Field name</b></td> 12872 <td width="20"><b>permission</b></td> 12873 <td width="40"><b>default</b></td> 12874 <td width="600"><b>Description</b></td> 12875 </tr> 12876 <tr> 12877 <td valign="top" align="center"><a name="1.18.34.1"></a>31:0 12878 </td> 12879 <td valign="top">FIPS_DATA</td> 12880 <td valign="top" align="center">wo</td> 12881 <td valign="top" align="center">0x0</td> 12882 <td valign="top">SECURE HOST FIPS data</td> 12883 </tr> 12884</table><a name="1.18.35"></a><br>1.18.35 : <b>Reg : ENV_FPGA_APB_FIPS_MASK</b> : 0x060005658<br><b>reg sep address</b> : <b> reg host address</b> : <br>the secure host write data mask for fips access match<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12885 <tr> 12886 <td colspan="32" align="center">ENV_FPGA_APB_FIPS_MASK</td> 12887 </tr> 12888 <tr></tr> 12889</table> 12890<table border="1" width="800"> 12891 <tr> 12892 <td width="40"><b>bits</b></td> 12893 <td width="100"><b>Field name</b></td> 12894 <td width="20"><b>permission</b></td> 12895 <td width="40"><b>default</b></td> 12896 <td width="600"><b>Description</b></td> 12897 </tr> 12898 <tr> 12899 <td valign="top" align="center"><a name="1.18.35.1"></a>31:0 12900 </td> 12901 <td valign="top">FIPS_MASK</td> 12902 <td valign="top" align="center">wo</td> 12903 <td valign="top" align="center">0x0</td> 12904 <td valign="top">SECURE HOST FIPS data mask</td> 12905 </tr> 12906</table><a name="1.18.36"></a><br>1.18.36 : <b>Reg : ENV_FPGA_APB_FIPS_CNT</b> : 0x06000565C<br><b>reg sep address</b> : <b> reg host address</b> : <br>the secure host fips access counter thershold <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12907 <tr> 12908 <td colspan="32" align="center">ENV_FPGA_APB_FIPS_CNT</td> 12909 </tr> 12910 <tr></tr> 12911</table> 12912<table border="1" width="800"> 12913 <tr> 12914 <td width="40"><b>bits</b></td> 12915 <td width="100"><b>Field name</b></td> 12916 <td width="20"><b>permission</b></td> 12917 <td width="40"><b>default</b></td> 12918 <td width="600"><b>Description</b></td> 12919 </tr> 12920 <tr> 12921 <td valign="top" align="center"><a name="1.18.36.1"></a>31:0 12922 </td> 12923 <td valign="top">FIPS_CNT</td> 12924 <td valign="top" align="center">wo</td> 12925 <td valign="top" align="center">0x0</td> 12926 <td valign="top">SECURE HOST FIPS CNT</td> 12927 </tr> 12928</table><a name="1.18.37"></a><br>1.18.37 : <b>Reg : ENV_FPGA_APB_FIPS_NEW_ADDR</b> : 0x060005660<br><b>reg sep address</b> : <b> reg host address</b> : <br>the secure host register offset of the new register after FIPS cnt reached<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12929 <tr> 12930 <td colspan="32" align="center">ENV_FPGA_APB_FIPS_NEW_ADDR</td> 12931 </tr> 12932 <tr></tr> 12933</table> 12934<table border="1" width="800"> 12935 <tr> 12936 <td width="40"><b>bits</b></td> 12937 <td width="100"><b>Field name</b></td> 12938 <td width="20"><b>permission</b></td> 12939 <td width="40"><b>default</b></td> 12940 <td width="600"><b>Description</b></td> 12941 </tr> 12942 <tr> 12943 <td valign="top" align="center"><a name="1.18.37.1"></a>11:0 12944 </td> 12945 <td valign="top">FIPS_NEW_ADDR</td> 12946 <td valign="top" align="center">wo</td> 12947 <td valign="top" align="center">0x0</td> 12948 <td valign="top">SECURE HOST FIPS NEW register offset</td> 12949 </tr> 12950 <tr> 12951 <td valign="top" align="center"><a name="1.18.37.2"></a>31:12 12952 </td> 12953 <td valign="top">RESERVED</td> 12954 <td valign="top" align="center">wo</td> 12955 <td valign="top" align="center">0x0</td> 12956 <td valign="top">reserved</td> 12957 </tr> 12958</table><a name="1.18.38"></a><br>1.18.38 : <b>Reg : ENV_FPGA_APB_FIPS_NEW_VAL</b> : 0x060005664<br><b>reg sep address</b> : <b> reg host address</b> : <br>the secure host new write data after fips cnt reached<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12959 <tr> 12960 <td colspan="32" align="center">ENV_FPGA_APB_FIPS_NEW_VAL</td> 12961 </tr> 12962 <tr></tr> 12963</table> 12964<table border="1" width="800"> 12965 <tr> 12966 <td width="40"><b>bits</b></td> 12967 <td width="100"><b>Field name</b></td> 12968 <td width="20"><b>permission</b></td> 12969 <td width="40"><b>default</b></td> 12970 <td width="600"><b>Description</b></td> 12971 </tr> 12972 <tr> 12973 <td valign="top" align="center"><a name="1.18.38.1"></a>31:0 12974 </td> 12975 <td valign="top">FIPS_DATA</td> 12976 <td valign="top" align="center">wo</td> 12977 <td valign="top" align="center">0x0</td> 12978 <td valign="top">SECURE HOST FIPS NEW data</td> 12979 </tr> 12980</table><a name="1.18.39"></a><br>1.18.39 : <b>Reg : ENV_FPGA_APB_PPROT_OVERRIDE</b> : 0x060005668<br><b>reg sep address</b> : <b> reg host address</b> : <br>apbs pprot override <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 12981 <tr> 12982 <td colspan="32" align="center">ENV_FPGA_APB_PPROT_OVERRIDE</td> 12983 </tr> 12984 <tr></tr> 12985</table> 12986<table border="1" width="800"> 12987 <tr> 12988 <td width="40"><b>bits</b></td> 12989 <td width="100"><b>Field name</b></td> 12990 <td width="20"><b>permission</b></td> 12991 <td width="40"><b>default</b></td> 12992 <td width="600"><b>Description</b></td> 12993 </tr> 12994 <tr> 12995 <td valign="top" align="center"><a name="1.18.39.1"></a>2:0 12996 </td> 12997 <td valign="top">PPROT_OVERRIDE_VAL</td> 12998 <td valign="top" align="center">rw</td> 12999 <td valign="top" align="center">0x0</td> 13000 <td valign="top">PPROT override value</td> 13001 </tr> 13002 <tr> 13003 <td valign="top" align="center"><a name="1.18.39.2"></a>3:3 13004 </td> 13005 <td valign="top">PPROT_OVERRIDE_CNTL</td> 13006 <td valign="top" align="center">rw</td> 13007 <td valign="top" align="center">0x0</td> 13008 <td valign="top">PPROT override control ;1 = ovveride</td> 13009 </tr> 13010 <tr> 13011 <td valign="top" align="center"><a name="1.18.39.3"></a>31:4 13012 </td> 13013 <td valign="top">RESERVED</td> 13014 <td valign="top" align="center">rw</td> 13015 <td valign="top" align="center">0x0</td> 13016 <td valign="top">ARPROT override value</td> 13017 </tr> 13018</table><a name="1.18.40"></a><br>1.18.40 : <b>Reg : ENV_FPGA_APBP_FIPS_ADDR</b> : 0x060005670<br><b>reg sep address</b> : <b> reg host address</b> : <br>the public host register offset for fips access match<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13019 <tr> 13020 <td colspan="32" align="center">ENV_FPGA_APBP_FIPS_ADDR</td> 13021 </tr> 13022 <tr></tr> 13023</table> 13024<table border="1" width="800"> 13025 <tr> 13026 <td width="40"><b>bits</b></td> 13027 <td width="100"><b>Field name</b></td> 13028 <td width="20"><b>permission</b></td> 13029 <td width="40"><b>default</b></td> 13030 <td width="600"><b>Description</b></td> 13031 </tr> 13032 <tr> 13033 <td valign="top" align="center"><a name="1.18.40.1"></a>11:0 13034 </td> 13035 <td valign="top">FIPS_ADDR</td> 13036 <td valign="top" align="center">wo</td> 13037 <td valign="top" align="center">0x0</td> 13038 <td valign="top">PUBLIC HOST FIPS register offset</td> 13039 </tr> 13040 <tr> 13041 <td valign="top" align="center"><a name="1.18.40.2"></a>31:12 13042 </td> 13043 <td valign="top">RESERVED</td> 13044 <td valign="top" align="center">wo</td> 13045 <td valign="top" align="center">0x0</td> 13046 <td valign="top">reserved</td> 13047 </tr> 13048</table><a name="1.18.41"></a><br>1.18.41 : <b>Reg : ENV_FPGA_APBP_FIPS_VAL</b> : 0x060005674<br><b>reg sep address</b> : <b> reg host address</b> : <br>the public host write data for fips access match<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13049 <tr> 13050 <td colspan="32" align="center">ENV_FPGA_APBP_FIPS_VAL</td> 13051 </tr> 13052 <tr></tr> 13053</table> 13054<table border="1" width="800"> 13055 <tr> 13056 <td width="40"><b>bits</b></td> 13057 <td width="100"><b>Field name</b></td> 13058 <td width="20"><b>permission</b></td> 13059 <td width="40"><b>default</b></td> 13060 <td width="600"><b>Description</b></td> 13061 </tr> 13062 <tr> 13063 <td valign="top" align="center"><a name="1.18.41.1"></a>31:0 13064 </td> 13065 <td valign="top">FIPS_DATA</td> 13066 <td valign="top" align="center">wo</td> 13067 <td valign="top" align="center">0x0</td> 13068 <td valign="top">PUBLIC HOST FIPS data</td> 13069 </tr> 13070</table><a name="1.18.42"></a><br>1.18.42 : <b>Reg : ENV_FPGA_APBP_FIPS_MASK</b> : 0x060005678<br><b>reg sep address</b> : <b> reg host address</b> : <br>the public host write data mask for fips access match<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13071 <tr> 13072 <td colspan="32" align="center">ENV_FPGA_APBP_FIPS_MASK</td> 13073 </tr> 13074 <tr></tr> 13075</table> 13076<table border="1" width="800"> 13077 <tr> 13078 <td width="40"><b>bits</b></td> 13079 <td width="100"><b>Field name</b></td> 13080 <td width="20"><b>permission</b></td> 13081 <td width="40"><b>default</b></td> 13082 <td width="600"><b>Description</b></td> 13083 </tr> 13084 <tr> 13085 <td valign="top" align="center"><a name="1.18.42.1"></a>31:0 13086 </td> 13087 <td valign="top">FIPS_MASK</td> 13088 <td valign="top" align="center">wo</td> 13089 <td valign="top" align="center">0x0</td> 13090 <td valign="top">PUBLIC HOST FIPS data mask</td> 13091 </tr> 13092</table><a name="1.18.43"></a><br>1.18.43 : <b>Reg : ENV_FPGA_APBP_FIPS_CNT</b> : 0x06000567C<br><b>reg sep address</b> : <b> reg host address</b> : <br>the public host fips access counter thershold <br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13093 <tr> 13094 <td colspan="32" align="center">ENV_FPGA_APBP_FIPS_CNT</td> 13095 </tr> 13096 <tr></tr> 13097</table> 13098<table border="1" width="800"> 13099 <tr> 13100 <td width="40"><b>bits</b></td> 13101 <td width="100"><b>Field name</b></td> 13102 <td width="20"><b>permission</b></td> 13103 <td width="40"><b>default</b></td> 13104 <td width="600"><b>Description</b></td> 13105 </tr> 13106 <tr> 13107 <td valign="top" align="center"><a name="1.18.43.1"></a>31:0 13108 </td> 13109 <td valign="top">FIPS_CNT</td> 13110 <td valign="top" align="center">wo</td> 13111 <td valign="top" align="center">0x0</td> 13112 <td valign="top">PUBLIC HOST FIPS CNT</td> 13113 </tr> 13114</table><a name="1.18.44"></a><br>1.18.44 : <b>Reg : ENV_FPGA_APBP_FIPS_NEW_ADDR</b> : 0x060005680<br><b>reg sep address</b> : <b> reg host address</b> : <br>the public host register offset of the new register after FIPS cnt reached<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13115 <tr> 13116 <td colspan="32" align="center">ENV_FPGA_APBP_FIPS_NEW_ADDR</td> 13117 </tr> 13118 <tr></tr> 13119</table> 13120<table border="1" width="800"> 13121 <tr> 13122 <td width="40"><b>bits</b></td> 13123 <td width="100"><b>Field name</b></td> 13124 <td width="20"><b>permission</b></td> 13125 <td width="40"><b>default</b></td> 13126 <td width="600"><b>Description</b></td> 13127 </tr> 13128 <tr> 13129 <td valign="top" align="center"><a name="1.18.44.1"></a>11:0 13130 </td> 13131 <td valign="top">FIPS_NEW_ADDR</td> 13132 <td valign="top" align="center">wo</td> 13133 <td valign="top" align="center">0x0</td> 13134 <td valign="top">PUBLIC HOST FIPS NEW register offset</td> 13135 </tr> 13136 <tr> 13137 <td valign="top" align="center"><a name="1.18.44.2"></a>31:12 13138 </td> 13139 <td valign="top">RESERVED</td> 13140 <td valign="top" align="center">wo</td> 13141 <td valign="top" align="center">0x0</td> 13142 <td valign="top">reserved</td> 13143 </tr> 13144</table><a name="1.18.45"></a><br>1.18.45 : <b>Reg : ENV_FPGA_APBP_FIPS_NEW_VAL</b> : 0x060005684<br><b>reg sep address</b> : <b> reg host address</b> : <br>the public host new write data after fips cnt reached<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13145 <tr> 13146 <td colspan="32" align="center">ENV_FPGA_APBP_FIPS_NEW_VAL</td> 13147 </tr> 13148 <tr></tr> 13149</table> 13150<table border="1" width="800"> 13151 <tr> 13152 <td width="40"><b>bits</b></td> 13153 <td width="100"><b>Field name</b></td> 13154 <td width="20"><b>permission</b></td> 13155 <td width="40"><b>default</b></td> 13156 <td width="600"><b>Description</b></td> 13157 </tr> 13158 <tr> 13159 <td valign="top" align="center"><a name="1.18.45.1"></a>31:0 13160 </td> 13161 <td valign="top">FIPS_DATA</td> 13162 <td valign="top" align="center">wo</td> 13163 <td valign="top" align="center">0x0</td> 13164 <td valign="top">PUBLIC HOST FIPS NEW data</td> 13165 </tr> 13166</table><a name="1.18.46"></a><br>1.18.46 : <b>Reg : ENV_FPGA_AO_CC_GPPC</b> : 0x060005700<br><b>reg sep address</b> : <b> reg host address</b> : <br>holds the AO_CC_GPPC value from AO<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13167 <tr> 13168 <td colspan="32" align="center">ENV_FPGA_AO_CC_GPPC</td> 13169 </tr> 13170 <tr></tr> 13171</table> 13172<table border="1" width="800"> 13173 <tr> 13174 <td width="40"><b>bits</b></td> 13175 <td width="100"><b>Field name</b></td> 13176 <td width="20"><b>permission</b></td> 13177 <td width="40"><b>default</b></td> 13178 <td width="600"><b>Description</b></td> 13179 </tr> 13180 <tr> 13181 <td valign="top" align="center"><a name="1.18.46.1"></a>7:0 13182 </td> 13183 <td valign="top">AO_CC_GPPC</td> 13184 <td valign="top" align="center">ro</td> 13185 <td valign="top" align="center">0x0</td> 13186 <td valign="top">AO_CC_GPPC</td> 13187 </tr> 13188 <tr> 13189 <td valign="top" align="center"><a name="1.18.46.2"></a>31:8 13190 </td> 13191 <td valign="top">RESERVED</td> 13192 <td valign="top" align="center">ro</td> 13193 <td valign="top" align="center">0x0</td> 13194 <td valign="top">reserved</td> 13195 </tr> 13196</table><a href="#1.18">(top of block)</a><a name="1.19"></a><br><table frame="border" width="95%" BORDERCOLOR="#993333"> 13197 <td><b><font color="#000000">1.19 : Block: ENV_PERF_RAM_BASE</font></b></td> 13198 <td align="right"><font color="#000000">0x060006000</font></td> 13199</table><br><a name="1.19.1"></a><br>1.19.1 : <b>Reg : ENV_PERF_RAM_BASE</b> : 0x060006000<br><b>reg sep address</b> : <b> reg host address</b> : <br>Performance RAM base address Data read from performance RAM<br>Note: This is a special register, affected by internal logic. Test result of this register is NA.<br><table border="1" bgcolor="#EEEEEE" width="800"> 13200 <tr> 13201 <td colspan="32" align="center">ENV_PERF_RAM_BASE</td> 13202 </tr> 13203 <tr></tr> 13204</table> 13205<table border="1" width="800"> 13206 <tr> 13207 <td width="40"><b>bits</b></td> 13208 <td width="100"><b>Field name</b></td> 13209 <td width="20"><b>permission</b></td> 13210 <td width="40"><b>default</b></td> 13211 <td width="600"><b>Description</b></td> 13212 </tr> 13213 <tr> 13214 <td valign="top" align="center"><a name="1.19.1.1"></a>31:0 13215 </td> 13216 <td valign="top">PERF_RAM_D</td> 13217 <td valign="top" align="center">ro</td> 13218 <td valign="top" align="center">0x0</td> 13219 <td valign="top">Data read from performance RAM</td> 13220 </tr> 13221</table><a href="#1.19">(top of block)</a><br><a href="#1">(top of chip)</a><hr WIDTH="100%" SIZE="3" NOSHADE="1">***** Copyright 2012 All Rights Reserved. *****
