1#-------------------------------------------------------------------------------
2# Copyright (c) 2022, Arm Limited. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6#-------------------------------------------------------------------------------
7
8set(CONFIG_TFM_ENABLE_FP                OFF         CACHE BOOL      "Enable/disable FP usage")
9set(CONFIG_TFM_ENABLE_MVE               OFF         CACHE BOOL      "Enable/disable integer MVE usage")
10set(CONFIG_TFM_ENABLE_MVE_FP            OFF         CACHE BOOL      "Enable/disable floating-point MVE usage")
11
12if (CONFIG_TFM_ENABLE_FP OR CONFIG_TFM_ENABLE_MVE OR CONFIG_TFM_ENABLE_MVE_FP)
13    # Set float abi to enable hardware floating-point instructions and hardware floating-point linkage.
14    set(CONFIG_TFM_FLOAT_ABI            "hard")
15    set(CONFIG_TFM_ENABLE_CP10CP11      ON          CACHE BOOL            "Make FPU and MVE operational when SPE and/or NSPE require FPU or MVE usage. This alone only enables the coprocessors CP10-CP11, whereas CONFIG_TFM_FLOAT_ABI=hard along with  CONFIG_TFM_ENABLE_FP, CONFIG_TFM_ENABLE_MVE or CONFIG_TFM_ENABLE_MVE_FP compiles the code with hardware FP or MVE instructions and ABI.")
16    set(CONFIG_TFM_LAZY_STACKING        ON          CACHE BOOL            "Enable/disable lazy stacking")
17else()
18    # Set float abi soft, meaning software library functions for floating-point operations and software floating-point linkage.
19    set(CONFIG_TFM_FLOAT_ABI           "soft")
20    set(CONFIG_TFM_ENABLE_CP10CP11      OFF         CACHE BOOL            "Make FPU and MVE operational when SPE and/or NSPE require FPU or MVE usage. This alone only enables the coprocessors CP10-CP11, whereas CONFIG_TFM_FLOAT_ABI=hard along with  CONFIG_TFM_ENABLE_FP, CONFIG_TFM_ENABLE_MVE or CONFIG_TFM_ENABLE_MVE_FP compiles the code with hardware FP or MVE instructions and ABI.")
21    set(CONFIG_TFM_LAZY_STACKING        OFF         CACHE BOOL            "Enable/disable lazy stacking")
22endif()
23
24