1 /*
2  * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3  * Copyright 2019-2020 NXP. All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *     http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 
18 #ifndef __REGION_DEFS_H__
19 #define __REGION_DEFS_H__
20 
21 #include "flash_layout.h"
22 
23 #define BL2_HEAP_SIZE           (0x0001000)
24 #define BL2_MSP_STACK_SIZE      (0x0001800)
25 
26 #ifdef ENABLE_HEAP
27     #define S_HEAP_SIZE             (0x0000200)
28 #endif
29 
30 #define S_MSP_STACK_SIZE        (0x0000800)
31 #define S_PSP_STACK_SIZE        (0x0000800)
32 
33 #define NS_HEAP_SIZE            (0x0001000)
34 #define NS_STACK_SIZE           (0x00001E0)
35 
36 /* This size of buffer is big enough to store an attestation
37  * token produced by initial attestation service
38  */
39 #define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE   (0x250)
40 
41 /* eFlash MPC granularity is 4 KB on Musca_B1. Alignment
42  * of partitions is defined in accordance with this constraint.
43  */
44 #ifdef BL2
45 #ifndef LINK_TO_SECONDARY_PARTITION
46 #define S_IMAGE_PRIMARY_PARTITION_OFFSET   (FLASH_AREA_0_OFFSET)
47 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
48 #else
49 #define S_IMAGE_PRIMARY_PARTITION_OFFSET   (FLASH_AREA_2_OFFSET)
50 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
51 #endif /* !LINK_TO_SECONDARY_PARTITION */
52 #else
53 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
54 #endif /* BL2 */
55 
56 #ifndef LINK_TO_SECONDARY_PARTITION
57 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
58                                            + FLASH_S_PARTITION_SIZE)
59 #else
60 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \
61                                            + FLASH_S_PARTITION_SIZE)
62 #endif /* !LINK_TO_SECONDARY_PARTITION */
63 
64 /* Boot partition structure if MCUBoot is used:
65  * 0x0_0000 Bootloader header
66  * 0x0_0400 Image area
67  * 0x1_FC00 Trailer
68  */
69 /* IMAGE_CODE_SIZE is the space available for the software binary image.
70  * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE
71  * because we reserve space for the image header and trailer introduced
72  * by the bootloader.
73  */
74 
75 #if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \
76     (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET)
77 /* If secure image and nonsecure image are concatenated, and nonsecure image
78  * locates at the higher memory range, then the secure image does not need
79  * the trailer area.
80  */
81 #define IMAGE_S_CODE_SIZE \
82             (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE)
83 #else
84 #define IMAGE_S_CODE_SIZE \
85             (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
86 #endif
87 
88 #define IMAGE_NS_CODE_SIZE \
89             (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
90 
91 #define CMSE_VENEER_REGION_SIZE     (0x340)
92 
93 /* Alias definitions for secure and non-secure areas*/
94 #define S_ROM_ALIAS(x)  (S_ROM_ALIAS_BASE + (x))
95 #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
96 
97 #define S_RAM_ALIAS(x)  (S_RAM_ALIAS_BASE + (x))
98 #define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
99 
100 /* Secure regions */
101 #define S_IMAGE_PRIMARY_AREA_OFFSET \
102              (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
103 #define S_CODE_START    (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
104 #define S_CODE_SIZE     (IMAGE_S_CODE_SIZE)
105 #define S_CODE_LIMIT    (S_CODE_START + S_CODE_SIZE - 1)
106 
107 #define S_DATA_START    (S_RAM_ALIAS(0x0))
108 #define S_DATA_SIZE     (TOTAL_RAM_SIZE / 2)
109 #define S_DATA_LIMIT    (S_DATA_START + S_DATA_SIZE - 1)
110 
111 /* Size of vector table: 75 interrupt handlers + 4 bytes MPS initial value */
112 #define S_CODE_VECTOR_TABLE_SIZE    (0x130)
113 
114 /* Non-secure regions */
115 #define NS_IMAGE_PRIMARY_AREA_OFFSET \
116                         (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
117 #define NS_CODE_START   (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
118 #define NS_CODE_SIZE    (IMAGE_NS_CODE_SIZE)
119 #define NS_CODE_LIMIT   (NS_CODE_START + NS_CODE_SIZE - 1)
120 
121 #define NS_DATA_START   (NS_RAM_ALIAS(S_DATA_SIZE))
122 #define NS_DATA_SIZE    (TOTAL_RAM_SIZE - S_DATA_SIZE)
123 #define NS_DATA_LIMIT   (NS_DATA_START + NS_DATA_SIZE - 1)
124 
125 /* Flash is divided into 32 kB sub-regions. Each sub-region can be assigned individual
126 security tier by programing corresponding registers in secure AHB controller.*/
127 #define FLASH_SUBREGION_SIZE    (0x8000)     /* 32 kB */
128 
129 /* RAM is divided into 4 kB sub-regions. Each sub-region can be assigned individual
130 security tier by programing corresponding registers in secure AHB controller. */
131 #define DATA_SUBREGION_SIZE 0x1000      /* 4 KB*/
132 
133 /* NS partition information is used for MPC and SAU configuration */
134 #define NS_PARTITION_START \
135             (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
136 #define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
137 
138 /* Secondary partition for new images in case of firmware upgrade */
139 #define SECONDARY_PARTITION_START \
140             (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
141 #define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
142                                   FLASH_NS_PARTITION_SIZE)
143 
144 /* Code SRAM area */
145 #define TOTAL_CODE_SRAM_SIZE     (0x8000) /* SRAM X region */
146 #define S_CODE_SRAM_ALIAS_BASE   (0x14000000)
147 #define NS_CODE_SRAM_ALIAS_BASE  (0x04000000)
148 
149 #ifdef BL2
150 /* Bootloader regions */
151 #define BL2_CODE_START    (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
152 #define BL2_CODE_SIZE     (FLASH_AREA_BL2_SIZE)
153 #define BL2_CODE_LIMIT    (BL2_CODE_START + BL2_CODE_SIZE - 1)
154 
155 #define BL2_DATA_START    (S_RAM_ALIAS(0x0))
156 #define BL2_DATA_SIZE     (TOTAL_RAM_SIZE)
157 #define BL2_DATA_LIMIT    (BL2_DATA_START + BL2_DATA_SIZE - 1)
158 #endif /* BL2 */
159 
160 /* Shared data area between bootloader and runtime firmware.
161  * Shared data area is allocated at the beginning of the RAM, it is overlapping
162  * with TF-M Secure code's MSP stack
163  */
164 #define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
165 #define BOOT_TFM_SHARED_DATA_SIZE (0x400)
166 #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
167                                     BOOT_TFM_SHARED_DATA_SIZE - 1)
168 
169 #endif /* __REGION_DEFS_H__ */
170