1/*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 *     http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/*********** WARNING: This is an auto-generated file. Do not edit! ***********/
20
21#include "region_defs.h"
22
23LR_CODE S_CODE_START {
24
25    /****  This initial section contains common code for secure binary */
26    ER_TFM_CODE S_CODE_START S_CODE_SIZE {
27        *.o (RESET +First)
28        * (+RO)
29    }
30
31    /**** Unprivileged Secure code start here */
32    TFM_UNPRIV_CODE +0 ALIGN 32 {
33        *(SFN)
34        *armlib*
35        *libtfm_sprt.a (+RO)
36    }
37
38    /**** PSA RoT RO part (CODE + RODATA) start here */
39    /*
40     * This empty, zero long execution region is here to mark the start address
41     * of PSA RoT code.
42     */
43    TFM_PSA_CODE_START +0 ALIGN 32 EMPTY 0x0 {
44    }
45
46#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
47    TFM_SP_ITS_LINKER +0 ALIGN 32 {
48        *tfm_internal_trusted_storage* (+RO)
49        *(TFM_SP_ITS_ATTR_FN)
50    }
51#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
52
53#ifdef TFM_PARTITION_CRYPTO
54    TFM_SP_CRYPTO_LINKER +0 ALIGN 32 {
55        *tfm_crypto* (+RO)
56        *(TFM_SP_CRYPTO_ATTR_FN)
57    }
58#endif /* TFM_PARTITION_CRYPTO */
59
60#ifdef TFM_PARTITION_PLATFORM
61    TFM_SP_PLATFORM_LINKER +0 ALIGN 32 {
62        *tfm_platform* (+RO)
63        *(TFM_SP_PLATFORM_ATTR_FN)
64    }
65#endif /* TFM_PARTITION_PLATFORM */
66
67#ifdef TFM_PARTITION_INITIAL_ATTESTATION
68    TFM_SP_INITIAL_ATTESTATION_LINKER +0 ALIGN 32 {
69        *tfm_attest* (+RO)
70        *(TFM_SP_INITIAL_ATTESTATION_ATTR_FN)
71    }
72#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
73
74#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
75    TFM_SP_SECURE_TEST_PARTITION_LINKER +0 ALIGN 32 {
76        *tfm_secure_client_service.* (+RO)
77        *test_framework* (+RO)
78        *uart_stdout.* (+RO)
79        *Driver_USART.* (+RO)
80        *arm_uart_drv.* (+RO)
81        *uart_pl011_drv.* (+RO)
82        *uart_cmsdk_drv* (+RO)
83        *secure_suites.* (+RO)
84        *attestation_s_interface_testsuite.* (+RO)
85        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
86    }
87#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
88
89#ifdef TFM_PARTITION_TEST_CORE_IPC
90    TFM_SP_IPC_SERVICE_TEST_LINKER +0 ALIGN 32 {
91        *ipc_service_test.* (+RO)
92        *(TFM_SP_IPC_SERVICE_TEST_ATTR_FN)
93    }
94#endif /* TFM_PARTITION_TEST_CORE_IPC */
95
96#ifdef TFM_PARTITION_TEST_PS
97    TFM_SP_PS_TEST_LINKER +0 ALIGN 32 {
98        *tfm_ps_test_service.* (+RO)
99        *(TFM_SP_PS_TEST_ATTR_FN)
100    }
101#endif /* TFM_PARTITION_TEST_PS */
102
103    /*
104     * This empty, zero long execution region is here to mark the end address
105     * of PSA RoT code.
106     */
107    TFM_PSA_CODE_END +0 ALIGN 32 EMPTY 0x0 {
108    }
109
110    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
111    /*
112     * This empty, zero long execution region is here to mark the start address
113     * of APP RoT code.
114     */
115    TFM_APP_CODE_START +0 ALIGN 32 EMPTY 0x0 {
116    }
117
118#ifdef TFM_PARTITION_PROTECTED_STORAGE
119    TFM_SP_PS_LINKER +0 ALIGN 32 {
120        *tfm_storage* (+RO)
121        *test_ps_nv_counters.* (+RO)
122        *(TFM_SP_PS_ATTR_FN)
123    }
124#endif /* TFM_PARTITION_PROTECTED_STORAGE */
125
126#ifdef TFM_PARTITION_TEST_CORE_IPC
127    TFM_SP_IPC_CLIENT_TEST_LINKER +0 ALIGN 32 {
128        *ipc_client_test.* (+RO)
129        *(TFM_SP_IPC_CLIENT_TEST_ATTR_FN)
130    }
131#endif /* TFM_PARTITION_TEST_CORE_IPC */
132
133#ifdef TEST_NS_SLIH_IRQ
134    TFM_SP_SLIH_TEST_LINKER +0 ALIGN 32 {
135        *tfm_slih_test_service.* (+RO)
136        *timer_cmsdk* (+RO)
137        *(TFM_SP_SLIH_TEST_ATTR_FN)
138    }
139#endif /* TEST_NS_SLIH_IRQ */
140
141#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
142    TFM_SP_SECURE_CLIENT_2_LINKER +0 ALIGN 32 {
143        *tfm_secure_client_2.* (+RO)
144        *(TFM_SP_SECURE_CLIENT_2_ATTR_FN)
145    }
146#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
147
148#ifdef TFM_MULTI_CORE_TEST
149    TFM_SP_MULTI_CORE_TEST_LINKER +0 ALIGN 32 {
150        *multi_core_test.* (+RO)
151        *(TFM_SP_MULTI_CORE_TEST_ATTR_FN)
152    }
153#endif /* TFM_MULTI_CORE_TEST */
154
155    /*
156     * This empty, zero long execution region is here to mark the end address
157     * of APP RoT code.
158     */
159    TFM_APP_CODE_END +0 ALIGN 32 EMPTY 0x0 {
160    }
161
162#if defined(S_CODE_SRAM_ALIAS_BASE)
163    /* eFlash driver code that gets copied from Flash to SRAM */
164    ER_CODE_SRAM S_CODE_SRAM_ALIAS_BASE ALIGN 4 {
165        Driver_GFC100_EFlash.o (+RO)
166        gfc100_eflash_drv.o (+RO)
167        musca_b1_eflash_drv.o (+RO)
168    }
169#endif
170
171    /**** Base address of secure data area */
172    TFM_SECURE_DATA_START S_DATA_START {
173    }
174
175    /* Shared area between BL2 and runtime to exchange data */
176    TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
177    }
178
179    /* MSP */
180    ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
181    }
182
183    STACKSEAL +0 EMPTY 0x8 {
184    }
185
186    /**** APP RoT DATA start here */
187    /*
188     * This empty, zero long execution region is here to mark the start address
189     * of APP RoT RW and Stack.
190     */
191    TFM_APP_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
192    }
193
194#ifdef TFM_PARTITION_PROTECTED_STORAGE
195    TFM_SP_PS_LINKER_DATA +0 ALIGN 32 {
196        *tfm_storage* (+RW +ZI)
197        *test_ps_nv_counters.* (+RW +ZI)
198        *(TFM_SP_PS_ATTR_RW)
199        *(TFM_SP_PS_ATTR_ZI)
200    }
201
202    TFM_SP_PS_LINKER_STACK +0 ALIGN 128 EMPTY 0x800 {
203    }
204#endif /* TFM_PARTITION_PROTECTED_STORAGE */
205
206#ifdef TFM_PARTITION_TEST_CORE_IPC
207    TFM_SP_IPC_CLIENT_TEST_LINKER_DATA +0 ALIGN 32 {
208        *ipc_client_test.* (+RW +ZI)
209        *(TFM_SP_IPC_CLIENT_TEST_ATTR_RW)
210        *(TFM_SP_IPC_CLIENT_TEST_ATTR_ZI)
211    }
212
213    TFM_SP_IPC_CLIENT_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0300 {
214    }
215#endif /* TFM_PARTITION_TEST_CORE_IPC */
216
217#ifdef TEST_NS_SLIH_IRQ
218    TFM_SP_SLIH_TEST_LINKER_DATA +0 ALIGN 32 {
219        *tfm_slih_test_service.* (+RW +ZI)
220        *timer_cmsdk* (+RW +ZI)
221        *(TFM_SP_SLIH_TEST_ATTR_RW)
222        *(TFM_SP_SLIH_TEST_ATTR_ZI)
223    }
224
225    TFM_SP_SLIH_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
226    }
227#endif /* TEST_NS_SLIH_IRQ */
228
229#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
230    TFM_SP_SECURE_CLIENT_2_LINKER_DATA +0 ALIGN 32 {
231        *tfm_secure_client_2.* (+RW +ZI)
232        *(TFM_SP_SECURE_CLIENT_2_ATTR_RW)
233        *(TFM_SP_SECURE_CLIENT_2_ATTR_ZI)
234    }
235
236    TFM_SP_SECURE_CLIENT_2_LINKER_STACK +0 ALIGN 128 EMPTY 0x300 {
237    }
238#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
239
240#ifdef TFM_MULTI_CORE_TEST
241    TFM_SP_MULTI_CORE_TEST_LINKER_DATA +0 ALIGN 32 {
242        *multi_core_test.* (+RW +ZI)
243        *(TFM_SP_MULTI_CORE_TEST_ATTR_RW)
244        *(TFM_SP_MULTI_CORE_TEST_ATTR_ZI)
245    }
246
247    TFM_SP_MULTI_CORE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0100 {
248    }
249#endif /* TFM_MULTI_CORE_TEST */
250
251    /*
252     * This empty, zero long execution region is here to mark the end address
253     * of APP RoT RW and Stack.
254     */
255    TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
256    }
257
258    ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
259    }
260
261    ER_TFM_DATA +0 {
262        * (+RW +ZI)
263    }
264
265    /**** PSA RoT DATA start here */
266    /*
267     * This empty, zero long execution region is here to mark the start address
268     * of PSA RoT RW and Stack.
269     */
270    TFM_PSA_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
271    }
272
273#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
274    TFM_SP_ITS_LINKER_DATA +0 ALIGN 32 {
275        *tfm_internal_trusted_storage* (+RW +ZI)
276        *(TFM_SP_ITS_ATTR_RW)
277        *(TFM_SP_ITS_ATTR_ZI)
278    }
279
280    TFM_SP_ITS_LINKER_STACK +0 ALIGN 128 EMPTY 0x680 {
281    }
282#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
283
284#ifdef TFM_PARTITION_CRYPTO
285    TFM_SP_CRYPTO_LINKER_DATA +0 ALIGN 32 {
286        *tfm_crypto* (+RW +ZI)
287        *(TFM_SP_CRYPTO_ATTR_RW)
288        *(TFM_SP_CRYPTO_ATTR_ZI)
289    }
290
291    TFM_SP_CRYPTO_LINKER_STACK +0 ALIGN 128 EMPTY 0x2000 {
292    }
293#endif /* TFM_PARTITION_CRYPTO */
294
295#ifdef TFM_PARTITION_PLATFORM
296    TFM_SP_PLATFORM_LINKER_DATA +0 ALIGN 32 {
297        *tfm_platform* (+RW +ZI)
298        *(TFM_SP_PLATFORM_ATTR_RW)
299        *(TFM_SP_PLATFORM_ATTR_ZI)
300    }
301
302    TFM_SP_PLATFORM_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
303    }
304#endif /* TFM_PARTITION_PLATFORM */
305
306#ifdef TFM_PARTITION_INITIAL_ATTESTATION
307    TFM_SP_INITIAL_ATTESTATION_LINKER_DATA +0 ALIGN 32 {
308        *tfm_attest* (+RW +ZI)
309        *(TFM_SP_INITIAL_ATTESTATION_ATTR_RW)
310        *(TFM_SP_INITIAL_ATTESTATION_ATTR_ZI)
311    }
312
313    TFM_SP_INITIAL_ATTESTATION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0A80 {
314    }
315#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
316
317#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
318    TFM_SP_SECURE_TEST_PARTITION_LINKER_DATA +0 ALIGN 32 {
319        *tfm_secure_client_service.* (+RW +ZI)
320        *test_framework* (+RW +ZI)
321        *uart_stdout.* (+RW +ZI)
322        *Driver_USART.* (+RW +ZI)
323        *arm_uart_drv.* (+RW +ZI)
324        *uart_pl011_drv.* (+RW +ZI)
325        *uart_cmsdk_drv* (+RW +ZI)
326        *secure_suites.* (+RW +ZI)
327        *attestation_s_interface_testsuite.* (+RW +ZI)
328        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_RW)
329        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_ZI)
330    }
331
332    TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0D00 {
333    }
334#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
335
336#ifdef TFM_PARTITION_TEST_CORE_IPC
337    TFM_SP_IPC_SERVICE_TEST_LINKER_DATA +0 ALIGN 32 {
338        *ipc_service_test.* (+RW +ZI)
339        *(TFM_SP_IPC_SERVICE_TEST_ATTR_RW)
340        *(TFM_SP_IPC_SERVICE_TEST_ATTR_ZI)
341    }
342
343    TFM_SP_IPC_SERVICE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0220 {
344    }
345#endif /* TFM_PARTITION_TEST_CORE_IPC */
346
347#ifdef TFM_PARTITION_TEST_PS
348    TFM_SP_PS_TEST_LINKER_DATA +0 ALIGN 32 {
349        *tfm_ps_test_service.* (+RW +ZI)
350        *(TFM_SP_PS_TEST_ATTR_RW)
351        *(TFM_SP_PS_TEST_ATTR_ZI)
352    }
353
354    TFM_SP_PS_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x500 {
355    }
356#endif /* TFM_PARTITION_TEST_PS */
357
358    /*
359     * This empty, zero long execution region is here to mark the end address
360     * of PSA RoT RW and Stack.
361     */
362    TFM_PSA_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
363    }
364
365#if defined (S_RAM_CODE_START)
366    /* Executable code allocated in RAM */
367    TFM_RAM_CODE S_RAM_CODE_START {
368        * (.ramfunc)
369    }
370#endif
371
372    /* This empty, zero long execution region is here to mark the limit address
373     * of the last execution region that is allocated in SRAM.
374     */
375    SRAM_WATERMARK +0 EMPTY 0x0 {
376    }
377
378    /* Make sure that the sections allocated in the SRAM does not exceed the
379     * size of the SRAM available.
380     */
381    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
382}
383
384LR_VENEER CMSE_VENEER_REGION_START {
385    /*
386     * Place the CMSE Veneers (containing the SG instruction) in a separate
387     * 32 bytes aligned region so that the SAU can be programmed to
388     * just set this region as Non-Secure Callable.
389     */
390    CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
391        *(Veneer$$CMSE)
392    }
393}
394
395LR_NS_PARTITION NS_PARTITION_START {
396    /* Reserved place for NS application.
397     * No code will be placed here, just address of this region is used in the
398     * secure code to configure certain HW components. This generates an empty
399     * execution region description warning during linking.
400     */
401    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
402    }
403}
404
405#ifdef BL2
406LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
407    /* Reserved place for new image in case of firmware upgrade.
408     * No code will be placed here, just address of this region is used in the
409     * secure code to configure certain HW components. This generates an empty
410     * execution region description warning during linking.
411     */
412    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
413        UNINIT SECONDARY_PARTITION_SIZE {
414    }
415}
416#endif /* BL2 */
417