1 /**************************************************************************//**
2 * @file eadc.c
3 * @version V2.00
4 * @brief M2354 series EADC driver source file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #include "NuMicro.h"
10
11 /** @addtogroup Standard_Driver Standard Driver
12 @{
13 */
14
15 /** @addtogroup EADC_Driver EADC Driver
16 @{
17 */
18
19 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
20 @{
21 */
22
23 /**
24 * @brief This function make EADC_module be ready to convert.
25 * @param[in] eadc The pointer of the specified EADC module.
26 * @param[in] u32InputMode Decides the input mode.
27 * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.
28 * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.
29 * @return None
30 * @details This function is used to set analog input mode and enable A/D Converter.
31 * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
32 * @note
33 */
EADC_Open(EADC_T * eadc,uint32_t u32InputMode)34 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
35 {
36 eadc->CTL &= (~(EADC_CTL_DIFFEN_Msk));
37
38 eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
39
40 while(!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {}
41 }
42
43 /**
44 * @brief Disable EADC_module.
45 * @param[in] eadc The pointer of the specified EADC module.
46 * @return None
47 * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
48 */
EADC_Close(EADC_T * eadc)49 void EADC_Close(EADC_T *eadc)
50 {
51 eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
52 }
53
54 /**
55 * @brief Configure the sample control logic module.
56 * @param[in] eadc The pointer of the specified EADC module.
57 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
58 * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
59 * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
60 * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
61 * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
62 * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
63 * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger
64 * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger
65 * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
66 * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
67 * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
68 * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
69 * - \ref EADC_PWM0TG0_TRIGGER : EPWM0TG0 trigger
70 * - \ref EADC_PWM0TG1_TRIGGER : EPWM0TG1 trigger
71 * - \ref EADC_PWM0TG2_TRIGGER : EPWM0TG2 trigger
72 * - \ref EADC_PWM0TG3_TRIGGER : EPWM0TG3 trigger
73 * - \ref EADC_PWM0TG4_TRIGGER : EPWM0TG4 trigger
74 * - \ref EADC_PWM0TG5_TRIGGER : EPWM0TG5 trigger
75 * - \ref EADC_PWM1TG0_TRIGGER : EPWM1TG0 trigger
76 * - \ref EADC_PWM1TG1_TRIGGER : EPWM1TG1 trigger
77 * - \ref EADC_PWM1TG2_TRIGGER : EPWM1TG2 trigger
78 * - \ref EADC_PWM1TG3_TRIGGER : EPWM1TG3 trigger
79 * - \ref EADC_PWM1TG4_TRIGGER : EPWM1TG4 trigger
80 * - \ref EADC_PWM1TG5_TRIGGER : EPWM1TG5 trigger
81 * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger
82 * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger
83 * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
84 * @return None
85 * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
86 * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
87 */
EADC_ConfigSampleModule(EADC_T * eadc,uint32_t u32ModuleNum,uint32_t u32TriggerSrc,uint32_t u32Channel)88 void EADC_ConfigSampleModule(EADC_T *eadc, \
89 uint32_t u32ModuleNum, \
90 uint32_t u32TriggerSrc, \
91 uint32_t u32Channel)
92 {
93 eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
94 eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
95 }
96
97
98 /**
99 * @brief Set trigger delay time.
100 * @param[in] eadc The pointer of the specified EADC module.
101 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
102 * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
103 * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
104 * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
105 * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
106 * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
107 * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
108 * @return None
109 * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
110 * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
111 */
EADC_SetTriggerDelayTime(EADC_T * eadc,uint32_t u32ModuleNum,uint32_t u32TriggerDelayTime,uint32_t u32DelayClockDivider)112 void EADC_SetTriggerDelayTime(EADC_T *eadc, \
113 uint32_t u32ModuleNum, \
114 uint32_t u32TriggerDelayTime, \
115 uint32_t u32DelayClockDivider)
116 {
117 eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
118 eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
119 }
120
121 /**
122 * @brief Set ADC extend sample time.
123 * @param[in] eadc The pointer of the specified EADC module.
124 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
125 * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
126 * @return None
127 * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
128 * user can extend A/D sampling time after trigger source is coming to get enough sampling time.
129 */
EADC_SetExtendSampleTime(EADC_T * eadc,uint32_t u32ModuleNum,uint32_t u32ExtendSampleTime)130 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
131 {
132 eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
133
134 eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
135
136 }
137
138 /**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
139
140 /**@}*/ /* end of group EADC_Driver */
141
142 /**@}*/ /* end of group Standard_Driver */
143
