1 /**************************************************************************//** 2 * @file pdma.h 3 * @version V3.00 4 * @brief M2351 series PDMA driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_H__ 10 #define __PDMA_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup PDMA_Driver PDMA Driver 23 @{ 24 */ 25 26 /** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants 27 @{ 28 */ 29 #define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* Operation Mode Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */ 35 #define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */ 36 #define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */ 37 38 /*---------------------------------------------------------------------------------------------------------*/ 39 /* Data Width Constant Definitions */ 40 /*---------------------------------------------------------------------------------------------------------*/ 41 #define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */ 42 #define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */ 43 #define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */ 44 45 /*---------------------------------------------------------------------------------------------------------*/ 46 /* Address Attribute Constant Definitions */ 47 /*---------------------------------------------------------------------------------------------------------*/ 48 #define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */ 49 #define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */ 50 #define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */ 51 #define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */ 52 53 /*---------------------------------------------------------------------------------------------------------*/ 54 /* Burst Mode Constant Definitions */ 55 /*---------------------------------------------------------------------------------------------------------*/ 56 #define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */ 57 #define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */ 58 59 #define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */ 60 #define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */ 61 #define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */ 62 #define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */ 63 #define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */ 64 #define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */ 65 #define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */ 66 #define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */ 67 68 /*---------------------------------------------------------------------------------------------------------*/ 69 /* Table Interrupt Disable Constant Definitions */ 70 /*---------------------------------------------------------------------------------------------------------*/ 71 #define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */ 72 #define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */ 73 74 /*---------------------------------------------------------------------------------------------------------*/ 75 /* Peripheral Transfer Mode Constant Definitions */ 76 /*---------------------------------------------------------------------------------------------------------*/ 77 #define PDMA_MEM 0x00000000UL /*!<DMA Connect to Memory \hideinitializer */ 78 #define PDMA_USB_TX 0x00000002UL /*!<DMA Connect to USB TX \hideinitializer */ 79 #define PDMA_USB_RX 0x00000003UL /*!<DMA Connect to USB RX \hideinitializer */ 80 #define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */ 81 #define PDMA_UART0_RX 0x00000005UL /*!<DMA Connect to UART0 RX \hideinitializer */ 82 #define PDMA_UART1_TX 0x00000006UL /*!<DMA Connect to UART1 TX \hideinitializer */ 83 #define PDMA_UART1_RX 0x00000007UL /*!<DMA Connect to UART1 RX \hideinitializer */ 84 #define PDMA_UART2_TX 0x00000008UL /*!<DMA Connect to UART2 TX \hideinitializer */ 85 #define PDMA_UART2_RX 0x00000009UL /*!<DMA Connect to UART2 RX \hideinitializer */ 86 #define PDMA_UART3_TX 0x0000000AUL /*!<DMA Connect to UART3 TX \hideinitializer */ 87 #define PDMA_UART3_RX 0x0000000BUL /*!<DMA Connect to UART3 RX \hideinitializer */ 88 #define PDMA_UART4_TX 0x0000000CUL /*!<DMA Connect to UART4 TX \hideinitializer */ 89 #define PDMA_UART4_RX 0x0000000DUL /*!<DMA Connect to UART4 RX \hideinitializer */ 90 #define PDMA_UART5_TX 0x0000000EUL /*!<DMA Connect to UART5 TX \hideinitializer */ 91 #define PDMA_UART5_RX 0x0000000FUL /*!<DMA Connect to UART5 RX \hideinitializer */ 92 #define PDMA_USCI0_TX 0x00000010UL /*!<DMA Connect to USCI0 TX \hideinitializer */ 93 #define PDMA_USCI0_RX 0x00000011UL /*!<DMA Connect to USCI0 RX \hideinitializer */ 94 #define PDMA_USCI1_TX 0x00000012UL /*!<DMA Connect to USCI1 TX \hideinitializer */ 95 #define PDMA_USCI1_RX 0x00000013UL /*!<DMA Connect to USCI1 RX \hideinitializer */ 96 #define PDMA_QSPI0_TX 0x00000014UL /*!<DMA Connect to QSPI0 TX \hideinitializer */ 97 #define PDMA_QSPI0_RX 0x00000015UL /*!<DMA Connect to QSPI0 RX \hideinitializer */ 98 #define PDMA_SPI0_TX 0x00000016UL /*!<DMA Connect to SPI0 TX \hideinitializer */ 99 #define PDMA_SPI0_RX 0x00000017UL /*!<DMA Connect to SPI0 RX \hideinitializer */ 100 #define PDMA_SPI1_TX 0x00000018UL /*!<DMA Connect to SPI1 TX \hideinitializer */ 101 #define PDMA_SPI1_RX 0x00000019UL /*!<DMA Connect to SPI1 RX \hideinitializer */ 102 #define PDMA_SPI2_TX 0x0000001AUL /*!<DMA Connect to SPI2 TX \hideinitializer */ 103 #define PDMA_SPI2_RX 0x0000001BUL /*!<DMA Connect to SPI2 RX \hideinitializer */ 104 #define PDMA_SPI3_TX 0x0000001CUL /*!<DMA Connect to SPI3 TX \hideinitializer */ 105 #define PDMA_SPI3_RX 0x0000001DUL /*!<DMA Connect to SPI3 RX \hideinitializer */ 106 #define PDMA_EPWM0_P1_RX 0x00000020UL /*!<DMA Connect to EPWM0 P1 RX \hideinitializer */ 107 #define PDMA_EPWM0_P2_RX 0x00000021UL /*!<DMA Connect to EPWM0 P2 RX \hideinitializer */ 108 #define PDMA_EPWM0_P3_RX 0x00000022UL /*!<DMA Connect to EPWM0 P3 RX \hideinitializer */ 109 #define PDMA_EPWM1_P1_RX 0x00000023UL /*!<DMA Connect to EPWM1 P1 RX \hideinitializer */ 110 #define PDMA_EPWM1_P2_RX 0x00000024UL /*!<DMA Connect to EPWM1 P2 RX \hideinitializer */ 111 #define PDMA_EPWM1_P3_RX 0x00000025UL /*!<DMA Connect to EPWM1 P3 RX \hideinitializer */ 112 #define PDMA_I2C0_TX 0x00000026UL /*!<DMA Connect to I2C0 TX \hideinitializer */ 113 #define PDMA_I2C0_RX 0x00000027UL /*!<DMA Connect to I2C0 RX \hideinitializer */ 114 #define PDMA_I2C1_TX 0x00000028UL /*!<DMA Connect to I2C1 TX \hideinitializer */ 115 #define PDMA_I2C1_RX 0x00000029UL /*!<DMA Connect to I2C1 RX \hideinitializer */ 116 #define PDMA_I2C2_TX 0x0000002AUL /*!<DMA Connect to I2C2 TX \hideinitializer */ 117 #define PDMA_I2C2_RX 0x0000002BUL /*!<DMA Connect to I2C2 RX \hideinitializer */ 118 #define PDMA_I2S0_TX 0x0000002CUL /*!<DMA Connect to I2S0 TX \hideinitializer */ 119 #define PDMA_I2S0_RX 0x0000002DUL /*!<DMA Connect to I2S0 RX \hideinitializer */ 120 #define PDMA_TMR0 0x0000002EUL /*!<DMA Connect to TMR0 \hideinitializer */ 121 #define PDMA_TMR1 0x0000002FUL /*!<DMA Connect to TMR1 \hideinitializer */ 122 #define PDMA_TMR2 0x00000030UL /*!<DMA Connect to TMR2 \hideinitializer */ 123 #define PDMA_TMR3 0x00000031UL /*!<DMA Connect to TMR3 \hideinitializer */ 124 #define PDMA_ADC_RX 0x00000032UL /*!<DMA Connect to ADC RX \hideinitializer */ 125 #define PDMA_DAC0_TX 0x00000033UL /*!<DMA Connect to DAC0 TX \hideinitializer */ 126 #define PDMA_DAC1_TX 0x00000034UL /*!<DMA Connect to DAC1 TX \hideinitializer */ 127 #define PDMA_EPWM0_CH0_TX 0x00000035UL /*!<DMA Connect to EPWM0 CH0 TX \hideinitializer */ 128 #define PDMA_EPWM0_CH1_TX 0x00000036UL /*!<DMA Connect to EPWM0 CH1 TX \hideinitializer */ 129 #define PDMA_EPWM0_CH2_TX 0x00000037UL /*!<DMA Connect to EPWM0 CH2 TX \hideinitializer */ 130 #define PDMA_EPWM0_CH3_TX 0x00000038UL /*!<DMA Connect to EPWM0 CH3 TX \hideinitializer */ 131 #define PDMA_EPWM0_CH4_TX 0x00000039UL /*!<DMA Connect to EPWM0 CH4 TX \hideinitializer */ 132 #define PDMA_EPWM0_CH5_TX 0x0000003AUL /*!<DMA Connect to EPWM0 CH5 TX \hideinitializer */ 133 #define PDMA_EPWM1_CH0_TX 0x0000003BUL /*!<DMA Connect to EPWM1 CH0 TX \hideinitializer */ 134 #define PDMA_EPWM1_CH1_TX 0x0000003CUL /*!<DMA Connect to EPWM1 CH1 TX \hideinitializer */ 135 #define PDMA_EPWM1_CH2_TX 0x0000003DUL /*!<DMA Connect to EPWM1 CH2 TX \hideinitializer */ 136 #define PDMA_EPWM1_CH3_TX 0x0000003EUL /*!<DMA Connect to EPWM1 CH3 TX \hideinitializer */ 137 #define PDMA_EPWM1_CH4_TX 0x0000003FUL /*!<DMA Connect to EPWM1 CH4 TX \hideinitializer */ 138 #define PDMA_EPWM1_CH5_TX 0x00000040UL /*!<DMA Connect to EPWM1 CH5 TX \hideinitializer */ 139 140 /*---------------------------------------------------------------------------------------------------------*/ 141 /* Interrupt Type Constant Definitions */ 142 /*---------------------------------------------------------------------------------------------------------*/ 143 #define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */ 144 #define PDMA_INT_TABLE 0x00000001UL /*!<Table Interrupt \hideinitializer */ 145 #define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */ 146 #define PDMA_INT_ALIGN 0x00000003UL /*!<Transfer Alignment Interrupt \hideinitializer */ 147 148 149 /*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */ 150 151 /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions 152 @{ 153 */ 154 155 /** 156 * @brief Get PDMA Interrupt Status 157 * 158 * @param[in] pdma The pointer of the specified PDMA module 159 * 160 * @return None 161 * 162 * @details This macro gets the interrupt status. 163 */ 164 #define PDMA_GET_INT_STATUS(pdma) ((uint32_t)((pdma)->INTSTS)) 165 166 /** 167 * @brief Get Transfer Done Interrupt Status 168 * 169 * @param[in] pdma The pointer of the specified PDMA module 170 * 171 * @return None 172 * 173 * @details Get the transfer done Interrupt status. 174 */ 175 #define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) 176 177 /** 178 * @brief Clear Transfer Done Interrupt Status 179 * 180 * @param[in] pdma The pointer of the specified PDMA module 181 * @param[in] u32Mask The channel mask 182 * 183 * @return None 184 * 185 * @details Clear the transfer done Interrupt status. 186 */ 187 #define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) 188 189 /** 190 * @brief Get Target Abort Interrupt Status 191 * 192 * @param[in] pdma The pointer of the specified PDMA module 193 * 194 * @return None 195 * 196 * @details Get the target abort Interrupt status. 197 */ 198 #define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) 199 200 /** 201 * @brief Clear Target Abort Interrupt Status 202 * 203 * @param[in] pdma The pointer of the specified PDMA module 204 * @param[in] u32Mask The channel mask 205 * 206 * @return None 207 * 208 * @details Clear the target abort Interrupt status. 209 */ 210 #define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) 211 212 /** 213 * @brief Get PDMA Transfer Alignment Status 214 * 215 * @param[in] pdma The pointer of the specified PDMA module 216 * 217 * @return None 218 * 219 * @details Get the PDMA transfer alignment status. 220 */ 221 #define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) 222 223 /** 224 * @brief Clear PDMA Transfer Alignment Interrupt Status 225 * 226 * @param[in] pdma The pointer of the specified PDMA module 227 * @param[in] u32Mask The channel mask 228 * 229 * @return None 230 * 231 * @details Clear the PDMA transfer alignment Interrupt status. 232 */ 233 #define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) 234 235 /** 236 * @brief Clear Timeout Interrupt Status 237 * 238 * @param[in] pdma The pointer of the specified PDMA module 239 * @param[in] u32Ch The selected channel 240 * 241 * @return None 242 * 243 * @details Clear the selected channel timeout interrupt status. 244 This function is only supported in channel 0 and channel 1. 245 */ 246 #define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) 247 248 /** 249 * @brief Check Channel Status 250 * 251 * @param[in] pdma The pointer of the specified PDMA module 252 * @param[in] u32Ch The selected channel 253 * 254 * @retval 0 Idle state 255 * @retval 1 Busy state 256 * 257 * @details Check the selected channel is busy or not. 258 */ 259 #define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) 260 261 /** 262 * @brief Set Source Address 263 * 264 * @param[in] pdma The pointer of the specified PDMA module 265 * @param[in] u32Ch The selected channel 266 * @param[in] u32Addr The selected address 267 * 268 * @return None 269 * 270 * @details This macro set the selected channel source address. 271 */ 272 #define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) 273 274 /** 275 * @brief Set Destination Address 276 * 277 * @param[in] pdma The pointer of the specified PDMA module 278 * @param[in] u32Ch The selected channel 279 * @param[in] u32Addr The selected address 280 * 281 * @return None 282 * 283 * @details This macro set the selected channel destination address. 284 */ 285 #define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) 286 287 /** 288 * @brief Set Transfer Count 289 * 290 * @param[in] pdma The pointer of the specified PDMA module 291 * @param[in] u32Ch The selected channel 292 * @param[in] u32TransCount Transfer Count 293 * 294 * @return None 295 * 296 * @details This macro set the selected channel transfer count. 297 */ 298 #define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) 299 300 /** 301 * @brief Set Scatter-gather descriptor Address 302 * 303 * @param[in] pdma The pointer of the specified PDMA module 304 * @param[in] u32Ch The selected channel 305 * @param[in] u32Addr The descriptor address 306 * 307 * @return None 308 * 309 * @details This macro set the selected channel scatter-gather descriptor address. 310 */ 311 #define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) 312 313 /** 314 * @brief Stop the channel 315 * 316 * @param[in] pdma The pointer of the specified PDMA module 317 * @param[in] u32Ch The selected channel 318 * 319 * @return None 320 * 321 * @details This macro stop the selected channel. 322 */ 323 #define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) 324 325 /** 326 * @brief Pause the channel 327 * 328 * @param[in] pdma The pointer of the specified PDMA module 329 * @param[in] u32Ch The selected channel 330 * 331 * @return None 332 * 333 * @details This macro pause the selected channel. 334 */ 335 #define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) 336 337 /** 338 * @brief Reset the channel 339 * 340 * @param[in] pdma The pointer of the specified PDMA module 341 * @param[in] u32Ch The selected channel 342 * 343 * @return None 344 * 345 * @details This macro reset the selected channel. 346 */ 347 #define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) 348 349 /*---------------------------------------------------------------------------------------------------------*/ 350 /* Define PWM functions prototype */ 351 /*---------------------------------------------------------------------------------------------------------*/ 352 void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); 353 void PDMA_Close(PDMA_T *pdma); 354 void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); 355 void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); 356 void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); 357 void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); 358 void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); 359 void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); 360 void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); 361 void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); 362 void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); 363 void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); 364 void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); 365 366 367 /*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ 368 369 /*@}*/ /* end of group PDMA_Driver */ 370 371 /*@}*/ /* end of group Standard_Driver */ 372 373 #ifdef __cplusplus 374 } 375 #endif 376 377 #endif /* __PDMA_H__ */ 378 379
