1 /*
2 * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
3 * Copyright (c) 2020 Nordic Semiconductor ASA.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #include "target_cfg.h"
19 #include "region_defs.h"
20 #include "tfm_plat_defs.h"
21 #include "tfm_peripherals_config.h"
22 #include "region.h"
23
24 #include <spu.h>
25 #include <nrfx.h>
26 #include <hal/nrf_nvmc.h>
27
28 #if TFM_PERIPHERAL_REGULATORS_SECURE
29 struct platform_data_t tfm_peripheral_regulators = {
30 NRF_REGULATORS_S_BASE,
31 NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1),
32 };
33 #endif
34
35 #if TFM_PERIPHERAL_CLOCK_SECURE
36 struct platform_data_t tfm_peripheral_clock = {
37 NRF_CLOCK_S_BASE,
38 NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1),
39 };
40 #endif
41
42 #if TFM_PERIPHERAL_POWER_SECURE
43 struct platform_data_t tfm_peripheral_power = {
44 NRF_POWER_S_BASE,
45 NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1),
46 };
47 #endif
48
49 #if TFM_PERIPHERAL_SPIM0_SECURE
50 struct platform_data_t tfm_peripheral_spim0 = {
51 NRF_SPIM0_S_BASE,
52 NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
53 };
54 #endif
55
56 #if TFM_PERIPHERAL_SPIS0_SECURE
57 struct platform_data_t tfm_peripheral_spis0 = {
58 NRF_SPIS0_S_BASE,
59 NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
60 };
61 #endif
62
63 #if TFM_PERIPHERAL_TWIM0_SECURE
64 struct platform_data_t tfm_peripheral_twim0 = {
65 NRF_TWIM0_S_BASE,
66 NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
67 };
68 #endif
69
70 #if TFM_PERIPHERAL_TWIS0_SECURE
71 struct platform_data_t tfm_peripheral_twis0 = {
72 NRF_TWIS0_S_BASE,
73 NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
74 };
75 #endif
76
77 #if TFM_PERIPHERAL_UARTE0_SECURE
78 struct platform_data_t tfm_peripheral_uarte0 = {
79 NRF_UARTE0_S_BASE,
80 NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
81 };
82 #endif
83
84 #if TFM_PERIPHERAL_SPIM1_SECURE
85 struct platform_data_t tfm_peripheral_spim1 = {
86 NRF_SPIM1_S_BASE,
87 NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
88 };
89 #endif
90
91 #if TFM_PERIPHERAL_SPIS1_SECURE
92 struct platform_data_t tfm_peripheral_spis1 = {
93 NRF_SPIS1_S_BASE,
94 NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
95 };
96 #endif
97
98 #if TFM_PERIPHERAL_TWIM1_SECURE
99 struct platform_data_t tfm_peripheral_twim1 = {
100 NRF_TWIM1_S_BASE,
101 NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
102 };
103 #endif
104
105 #if TFM_PERIPHERAL_TWIS1_SECURE
106 struct platform_data_t tfm_peripheral_twis1 = {
107 NRF_TWIS1_S_BASE,
108 NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
109 };
110 #endif
111
112 #if TFM_PERIPHERAL_UARTE1_SECURE
113 struct platform_data_t tfm_peripheral_uarte1 = {
114 NRF_UARTE1_S_BASE,
115 NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
116 };
117 #endif
118
119 #if TFM_PERIPHERAL_SPIM2_SECURE
120 struct platform_data_t tfm_peripheral_spim2 = {
121 NRF_SPIM2_S_BASE,
122 NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
123 };
124 #endif
125
126 #if TFM_PERIPHERAL_SPIS2_SECURE
127 struct platform_data_t tfm_peripheral_spis2 = {
128 NRF_SPIS2_S_BASE,
129 NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
130 };
131 #endif
132
133 #if TFM_PERIPHERAL_TWIM2_SECURE
134 struct platform_data_t tfm_peripheral_twim2 = {
135 NRF_TWIM2_S_BASE,
136 NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
137 };
138 #endif
139
140 #if TFM_PERIPHERAL_TWIS2_SECURE
141 struct platform_data_t tfm_peripheral_twis2 = {
142 NRF_TWIS2_S_BASE,
143 NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
144 };
145 #endif
146
147 #if TFM_PERIPHERAL_UARTE2_SECURE
148 struct platform_data_t tfm_peripheral_uarte2 = {
149 NRF_UARTE2_S_BASE,
150 NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
151 };
152 #endif
153
154 #if TFM_PERIPHERAL_SPIM3_SECURE
155 struct platform_data_t tfm_peripheral_spim3 = {
156 NRF_SPIM3_S_BASE,
157 NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
158 };
159 #endif
160
161 #if TFM_PERIPHERAL_SPIS3_SECURE
162 struct platform_data_t tfm_peripheral_spis3 = {
163 NRF_SPIS3_S_BASE,
164 NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
165 };
166 #endif
167
168 #if TFM_PERIPHERAL_TWIM3_SECURE
169 struct platform_data_t tfm_peripheral_twim3 = {
170 NRF_TWIM3_S_BASE,
171 NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
172 };
173 #endif
174
175 #if TFM_PERIPHERAL_TWIS3_SECURE
176 struct platform_data_t tfm_peripheral_twis3 = {
177 NRF_TWIS3_S_BASE,
178 NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
179 };
180 #endif
181
182 #if TFM_PERIPHERAL_UARTE3_SECURE
183 struct platform_data_t tfm_peripheral_uarte3 = {
184 NRF_UARTE3_S_BASE,
185 NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
186 };
187 #endif
188
189 #if TFM_PERIPHERAL_SAADC_SECURE
190 struct platform_data_t tfm_peripheral_saadc = {
191 NRF_SAADC_S_BASE,
192 NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1),
193 };
194 #endif
195
196 #if TFM_PERIPHERAL_TIMER0_SECURE
197 struct platform_data_t tfm_peripheral_timer0 = {
198 NRF_TIMER0_S_BASE,
199 NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1),
200 };
201 #endif
202
203 #if TFM_PERIPHERAL_TIMER1_SECURE
204 struct platform_data_t tfm_peripheral_timer1 = {
205 NRF_TIMER1_S_BASE,
206 NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1),
207 };
208 #endif
209
210 #if TFM_PERIPHERAL_TIMER2_SECURE
211 struct platform_data_t tfm_peripheral_timer2 = {
212 NRF_TIMER2_S_BASE,
213 NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1),
214 };
215 #endif
216
217 #if TFM_PERIPHERAL_RTC0_SECURE
218 struct platform_data_t tfm_peripheral_rtc0 = {
219 NRF_RTC0_S_BASE,
220 NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1),
221 };
222 #endif
223
224 #if TFM_PERIPHERAL_RTC1_SECURE
225 struct platform_data_t tfm_peripheral_rtc1 = {
226 NRF_RTC1_S_BASE,
227 NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1),
228 };
229 #endif
230
231 #if TFM_PERIPHERAL_DPPI_SECURE
232 struct platform_data_t tfm_peripheral_dppi = {
233 NRF_DPPIC_S_BASE,
234 NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1),
235 };
236 #endif
237
238 #if TFM_PERIPHERAL_WDT_SECURE
239 struct platform_data_t tfm_peripheral_wdt = {
240 NRF_WDT_S_BASE,
241 NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1),
242 };
243 #endif
244
245 #if TFM_PERIPHERAL_EGU0_SECURE
246 struct platform_data_t tfm_peripheral_egu0 = {
247 NRF_EGU0_S_BASE,
248 NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1),
249 };
250 #endif
251
252 #if TFM_PERIPHERAL_EGU1_SECURE
253 struct platform_data_t tfm_peripheral_egu1 = {
254 NRF_EGU1_S_BASE,
255 NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1),
256 };
257 #endif
258
259 #if TFM_PERIPHERAL_EGU2_SECURE
260 struct platform_data_t tfm_peripheral_egu2 = {
261 NRF_EGU2_S_BASE,
262 NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1),
263 };
264 #endif
265
266 #if TFM_PERIPHERAL_EGU3_SECURE
267 struct platform_data_t tfm_peripheral_egu3 = {
268 NRF_EGU3_S_BASE,
269 NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1),
270 };
271 #endif
272
273 #if TFM_PERIPHERAL_EGU4_SECURE
274 struct platform_data_t tfm_peripheral_egu4 = {
275 NRF_EGU4_S_BASE,
276 NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1),
277 };
278 #endif
279
280 #if TFM_PERIPHERAL_EGU5_SECURE
281 struct platform_data_t tfm_peripheral_egu5 = {
282 NRF_EGU5_S_BASE,
283 NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1),
284 };
285 #endif
286
287 #if TFM_PERIPHERAL_PWM0_SECURE
288 struct platform_data_t tfm_peripheral_pwm0 = {
289 NRF_PWM0_S_BASE,
290 NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1),
291 };
292 #endif
293
294 #if TFM_PERIPHERAL_PWM1_SECURE
295 struct platform_data_t tfm_peripheral_pwm1 = {
296 NRF_PWM1_S_BASE,
297 NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1),
298 };
299 #endif
300
301 #if TFM_PERIPHERAL_PWM2_SECURE
302 struct platform_data_t tfm_peripheral_pwm2 = {
303 NRF_PWM2_S_BASE,
304 NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1),
305 };
306 #endif
307
308 #if TFM_PERIPHERAL_PWM3_SECURE
309 struct platform_data_t tfm_peripheral_pwm3 = {
310 NRF_PWM3_S_BASE,
311 NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1),
312 };
313 #endif
314
315 #if TFM_PERIPHERAL_PDM_SECURE
316 struct platform_data_t tfm_peripheral_pdm = {
317 NRF_PDM_S_BASE,
318 NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1),
319 };
320 #endif
321
322 #if TFM_PERIPHERAL_I2S_SECURE
323 struct platform_data_t tfm_peripheral_i2s = {
324 NRF_I2S_S_BASE,
325 NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1),
326 };
327 #endif
328
329 #if TFM_PERIPHERAL_IPC_SECURE
330 struct platform_data_t tfm_peripheral_ipc = {
331 NRF_IPC_S_BASE,
332 NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1),
333 };
334 #endif
335
336 #if TFM_PERIPHERAL_FPU_SECURE
337 struct platform_data_t tfm_peripheral_fpu = {
338 NRF_FPU_S_BASE,
339 NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1),
340 };
341 #endif
342
343 #if TFM_PERIPHERAL_NVMC_SECURE
344 struct platform_data_t tfm_peripheral_nvmc = {
345 NRF_NVMC_S_BASE,
346 NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1),
347 };
348 #endif
349
350 #if TFM_PERIPHERAL_VMC_SECURE
351 struct platform_data_t tfm_peripheral_vmc = {
352 NRF_VMC_S_BASE,
353 NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1),
354 };
355 #endif
356
357 #if TFM_PERIPHERAL_GPIO0_SECURE
358 struct platform_data_t tfm_peripheral_gpio0 = {
359 NRF_P0_S_BASE,
360 NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1),
361 };
362 #endif
363
364 #ifdef PSA_API_TEST_IPC
365 struct platform_data_t
366 tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = {
367 FF_TEST_SERVER_PARTITION_MMIO_START,
368 FF_TEST_SERVER_PARTITION_MMIO_END
369 };
370
371 struct platform_data_t
372 tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO = {
373 FF_TEST_DRIVER_PARTITION_MMIO_START,
374 FF_TEST_DRIVER_PARTITION_MMIO_END
375 };
376
377 /* This platform implementation uses PSA_TEST_SCRATCH_AREA for
378 * storing the state between resets, but the FF_TEST_NVMEM_REGIONS
379 * definitons are still needed for tests to compile.
380 */
381 #define FF_TEST_NVMEM_REGION_START 0xFFFFFFFF
382 #define FF_TEST_NVMEM_REGION_END 0xFFFFFFFF
383 struct platform_data_t
384 tfm_peripheral_FF_TEST_NVMEM_REGION = {
385 FF_TEST_NVMEM_REGION_START,
386 FF_TEST_NVMEM_REGION_END
387 };
388 #endif /* PSA_API_TEST_IPC */
389
390
391 /* The section names come from the scatter file */
392 REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
393 REGION_DECLARE(Image$$, ER_VENEER, $$Base);
394 REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
395
396 const struct memory_region_limits memory_regions = {
397 .non_secure_code_start =
398 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
399 BL2_HEADER_SIZE,
400
401 .non_secure_partition_base =
402 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
403
404 .non_secure_partition_limit =
405 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
406 NS_PARTITION_SIZE - 1,
407
408 .veneer_base =
409 (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
410
411 .veneer_limit =
412 (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
413
414 #ifdef NRF_NS_SECONDARY
415 .secondary_partition_base = SECONDARY_PARTITION_START,
416 .secondary_partition_limit = SECONDARY_PARTITION_START +
417 SECONDARY_PARTITION_SIZE - 1,
418 #endif /* NRF_NS_SECONDARY */
419
420 #ifdef NRF_NS_STORAGE_PARTITION_START
421 .non_secure_storage_partition_base = NRF_NS_STORAGE_PARTITION_START,
422 .non_secure_storage_partition_limit = NRF_NS_STORAGE_PARTITION_START +
423 NRF_NS_STORAGE_PARTITION_SIZE - 1,
424 #endif /* NRF_NS_STORAGE_PARTITION_START */
425 };
426
427 /* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
428 * otherwise the processor ignores the write.
429 */
430 #define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
431
enable_fault_handlers(void)432 enum tfm_plat_err_t enable_fault_handlers(void)
433 {
434 /* Explicitly set secure fault priority to the highest */
435 NVIC_SetPriority(SecureFault_IRQn, 0);
436
437 /* Enables BUS, MEM, USG and Secure faults */
438 SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk |
439 SCB_SHCSR_BUSFAULTENA_Msk |
440 SCB_SHCSR_MEMFAULTENA_Msk |
441 SCB_SHCSR_SECUREFAULTENA_Msk;
442
443 return TFM_PLAT_ERR_SUCCESS;
444 }
445
system_reset_cfg(void)446 enum tfm_plat_err_t system_reset_cfg(void)
447 {
448 uint32_t reg_value = SCB->AIRCR;
449
450 /* Clear SCB_AIRCR_VECTKEY value */
451 reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
452
453 /* Enable system reset request only to the secure world */
454 reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk);
455
456 SCB->AIRCR = reg_value;
457
458 return TFM_PLAT_ERR_SUCCESS;
459 }
460
init_debug(void)461 enum tfm_plat_err_t init_debug(void)
462 {
463 #if !defined(DAUTH_CHIP_DEFAULT)
464 #error "Debug access on this platform can only be configured by programming the corresponding registers in UICR."
465 #endif
466
467 return TFM_PLAT_ERR_SUCCESS;
468 }
469
470 /*----------------- NVIC interrupt target state to NS configuration ----------*/
nvic_interrupt_target_state_cfg(void)471 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
472 {
473 /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */
474 for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) {
475 NVIC->ITNS[i] = 0xFFFFFFFF;
476 }
477
478 /* Make sure that the SPU is targeted to S state */
479 NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_SPU));
480
481 #ifdef SECURE_UART1
482 /* UARTE1 is a secure peripheral, so its IRQ has to target S state */
483 NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_UARTE1));
484 #endif
485
486 return TFM_PLAT_ERR_SUCCESS;
487 }
488
489 /*----------------- NVIC interrupt enabling for S peripherals ----------------*/
nvic_interrupt_enable(void)490 enum tfm_plat_err_t nvic_interrupt_enable(void)
491 {
492 /* SPU interrupt enabling */
493 spu_enable_interrupts();
494
495 NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU));
496 NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU));
497
498 return TFM_PLAT_ERR_SUCCESS;
499 }
500
501 /*------------------- SAU/IDAU configuration functions -----------------------*/
502
sau_and_idau_cfg(void)503 void sau_and_idau_cfg(void)
504 {
505 /* IDAU (SPU) is always enabled. SAU is non-existent.
506 * Allow SPU to have precedence over (non-existing) ARMv8-M SAU.
507 */
508 TZ_SAU_Disable();
509 SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
510 }
511
spu_init_cfg(void)512 enum tfm_plat_err_t spu_init_cfg(void)
513 {
514 /*
515 * Configure SPU Regions for Non-Secure Code and SRAM (Data)
516 * Configure SPU for Peripheral Security
517 * Configure Non-Secure Callable Regions
518 * Configure Secondary Image Partition
519 * Configure Non-Secure Storage Partition
520 */
521
522 /* Reset Flash and SRAM configuration of regions that are not owned by
523 * the bootloader(s) to all-Secure.
524 */
525 spu_regions_reset_unlocked_secure();
526
527 /* Configures SPU Code and Data regions to be non-secure */
528 spu_regions_flash_config_non_secure(
529 memory_regions.non_secure_partition_base,
530 memory_regions.non_secure_partition_limit);
531 spu_regions_sram_config_non_secure(NS_DATA_START, NS_DATA_LIMIT);
532
533 /* Configures veneers region to be non-secure callable */
534 spu_regions_flash_config_non_secure_callable(
535 memory_regions.veneer_base,
536 memory_regions.veneer_limit - 1);
537
538 #ifdef NRF_NS_SECONDARY
539 /* Secondary image partition */
540 spu_regions_flash_config_non_secure(
541 memory_regions.secondary_partition_base,
542 memory_regions.secondary_partition_limit);
543 #endif /* NRF_NS_SECONDARY */
544
545 #ifdef NRF_NS_STORAGE_PARTITION_START
546 /* Configures storage partition to be non-secure */
547 spu_regions_flash_config_non_secure(
548 memory_regions.non_secure_storage_partition_base,
549 memory_regions.non_secure_storage_partition_limit);
550 #endif /* NRF_NS_STORAGE_PARTITION_START */
551
552 return TFM_PLAT_ERR_SUCCESS;
553 }
554
spu_periph_init_cfg(void)555 enum tfm_plat_err_t spu_periph_init_cfg(void)
556 {
557 /* Peripheral configuration */
558
559 /* The following peripherals share ID:
560 * - REGULATORS
561 * - OSCILLATORS
562 */
563 spu_peripheral_config_non_secure((uint32_t)NRF_REGULATORS, false);
564 /* The following peripherals share ID:
565 * - CLOCK
566 * - POWER
567 */
568 spu_peripheral_config_non_secure((uint32_t)NRF_CLOCK, false);
569 /* The following peripherals share ID: (referred to as Serial-Box)
570 * - SPIMx
571 * - SPISx
572 * - TWIMx
573 * - TWISx
574 * - UARTEx
575 */
576 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM0, false);
577 #ifndef SECURE_UART1
578 /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */
579 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM1, false);
580 #endif
581 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM2, false);
582 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM3, false);
583 spu_peripheral_config_non_secure((uint32_t)NRF_SAADC, false);
584 spu_peripheral_config_non_secure((uint32_t)NRF_TIMER0, false);
585 spu_peripheral_config_non_secure((uint32_t)NRF_TIMER1, false);
586 spu_peripheral_config_non_secure((uint32_t)NRF_TIMER2, false);
587 spu_peripheral_config_non_secure((uint32_t)NRF_RTC0, false);
588 spu_peripheral_config_non_secure((uint32_t)NRF_RTC1, false);
589 spu_peripheral_config_non_secure((uint32_t)NRF_DPPIC, false);
590 spu_peripheral_config_non_secure((uint32_t)NRF_WDT, false);
591 spu_peripheral_config_non_secure((uint32_t)NRF_EGU0, false);
592 spu_peripheral_config_non_secure((uint32_t)NRF_EGU1, false);
593 spu_peripheral_config_non_secure((uint32_t)NRF_EGU2, false);
594 spu_peripheral_config_non_secure((uint32_t)NRF_EGU3, false);
595 spu_peripheral_config_non_secure((uint32_t)NRF_EGU4, false);
596 #ifndef PSA_API_TEST_IPC
597 /* EGU5 is used as a secure peripheral in PSA FF tests */
598 spu_peripheral_config_non_secure((uint32_t)NRF_EGU5, false);
599 #endif
600 spu_peripheral_config_non_secure((uint32_t)NRF_PWM0, false);
601 spu_peripheral_config_non_secure((uint32_t)NRF_PWM1, false);
602 spu_peripheral_config_non_secure((uint32_t)NRF_PWM2, false);
603 spu_peripheral_config_non_secure((uint32_t)NRF_PWM2, false);
604 spu_peripheral_config_non_secure((uint32_t)NRF_PDM, false);
605 spu_peripheral_config_non_secure((uint32_t)NRF_I2S, false);
606 spu_peripheral_config_non_secure((uint32_t)NRF_IPC, false);
607 spu_peripheral_config_non_secure((uint32_t)NRF_NVMC, false);
608 spu_peripheral_config_non_secure((uint32_t)NRF_VMC, false);
609 spu_peripheral_config_non_secure((uint32_t)NRF_P0, false);
610
611 /* DPPI channel configuration */
612 spu_dppi_config_non_secure(TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, true);
613
614 /* GPIO pin configuration */
615 spu_gpio_config_non_secure(0, TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, true);
616
617 /* Enable the instruction cache (this can be done only from secure code;
618 * that's why it is placed here).
619 */
620 nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
621
622 return TFM_PLAT_ERR_SUCCESS;
623 }
624
spu_periph_configure_to_secure(uint32_t periph_num)625 void spu_periph_configure_to_secure(uint32_t periph_num)
626 {
627 spu_peripheral_config_secure(periph_num, true);
628 }
629
spu_periph_configure_to_non_secure(uint32_t periph_num)630 void spu_periph_configure_to_non_secure(uint32_t periph_num)
631 {
632 spu_peripheral_config_non_secure(periph_num, true);
633 }
634
