1 /*
2 * Copyright (c) 2021, Arm Limited. All rights reserved.
3 * Copyright (c) 2021-2022 Cypress Semiconductor Corporation (an Infineon
4 * company) or an affiliate of Cypress Semiconductor Corporation. All rights
5 * reserved.
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 *
9 */
10
11 #include <stdint.h>
12
13 #include "cmsis.h"
14 #include "cy_ipc_drv.h"
15 #include "spe_ipc_config.h"
16 #include "spm_ipc.h"
17 #include "tfm_hal_interrupt.h"
18 #include "tfm_peripherals_def.h"
19 #include "ffm/interrupt.h"
20 #include "load/interrupt_defs.h"
21 #include "mailbox/platform_multicore.h"
22
23 static struct irq_t timer0_irq = {0};
24
TFM_TIMER0_IRQ_Handler(void)25 void TFM_TIMER0_IRQ_Handler(void)
26 {
27 spm_handle_interrupt(timer0_irq.p_pt, timer0_irq.p_ildi);
28 }
29
tfm_timer0_irq_init(void * p_pt,const struct irq_load_info_t * p_ildi)30 enum tfm_hal_status_t tfm_timer0_irq_init(void *p_pt,
31 const struct irq_load_info_t *p_ildi)
32 {
33 timer0_irq.p_ildi = p_ildi;
34 timer0_irq.p_pt = p_pt;
35
36 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY);
37 NVIC_DisableIRQ(TFM_TIMER0_IRQ);
38
39 return TFM_HAL_SUCCESS;
40 }
41
42 static struct irq_t mbox_irq_info = {0};
43
mailbox_clear_intr(void)44 static void mailbox_clear_intr(void)
45 {
46 uint32_t status;
47
48 status = Cy_IPC_Drv_GetInterruptStatusMasked(
49 Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
50 status >>= CY_IPC_NOTIFY_SHIFT;
51 if ((status & IPC_RX_INT_MASK) == 0) {
52 return;
53 }
54
55 Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT),
56 0, IPC_RX_INT_MASK);
57 }
58
tfm_mailbox_irq_handler(void)59 void tfm_mailbox_irq_handler(void)
60 {
61 uint32_t magic;
62
63 mailbox_clear_intr();
64
65 /* Read from mailbox */
66 platform_mailbox_fetch_msg_data(&magic);
67 if (magic == PSA_CLIENT_CALL_REQ_MAGIC) {
68 spm_handle_interrupt(mbox_irq_info.p_pt, mbox_irq_info.p_ildi);
69 }
70 }
71
mailbox_irq_init(void * p_pt,const struct irq_load_info_t * p_ildi)72 enum tfm_hal_status_t mailbox_irq_init(void *p_pt,
73 const struct irq_load_info_t *p_ildi)
74 {
75 mbox_irq_info.p_pt = p_pt;
76 mbox_irq_info.p_ildi = p_ildi;
77
78 NVIC_SetPriority(NvicMux7_IRQn, DEFAULT_IRQ_PRIORITY);
79 NVIC_DisableIRQ(NvicMux7_IRQn);
80
81 return TFM_HAL_SUCCESS;
82 }
83 #ifdef PSA_API_TEST_IPC
84
85 static struct irq_t ff_test_uart_irq;
86
FF_TEST_UART_IRQ_Handler(void)87 void FF_TEST_UART_IRQ_Handler(void)
88 {
89 spm_handle_interrupt(ff_test_uart_irq.p_pt, ff_test_uart_irq.p_ildi);
90 }
91
ff_test_uart_irq_init(void * p_pt,const struct irq_load_info_t * p_ildi)92 enum tfm_hal_status_t ff_test_uart_irq_init(void *p_pt,
93 const struct irq_load_info_t *p_ildi)
94 {
95 ff_test_uart_irq.p_ildi = p_ildi;
96 ff_test_uart_irq.p_pt = p_pt;
97
98 NVIC_SetPriority(FF_TEST_UART_IRQ, DEFAULT_IRQ_PRIORITY);
99 NVIC_ClearTargetState(FF_TEST_UART_IRQ);
100 NVIC_DisableIRQ(FF_TEST_UART_IRQ);
101
102 return TFM_HAL_SUCCESS;
103 }
104
105 #endif
106
