1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __TARGET_CFG_H__ 18 #define __TARGET_CFG_H__ 19 20 #include <stdint.h> 21 #include "tfm_peripherals_def.h" 22 #include "tfm_plat_defs.h" 23 24 #define TFM_DRIVER_STDIO Driver_USART0 25 #define NS_DRIVER_STDIO Driver_USART0 26 27 /** 28 * \brief Defines the word offsets of Slave Peripheral Protection Controller 29 * Registers 30 */ 31 enum ppc_bank_e 32 { 33 PPC_SP_DO_NOT_CONFIGURE = -1, 34 PPC_SP_MAIN0 = 0, 35 PPC_SP_MAIN_EXP0 = 1, 36 PPC_SP_MAIN_EXP1 = 2, 37 PPC_SP_MAIN_EXP2 = 3, 38 PPC_SP_MAIN_EXP3 = 4, 39 PPC_SP_PERIPH0 = 5, 40 PPC_SP_PERIPH1 = 6, 41 PPC_SP_PERIPH_EXP0 = 7, 42 PPC_SP_PERIPH_EXP1 = 8, 43 PPC_SP_PERIPH_EXP2 = 9, 44 PPC_SP_PERIPH_EXP3 = 10, 45 }; 46 47 /** 48 * \brief Store the addresses of memory regions 49 */ 50 struct memory_region_limits { 51 uint32_t non_secure_code_start; 52 uint32_t non_secure_partition_base; 53 uint32_t non_secure_partition_limit; 54 uint32_t veneer_base; 55 uint32_t veneer_limit; 56 }; 57 58 /** 59 * \brief Holds the data necessary to do isolation for a specific peripheral. 60 */ 61 struct platform_data_t { 62 uint32_t periph_start; 63 uint32_t periph_limit; 64 enum ppc_bank_e periph_ppc_bank; 65 int16_t periph_ppc_mask; 66 }; 67 68 /** 69 * \brief Enables the fault handlers BusFault, UsageFault, 70 * MemManageFault and SecureFault. 71 */ 72 enum tfm_plat_err_t enable_fault_handlers(void); 73 74 /** 75 * \brief Configures the system reset request properties 76 * 77 * \return Returns values as specified by the \ref tfm_plat_err_t 78 */ 79 enum tfm_plat_err_t system_reset_cfg(void); 80 81 /** 82 * \brief Configures all external interrupts to target the 83 * NS state, apart for the ones associated to secure 84 * peripherals (plus MPC and PPC) 85 * 86 * \return Returns values as specified by the \ref tfm_plat_err_t 87 */ 88 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 89 90 /** 91 * \brief This function enable the interrupts associated 92 * to the secure peripherals (plus MPC and PPC) 93 * 94 * \return Returns values as specified by the \ref tfm_plat_err_t 95 */ 96 enum tfm_plat_err_t nvic_interrupt_enable(void); 97 98 /** 99 * \brief Configures the system debug properties. 100 * 101 * \return Returns values as specified by the \ref tfm_plat_err_t 102 */ 103 enum tfm_plat_err_t init_debug(void); 104 105 /** 106 * \brief Configures the Memory Protection Controller. 107 * 108 * \return Returns error code. 109 */ 110 enum tfm_plat_err_t mpc_init_cfg(void); 111 112 /** 113 * \brief Clear MPC interrupt. 114 */ 115 void mpc_clear_irq(void); 116 117 /** 118 * \brief Configures the Peripheral Protection Controller. 119 */ 120 enum tfm_plat_err_t ppc_init_cfg(void); 121 122 /** 123 * \brief Restrict peripheral access to secure access only 124 * 125 * \note The function does not configure privilege 126 */ 127 void ppc_configure_to_secure(enum ppc_bank_e bank, uint32_t pos); 128 129 /** 130 * \brief Allow non-secure access to peripheral 131 * 132 * \note The function does not configure privilege 133 */ 134 void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint32_t pos); 135 136 /** 137 * \brief Enable secure unprivileged access to peripheral 138 */ 139 void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint32_t pos); 140 141 /** 142 * \brief Clear secure unprivileged access to peripheral 143 */ 144 void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint32_t pos); 145 146 /** 147 * \brief Clears PPC interrupt. 148 */ 149 void ppc_clear_irq(void); 150 151 /** 152 * \brief Configures SAU and IDAU. 153 */ 154 void sau_and_idau_cfg(void); 155 156 /** 157 * \brief Initialize the DMA devices and channels. 158 * 159 * \return Returns values as specified by the \ref tfm_plat_err_t 160 */ 161 enum tfm_plat_err_t dma_init_cfg(void); 162 163 #endif /* __TARGET_CFG_H__ */ 164
