1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __REGION_DEFS_H__ 18 #define __REGION_DEFS_H__ 19 20 #include "flash_layout.h" 21 #include "platform_base_address.h" 22 23 #define BL1_1_HEAP_SIZE (0x0001000) 24 #define BL1_1_MSP_STACK_SIZE (0x0001800) 25 26 #define BL1_2_HEAP_SIZE (0x0001000) 27 #define BL1_2_MSP_STACK_SIZE (0x0001800) 28 29 #define BL2_HEAP_SIZE (0x0001000) 30 #define BL2_MSP_STACK_SIZE (0x0001800) 31 32 #define S_HEAP_SIZE (0x0001000) 33 #define S_MSP_STACK_SIZE (0x0000800) 34 35 #define NS_HEAP_SIZE (0x0001000) 36 #define NS_STACK_SIZE (0x0001000) 37 38 /* This size of buffer is big enough to store an attestation 39 * token produced by initial attestation service 40 */ 41 #define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x800) 42 /* This size of buffer is big enough to store an array of all the 43 * boot records/measurements which is encoded in CBOR format. 44 */ 45 #define TFM_ATTEST_BOOT_RECORDS_MAX_SIZE (0x400) 46 47 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_4_OFFSET) 48 49 /* Boot partition structure if MCUBoot is used: 50 * 0x0_0000 Bootloader header 51 * 0x0_0400 Image area 52 * 0x5_0000 Trailer 53 */ 54 /* IMAGE_CODE_SIZE is the space available for the software binary image. 55 * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE 56 * because we reserve space for the image header and trailer introduced 57 * by the bootloader. 58 */ 59 #define IMAGE_BL2_CODE_SIZE \ 60 (FLASH_BL2_PARTITION_SIZE - BL1_HEADER_SIZE - BL1_TRAILER_SIZE) 61 62 #define IMAGE_S_CODE_SIZE \ 63 (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) 64 65 #define IMAGE_NS_CODE_SIZE \ 66 (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) 67 68 /* Secure regions */ 69 /* Secure Code executes from VM1 */ 70 #define S_CODE_START (S_IMAGE_LOAD_ADDRESS + BL2_HEADER_SIZE) 71 #define S_CODE_SIZE (IMAGE_S_CODE_SIZE) 72 #define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) 73 74 /* Secure Data stored in VM0 */ 75 #define S_DATA_START (VM0_BASE_S + 0x500000) 76 #define S_DATA_SIZE (0x100000) 77 #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) 78 79 /* Size of vector table: 111 interrupt handlers + 4 bytes MSP initial value */ 80 #define S_CODE_VECTOR_TABLE_SIZE (0x1C0) 81 82 /* Non-secure regions */ 83 /* Non-Secure Code executes from VM1 */ 84 #define NS_CODE_START (VM1_BASE_NS + SECURE_IMAGE_MAX_SIZE + BL2_HEADER_SIZE) 85 #define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) 86 #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) 87 88 /* Non-Secure Data stored in VM0 */ 89 #define NS_DATA_START (VM0_BASE_NS + 0x600000) 90 #define NS_DATA_SIZE (0x100000) 91 #define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) 92 93 /* NS partition information is used for MPC and SAU configuration */ 94 #define NS_PARTITION_START \ 95 (VM1_BASE_NS + SECURE_IMAGE_MAX_SIZE) 96 #define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) 97 98 /* Secondary partition for new images in case of firmware upgrade */ 99 #define SECONDARY_PARTITION_START \ 100 (VM0_BASE_NS + S_IMAGE_SECONDARY_PARTITION_OFFSET) 101 #define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ 102 FLASH_NS_PARTITION_SIZE) 103 104 /* Bootloader regions */ 105 /* BL1_1 is XIP from ROM */ 106 #define BL1_1_CODE_START (ROM_BASE_S) 107 #define BL1_1_CODE_SIZE (0xE000) /* 56 KB */ 108 #define BL1_1_CODE_LIMIT (BL1_1_CODE_START + BL1_1_CODE_SIZE - 1) 109 110 #define PROVISIONING_DATA_START (BL1_1_CODE_START + BL1_1_CODE_SIZE) 111 #define PROVISIONING_DATA_SIZE (0x2400) /* 9 KB */ 112 #define PROVISIONING_DATA_LIMIT (PROVISIONING_DATA_START + PROVISIONING_DATA_SIZE - 1) 113 114 /* BL1_2 executes from VM1 */ 115 #define BL1_2_CODE_START (NS_IMAGE_LOAD_ADDRESS + NON_SECURE_IMAGE_MAX_SIZE) 116 #define BL1_2_CODE_SIZE (0x2000) /* 8 KB */ 117 #define BL1_2_CODE_LIMIT (BL1_2_CODE_START + BL1_2_CODE_SIZE - 1) 118 119 /* BL2 executes from VM1, and is positioned directly after BL1_2 */ 120 #define BL2_IMAGE_START (BL1_2_CODE_START + BL1_2_CODE_SIZE) 121 #define BL2_CODE_START (BL2_IMAGE_START + BL1_HEADER_SIZE) 122 #define BL2_CODE_SIZE (IMAGE_BL2_CODE_SIZE) 123 #define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) 124 125 /* Bootloader uses same memory as for secure image */ 126 #define BL1_1_DATA_START (S_DATA_START) 127 #define BL1_1_DATA_SIZE (0x4000) /* 16 KB */ 128 #define BL1_1_DATA_LIMIT (BL1_1_DATA_START + BL1_1_DATA_SIZE - 1) 129 130 #define BL1_2_DATA_START (BL1_1_DATA_START + BL1_1_DATA_SIZE) 131 #define BL1_2_DATA_SIZE (0x4000) /* 16 KB */ 132 #define BL1_2_DATA_LIMIT (BL1_2_DATA_START + BL1_2_DATA_SIZE - 1) 133 134 #define BL2_DATA_START (S_DATA_START) 135 #define BL2_DATA_SIZE (0x8000) /* 32 KB */ 136 #define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) 137 138 /* Shared data area between bootloader and runtime firmware. 139 * Shared data area is allocated at the beginning of the RAM, it is overlapping 140 * with TF-M Secure code's MSP stack 141 */ 142 #define BOOT_TFM_SHARED_DATA_BASE S_DATA_START 143 #define BOOT_TFM_SHARED_DATA_SIZE (0x400) 144 #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ 145 BOOT_TFM_SHARED_DATA_SIZE - 1) 146 147 /* AP to RSS MHU receiver interrupt */ 148 #define MAILBOX_IRQ CMU_MHU0_Receiver_IRQn 149 150 #endif /* __REGION_DEFS_H__ */ 151
