1 /*
2 * Copyright (c) 2022 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c
21 * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
22 */
23
24 #include "cmsis.h"
25
26 /*----------------------------------------------------------------------------
27 External References
28 *----------------------------------------------------------------------------*/
29 extern uint32_t __INITIAL_SP;
30 extern uint32_t __STACK_LIMIT;
31 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
32 extern uint64_t __STACK_SEAL;
33 #endif
34
35 extern void __PROGRAM_START(void) __NO_RETURN;
36
37 /*----------------------------------------------------------------------------
38 Internal References
39 *----------------------------------------------------------------------------*/
40 void Reset_Handler (void) __NO_RETURN;
41
42 /*----------------------------------------------------------------------------
43 Exception / Interrupt Handler
44 *----------------------------------------------------------------------------*/
45 #define DEFAULT_IRQ_HANDLER(handler_name) \
46 void __WEAK handler_name(void) __NO_RETURN; \
47 void handler_name(void) { \
48 while(1); \
49 }
50
51 /* Exceptions */
52 DEFAULT_IRQ_HANDLER(NMI_Handler)
53 DEFAULT_IRQ_HANDLER(HardFault_Handler)
54 DEFAULT_IRQ_HANDLER(MemManage_Handler)
55 DEFAULT_IRQ_HANDLER(BusFault_Handler)
56 DEFAULT_IRQ_HANDLER(UsageFault_Handler)
57 DEFAULT_IRQ_HANDLER(SecureFault_Handler)
58 DEFAULT_IRQ_HANDLER(SVC_Handler)
59 DEFAULT_IRQ_HANDLER(DebugMon_Handler)
60 DEFAULT_IRQ_HANDLER(PendSV_Handler)
61 DEFAULT_IRQ_HANDLER(SysTick_Handler)
62
63 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler)
64 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
65 DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
66 DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
67 DEFAULT_IRQ_HANDLER(TIMER1_Handler)
68 DEFAULT_IRQ_HANDLER(TIMER2_Handler)
69 DEFAULT_IRQ_HANDLER(MPC_Handler)
70 DEFAULT_IRQ_HANDLER(PPC_Handler)
71 DEFAULT_IRQ_HANDLER(MSC_Handler)
72 DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
73 DEFAULT_IRQ_HANDLER(PPU_Combined_Handler)
74 DEFAULT_IRQ_HANDLER(NPU0_Handler)
75 DEFAULT_IRQ_HANDLER(NPU1_Handler)
76 DEFAULT_IRQ_HANDLER(NPU2_Handler)
77 DEFAULT_IRQ_HANDLER(NPU3_Handler)
78 DEFAULT_IRQ_HANDLER(KMU_Handler)
79 DEFAULT_IRQ_HANDLER(DMA_Combined_S_Handler)
80 DEFAULT_IRQ_HANDLER(DMA_Combined_NS_Handler)
81 DEFAULT_IRQ_HANDLER(DMA_Security_Violation_Handler)
82 DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler)
83 DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler)
84 DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler)
85
86 DEFAULT_IRQ_HANDLER(SAM_Critical_Sec_Fault_S_Handler)
87 DEFAULT_IRQ_HANDLER(SAM_Sec_Fault_S_Handler)
88 DEFAULT_IRQ_HANDLER(GPIO_Combined_S_Handler)
89 DEFAULT_IRQ_HANDLER(SDC_Handler)
90 DEFAULT_IRQ_HANDLER(FPU_Handler)
91 DEFAULT_IRQ_HANDLER(SRAM_TRAM_ECC_Err_Combined_S_Handler)
92 DEFAULT_IRQ_HANDLER(SIC_S_Handler)
93 DEFAULT_IRQ_HANDLER(ATU_S_Handler)
94 DEFAULT_IRQ_HANDLER(CMU_MHU0_Sender_Handler)
95 DEFAULT_IRQ_HANDLER(CMU_MHU0_Receiver_Handler)
96 DEFAULT_IRQ_HANDLER(CMU_MHU1_Sender_Handler)
97 DEFAULT_IRQ_HANDLER(CMU_MHU1_Receiver_Handler)
98 DEFAULT_IRQ_HANDLER(CMU_MHU2_Sender_Handler)
99 DEFAULT_IRQ_HANDLER(CMU_MHU2_Receiver_Handler)
100 DEFAULT_IRQ_HANDLER(CMU_MHU3_Sender_Handler)
101 DEFAULT_IRQ_HANDLER(CMU_MHU3_Receiver_Handler)
102 DEFAULT_IRQ_HANDLER(CMU_MHU4_Sender_Handler)
103 DEFAULT_IRQ_HANDLER(CMU_MHU4_Receiver_Handler)
104 DEFAULT_IRQ_HANDLER(CMU_MHU5_Sender_Handler)
105 DEFAULT_IRQ_HANDLER(CMU_MHU5_Receiver_Handler)
106 DEFAULT_IRQ_HANDLER(CMU_MHU6_Sender_Handler)
107 DEFAULT_IRQ_HANDLER(CMU_MHU6_Receiver_Handler)
108 DEFAULT_IRQ_HANDLER(CMU_MHU7_Sender_Handler)
109 DEFAULT_IRQ_HANDLER(CMU_MHU7_Receiver_Handler)
110 DEFAULT_IRQ_HANDLER(CMU_MHU8_Sender_Handler)
111 DEFAULT_IRQ_HANDLER(CMU_MHU8_Receiver_Handler)
112 DEFAULT_IRQ_HANDLER(Crypto_Engine_S_Handler)
113 DEFAULT_IRQ_HANDLER(SoC_System_Timer0_AON_Handler)
114 DEFAULT_IRQ_HANDLER(SoC_System_Timer1_AON_Handler)
115
116 /*----------------------------------------------------------------------------
117 Exception / Interrupt Vector table
118 *----------------------------------------------------------------------------*/
119
120 #if defined ( __GNUC__ )
121 #pragma GCC diagnostic push
122 #pragma GCC diagnostic ignored "-Wpedantic"
123 #endif
124
125 extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
126 const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
127 (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
128 Reset_Handler, /* Reset Handler */
129 NMI_Handler, /* -14: NMI Handler */
130 HardFault_Handler, /* -13: Hard Fault Handler */
131 MemManage_Handler, /* -12: MPU Fault Handler */
132 BusFault_Handler, /* -11: Bus Fault Handler */
133 UsageFault_Handler, /* -10: Usage Fault Handler */
134 SecureFault_Handler, /* -9: Secure Fault Handler */
135 0, /* Reserved */
136 0, /* Reserved */
137 0, /* Reserved */
138 SVC_Handler, /* -5: SVCall Handler */
139 DebugMon_Handler, /* -4: Debug Monitor Handler */
140 0, /* Reserved */
141 PendSV_Handler, /* -2: PendSV Handler */
142 SysTick_Handler, /* -1: SysTick Handler */
143
144 NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
145 NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
146 SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
147 TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
148 TIMER1_Handler, /* 4: TIMER 1 Handler */
149 TIMER2_Handler, /* 5: TIMER 2 Handler */
150 0, /* 6: Reserved */
151 0, /* 7: Reserved */
152 0, /* 8: Reserved */
153 MPC_Handler, /* 9: MPC Combined (Secure) Handler */
154 PPC_Handler, /* 10: PPC Combined (Secure) Handler */
155 MSC_Handler, /* 11: MSC Combined (Secure) Handler */
156 BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
157 0, /* 13: Reserved */
158 PPU_Combined_Handler, /* 14: PPU Combined (Secure) Handler */
159 0, /* 15: Reserved */
160 NPU0_Handler, /* 16: NPU0 Handler */
161 NPU1_Handler, /* 17: NPU1 Handler */
162 NPU2_Handler, /* 18: NPU2 Handler */
163 NPU3_Handler, /* 19: NPU3 Handler */
164 KMU_Handler, /* 20: KMU (Secure) Handler */
165 0, /* 21: Reserved */
166 0, /* 22: Reserved */
167 0, /* 23: Reserved */
168 DMA_Combined_S_Handler, /* 24: DMA350 Combined (Secure) Handler */
169 DMA_Combined_NS_Handler, /* 25: DMA350 Combined (Non-Secure) Handler */
170 DMA_Security_Violation_Handler, /* 26: DMA350 Security Violation Handler */
171 TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */
172 CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */
173 CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */
174 0, /* 30: Reserved */
175 0, /* 31: Reserved */
176
177 /* External interrupts */
178 SAM_Critical_Sec_Fault_S_Handler, /* 32: SAM Critical Security Fault (Secure) Handler */
179 SAM_Sec_Fault_S_Handler, /* 33: SAM Security Fault (Secure) Handler */
180 GPIO_Combined_S_Handler, /* 34: GPIO Combined (Secure) Handler */
181 SDC_Handler, /* 35: Secure Debug Channel Handler */
182 FPU_Handler, /* 36: FPU Exception Handler */
183 SRAM_TRAM_ECC_Err_Combined_S_Handler,
184 /* 37: SRAM and TRAM Corrected ECC Error
185 * Combined (Secure) Handler */
186 SIC_S_Handler, /* 38: SICache (Secure) Handler */
187 ATU_S_Handler, /* 39: ATU (Secure) Handler */
188 CMU_MHU0_Sender_Handler, /* 40: CMU MHU 0 Sender Handler */
189 CMU_MHU0_Receiver_Handler, /* 41: CMU MHU 0 Receiver Handler */
190 CMU_MHU1_Sender_Handler, /* 42: CMU MHU 1 Sender Handler */
191 CMU_MHU1_Receiver_Handler, /* 43: CMU MHU 1 Receiver Handler */
192 CMU_MHU2_Sender_Handler, /* 44: CMU MHU 2 Sender Handler */
193 CMU_MHU2_Receiver_Handler, /* 45: CMU MHU 2 Receiver Handler */
194 CMU_MHU3_Sender_Handler, /* 46: CMU MHU 3 Sender Handler */
195 CMU_MHU3_Receiver_Handler, /* 47: CMU MHU 3 Receiver Handler */
196 CMU_MHU4_Sender_Handler, /* 48: CMU MHU 4 Sender Handler */
197 CMU_MHU4_Receiver_Handler, /* 49: CMU MHU 4 Receiver Handler */
198 CMU_MHU5_Sender_Handler, /* 50: CMU MHU 5 Sender Handler */
199 CMU_MHU5_Receiver_Handler, /* 51: CMU MHU 5 Receiver Handler */
200 CMU_MHU6_Sender_Handler, /* 52: CMU MHU 6 Sender Handler */
201 CMU_MHU6_Receiver_Handler, /* 53: CMU MHU 6 Receiver Handler */
202 CMU_MHU7_Sender_Handler, /* 54: CMU MHU 7 Sender Handler */
203 CMU_MHU7_Receiver_Handler, /* 55: CMU MHU 7 Receiver Handler */
204 CMU_MHU8_Sender_Handler, /* 56: CMU MHU 8 Sender Handler */
205 CMU_MHU8_Receiver_Handler, /* 57: CMU MHU 8 Receiver Handler */
206 Crypto_Engine_S_Handler, /* 58: Crypto Engine (Secure) Handler */
207 SoC_System_Timer0_AON_Handler, /* 59: SoC System Timer 0 AON Handler */
208 SoC_System_Timer1_AON_Handler, /* 60: SoC System Timer 1 AON Handler */
209 };
210
211 #if defined ( __GNUC__ )
212 #pragma GCC diagnostic pop
213 #endif
214
215 /*----------------------------------------------------------------------------
216 Reset Handler called on controller reset
217 *----------------------------------------------------------------------------*/
Reset_Handler(void)218 void Reset_Handler(void)
219 {
220 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
221 __disable_irq();
222 #endif
223 __set_PSP((uint32_t)(&__INITIAL_SP));
224
225 __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
226 __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
227
228 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
229 __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
230 #endif
231
232 SystemInit(); /* CMSIS System Initialization */
233 __PROGRAM_START(); /* Enter PreMain (C library entry point) */
234 }
235
