1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file device_definition.c 19 * \brief This file defines exports the structures based on the peripheral 20 * definitions from device_cfg.h. 21 * This file is meant to be used as a helper for baremetal 22 * applications and/or as an example of how to configure the generic 23 * driver structures. 24 */ 25 26 #include "device_definition.h" 27 #include "platform_base_address.h" 28 29 /* Arm ATU driver structures */ 30 #ifdef ATU_S 31 static const struct atu_dev_cfg_t ATU_DEV_CFG_S = { 32 .base = ATU_BASE_S}; 33 struct atu_dev_t ATU_DEV_S = {&ATU_DEV_CFG_S}; 34 #endif 35 36 /* Arm UART PL011 driver structures */ 37 #ifdef UART0_PL011_S 38 static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_S = { 39 .base = UART0_BASE_S, 40 .def_baudrate = DEFAULT_UART_BAUDRATE, 41 .def_wlen = UART_PL011_WLEN_8, 42 .def_parity = UART_PL011_PARITY_DISABLED, 43 .def_stopbit = UART_PL011_STOPBIT_1}; 44 static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_S = { 45 .state = 0, 46 .uart_clk = 0, 47 .baudrate = 0}; 48 struct uart_pl011_dev_t UART0_PL011_DEV_S = {&(UART0_PL011_DEV_CFG_S), 49 &(UART0_PL011_DEV_DATA_S)}; 50 #endif 51 #ifdef UART0_PL011_NS 52 static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_NS = { 53 .base = UART0_BASE_NS, 54 .def_baudrate = DEFAULT_UART_BAUDRATE, 55 .def_wlen = UART_PL011_WLEN_8, 56 .def_parity = UART_PL011_PARITY_DISABLED, 57 .def_stopbit = UART_PL011_STOPBIT_1}; 58 static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_NS = { 59 .state = 0, 60 .uart_clk = 0, 61 .baudrate = 0}; 62 struct uart_pl011_dev_t UART0_PL011_DEV_NS = {&(UART0_PL011_DEV_CFG_NS), 63 &(UART0_PL011_DEV_DATA_NS)}; 64 #endif 65 66 /* RSS PPC driver structures */ 67 #ifdef PPC_RSS_MAIN0_S 68 static struct ppc_rss_dev_cfg_t PPC_RSS_MAIN0_CFG_S = { 69 .sacfg_base = RSS_SACFG_BASE_S, 70 .nsacfg_base = RSS_NSACFG_BASE_NS, 71 .ppc_name = PPC_RSS_MAIN0}; 72 static struct ppc_rss_dev_data_t PPC_RSS_MAIN0_DATA_S = { 73 .sacfg_ns_ppc = 0, 74 .sacfg_sp_ppc = 0, 75 .nsacfg_nsp_ppc = 0, 76 .int_bit_mask = 0, 77 .is_initialized = false }; 78 struct ppc_rss_dev_t PPC_RSS_MAIN0_DEV_S = { 79 &PPC_RSS_MAIN0_CFG_S, 80 &PPC_RSS_MAIN0_DATA_S }; 81 #endif 82 83 #ifdef PPC_RSS_MAIN_EXP0_S 84 static struct ppc_rss_dev_cfg_t PPC_RSS_MAIN_EXP0_CFG_S = { 85 .sacfg_base = RSS_SACFG_BASE_S, 86 .nsacfg_base = RSS_NSACFG_BASE_NS, 87 .ppc_name = PPC_RSS_MAIN_EXP0}; 88 static struct ppc_rss_dev_data_t PPC_RSS_MAIN_EXP0_DATA_S = { 89 .sacfg_ns_ppc = 0, 90 .sacfg_sp_ppc = 0, 91 .nsacfg_nsp_ppc = 0, 92 .int_bit_mask = 0, 93 .is_initialized = false }; 94 struct ppc_rss_dev_t PPC_RSS_MAIN_EXP0_DEV_S = { 95 &PPC_RSS_MAIN_EXP0_CFG_S, 96 &PPC_RSS_MAIN_EXP0_DATA_S }; 97 #endif 98 99 #ifdef PPC_RSS_MAIN_EXP1_S 100 static struct ppc_rss_dev_cfg_t PPC_RSS_MAIN_EXP1_CFG_S = { 101 .sacfg_base = RSS_SACFG_BASE_S, 102 .nsacfg_base = RSS_NSACFG_BASE_NS, 103 .ppc_name = PPC_RSS_MAIN_EXP1}; 104 static struct ppc_rss_dev_data_t PPC_RSS_MAIN_EXP1_DATA_S = { 105 .sacfg_ns_ppc = 0, 106 .sacfg_sp_ppc = 0, 107 .nsacfg_nsp_ppc = 0, 108 .int_bit_mask = 0, 109 .is_initialized = false }; 110 struct ppc_rss_dev_t PPC_RSS_MAIN_EXP1_DEV_S = { 111 &PPC_RSS_MAIN_EXP1_CFG_S, 112 &PPC_RSS_MAIN_EXP1_DATA_S }; 113 #endif 114 115 #ifdef PPC_RSS_MAIN_EXP2_S 116 static struct ppc_rss_dev_cfg_t PPC_RSS_MAIN_EXP2_CFG_S = { 117 .sacfg_base = RSS_SACFG_BASE_S, 118 .nsacfg_base = RSS_NSACFG_BASE_NS, 119 .ppc_name = PPC_RSS_MAIN_EXP2}; 120 static struct ppc_rss_dev_data_t PPC_RSS_MAIN_EXP2_DATA_S = { 121 .sacfg_ns_ppc = 0, 122 .sacfg_sp_ppc = 0, 123 .nsacfg_nsp_ppc = 0, 124 .int_bit_mask = 0, 125 .is_initialized = false }; 126 struct ppc_rss_dev_t PPC_RSS_MAIN_EXP2_DEV_S = { 127 &PPC_RSS_MAIN_EXP2_CFG_S, 128 &PPC_RSS_MAIN_EXP2_DATA_S }; 129 #endif 130 131 #ifdef PPC_RSS_MAIN_EXP3_S 132 static struct ppc_rss_dev_cfg_t PPC_RSS_MAIN_EXP3_CFG_S = { 133 .sacfg_base = RSS_SACFG_BASE_S, 134 .nsacfg_base = RSS_NSACFG_BASE_NS, 135 .ppc_name = PPC_RSS_MAIN_EXP3}; 136 static struct ppc_rss_dev_data_t PPC_RSS_MAIN_EXP3_DATA_S = { 137 .sacfg_ns_ppc = 0, 138 .sacfg_sp_ppc = 0, 139 .nsacfg_nsp_ppc = 0, 140 .int_bit_mask = 0, 141 .is_initialized = false }; 142 struct ppc_rss_dev_t PPC_RSS_MAIN_EXP3_DEV_S = { 143 &PPC_RSS_MAIN_EXP3_CFG_S, 144 &PPC_RSS_MAIN_EXP3_DATA_S }; 145 #endif 146 147 #ifdef PPC_RSS_PERIPH0_S 148 static struct ppc_rss_dev_cfg_t PPC_RSS_PERIPH0_CFG_S = { 149 .sacfg_base = RSS_SACFG_BASE_S, 150 .nsacfg_base = RSS_NSACFG_BASE_NS, 151 .ppc_name = PPC_RSS_PERIPH0}; 152 static struct ppc_rss_dev_data_t PPC_RSS_PERIPH0_DATA_S = { 153 .sacfg_ns_ppc = 0, 154 .sacfg_sp_ppc = 0, 155 .nsacfg_nsp_ppc = 0, 156 .int_bit_mask = 0, 157 .is_initialized = false }; 158 struct ppc_rss_dev_t PPC_RSS_PERIPH0_DEV_S = { 159 &PPC_RSS_PERIPH0_CFG_S, 160 &PPC_RSS_PERIPH0_DATA_S }; 161 #endif 162 163 #ifdef PPC_RSS_PERIPH1_S 164 static struct ppc_rss_dev_cfg_t PPC_RSS_PERIPH1_CFG_S = { 165 .sacfg_base = RSS_SACFG_BASE_S, 166 .nsacfg_base = RSS_NSACFG_BASE_NS, 167 .ppc_name = PPC_RSS_PERIPH1}; 168 static struct ppc_rss_dev_data_t PPC_RSS_PERIPH1_DATA_S = { 169 .sacfg_ns_ppc = 0, 170 .sacfg_sp_ppc = 0, 171 .nsacfg_nsp_ppc = 0, 172 .int_bit_mask = 0, 173 .is_initialized = false }; 174 struct ppc_rss_dev_t PPC_RSS_PERIPH1_DEV_S = { 175 &PPC_RSS_PERIPH1_CFG_S, 176 &PPC_RSS_PERIPH1_DATA_S }; 177 #endif 178 179 #ifdef PPC_RSS_PERIPH_EXP0_S 180 static struct ppc_rss_dev_cfg_t PPC_RSS_PERIPH_EXP0_CFG_S = { 181 .sacfg_base = RSS_SACFG_BASE_S, 182 .nsacfg_base = RSS_NSACFG_BASE_NS, 183 .ppc_name = PPC_RSS_PERIPH_EXP0}; 184 static struct ppc_rss_dev_data_t PPC_RSS_PERIPH_EXP0_DATA_S = { 185 .sacfg_ns_ppc = 0, 186 .sacfg_sp_ppc = 0, 187 .nsacfg_nsp_ppc = 0, 188 .int_bit_mask = 0, 189 .is_initialized = false }; 190 struct ppc_rss_dev_t PPC_RSS_PERIPH_EXP0_DEV_S = { 191 &PPC_RSS_PERIPH_EXP0_CFG_S, 192 &PPC_RSS_PERIPH_EXP0_DATA_S }; 193 #endif 194 195 #ifdef PPC_RSS_PERIPH_EXP1_S 196 static struct ppc_rss_dev_cfg_t PPC_RSS_PERIPH_EXP1_CFG_S = { 197 .sacfg_base = RSS_SACFG_BASE_S, 198 .nsacfg_base = RSS_NSACFG_BASE_NS, 199 .ppc_name = PPC_RSS_PERIPH_EXP1}; 200 static struct ppc_rss_dev_data_t PPC_RSS_PERIPH_EXP1_DATA_S = { 201 .sacfg_ns_ppc = 0, 202 .sacfg_sp_ppc = 0, 203 .nsacfg_nsp_ppc = 0, 204 .int_bit_mask = 0, 205 .is_initialized = false }; 206 struct ppc_rss_dev_t PPC_RSS_PERIPH_EXP1_DEV_S = { 207 &PPC_RSS_PERIPH_EXP1_CFG_S, 208 &PPC_RSS_PERIPH_EXP1_DATA_S }; 209 #endif 210 211 #ifdef PPC_RSS_PERIPH_EXP2_S 212 static struct ppc_rss_dev_cfg_t PPC_RSS_PERIPH_EXP2_CFG_S = { 213 .sacfg_base = RSS_SACFG_BASE_S, 214 .nsacfg_base = RSS_NSACFG_BASE_NS, 215 .ppc_name = PPC_RSS_PERIPH_EXP2}; 216 static struct ppc_rss_dev_data_t PPC_RSS_PERIPH_EXP2_DATA_S = { 217 .sacfg_ns_ppc = 0, 218 .sacfg_sp_ppc = 0, 219 .nsacfg_nsp_ppc = 0, 220 .int_bit_mask = 0, 221 .is_initialized = false }; 222 struct ppc_rss_dev_t PPC_RSS_PERIPH_EXP2_DEV_S = { 223 &PPC_RSS_PERIPH_EXP2_CFG_S, 224 &PPC_RSS_PERIPH_EXP2_DATA_S }; 225 #endif 226 227 #ifdef PPC_RSS_PERIPH_EXP3_S 228 static struct ppc_rss_dev_cfg_t PPC_RSS_PERIPH_EXP3_CFG_S = { 229 .sacfg_base = RSS_SACFG_BASE_S, 230 .nsacfg_base = RSS_NSACFG_BASE_NS, 231 .ppc_name = PPC_RSS_PERIPH_EXP3}; 232 static struct ppc_rss_dev_data_t PPC_RSS_PERIPH_EXP3_DATA_S = { 233 .sacfg_ns_ppc = 0, 234 .sacfg_sp_ppc = 0, 235 .nsacfg_nsp_ppc = 0, 236 .int_bit_mask = 0, 237 .is_initialized = false }; 238 struct ppc_rss_dev_t PPC_RSS_PERIPH_EXP3_DEV_S = { 239 &PPC_RSS_PERIPH_EXP3_CFG_S, 240 &PPC_RSS_PERIPH_EXP3_DATA_S }; 241 #endif 242 243 /* System counters */ 244 #ifdef SYSCOUNTER_CNTRL_ARMV8_M_S 245 246 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT > \ 247 SYSCOUNTER_ARMV8_M_SCALE_VAL_INT_MAX 248 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT is invalid. 249 #endif 250 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT > \ 251 SYSCOUNTER_ARMV8_M_SCALE_VAL_FRACT_MAX 252 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT is invalid. 253 #endif 254 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT > \ 255 SYSCOUNTER_ARMV8_M_SCALE_VAL_INT_MAX 256 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT is invalid. 257 #endif 258 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT > \ 259 SYSCOUNTER_ARMV8_M_SCALE_VAL_FRACT_MAX 260 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT is invalid. 261 #endif 262 263 static const struct syscounter_armv8_m_cntrl_dev_cfg_t 264 SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_S = { 265 .base = SYSCNTR_CNTRL_BASE_S, 266 .scale0.integer = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT, 267 .scale0.fixed_point_fraction = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT, 268 .scale1.integer = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT, 269 .scale1.fixed_point_fraction = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 270 }; 271 static struct syscounter_armv8_m_cntrl_dev_data_t 272 SYSCOUNTER_CNTRL_ARMV8_M_DEV_DATA_S = { 273 .is_initialized = false 274 }; 275 struct syscounter_armv8_m_cntrl_dev_t SYSCOUNTER_CNTRL_ARMV8_M_DEV_S = { 276 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_S), 277 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_DATA_S) 278 }; 279 #endif 280 281 #ifdef SYSCOUNTER_READ_ARMV8_M_S 282 static const struct syscounter_armv8_m_read_dev_cfg_t 283 SYSCOUNTER_READ_ARMV8_M_DEV_CFG_S = { 284 .base = SYSCNTR_READ_BASE_S, 285 }; 286 struct syscounter_armv8_m_read_dev_t SYSCOUNTER_READ_ARMV8_M_DEV_S = { 287 &(SYSCOUNTER_READ_ARMV8_M_DEV_CFG_S), 288 }; 289 #endif 290 291 /* System timers */ 292 #ifdef SYSTIMER0_ARMV8_M_S 293 static const struct systimer_armv8_m_dev_cfg_t 294 SYSTIMER0_ARMV8_M_DEV_CFG_S = { 295 .base = SYSTIMER0_ARMV8_M_BASE_S, 296 .default_freq_hz = SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ 297 }; 298 static struct systimer_armv8_m_dev_data_t 299 SYSTIMER0_ARMV8_M_DEV_DATA_S = { 300 .is_initialized = false 301 }; 302 struct systimer_armv8_m_dev_t SYSTIMER0_ARMV8_M_DEV_S = { 303 &(SYSTIMER0_ARMV8_M_DEV_CFG_S), 304 &(SYSTIMER0_ARMV8_M_DEV_DATA_S) 305 }; 306 #endif 307 308 #ifdef SYSTIMER0_ARMV8_M_NS 309 static const struct systimer_armv8_m_dev_cfg_t 310 SYSTIMER0_ARMV8_M_DEV_CFG_NS = { 311 .base = SYSTIMER0_ARMV8_M_BASE_NS, 312 .default_freq_hz = SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ 313 }; 314 static struct systimer_armv8_m_dev_data_t 315 SYSTIMER0_ARMV8_M_DEV_DATA_NS = { 316 .is_initialized = false 317 }; 318 struct systimer_armv8_m_dev_t SYSTIMER0_ARMV8_M_DEV_NS = { 319 &(SYSTIMER0_ARMV8_M_DEV_CFG_NS), 320 &(SYSTIMER0_ARMV8_M_DEV_DATA_NS) 321 }; 322 #endif 323 324 #ifdef SYSTIMER1_ARMV8_M_S 325 static const struct systimer_armv8_m_dev_cfg_t 326 SYSTIMER1_ARMV8_M_DEV_CFG_S = { 327 .base = SYSTIMER1_ARMV8_M_BASE_S, 328 .default_freq_hz = SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ 329 }; 330 static struct systimer_armv8_m_dev_data_t 331 SYSTIMER1_ARMV8_M_DEV_DATA_S = { 332 .is_initialized = false 333 }; 334 struct systimer_armv8_m_dev_t SYSTIMER1_ARMV8_M_DEV_S = { 335 &(SYSTIMER1_ARMV8_M_DEV_CFG_S), 336 &(SYSTIMER1_ARMV8_M_DEV_DATA_S) 337 }; 338 #endif 339 340 #ifdef SYSTIMER1_ARMV8_M_NS 341 static const struct systimer_armv8_m_dev_cfg_t 342 SYSTIMER1_ARMV8_M_DEV_CFG_NS = { 343 .base = SYSTIMER1_ARMV8_M_BASE_NS, 344 .default_freq_hz = SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ 345 }; 346 static struct systimer_armv8_m_dev_data_t 347 SYSTIMER1_ARMV8_M_DEV_DATA_NS = { 348 .is_initialized = false 349 }; 350 struct systimer_armv8_m_dev_t SYSTIMER1_ARMV8_M_DEV_NS = { 351 &(SYSTIMER1_ARMV8_M_DEV_CFG_NS), 352 &(SYSTIMER1_ARMV8_M_DEV_DATA_NS) 353 }; 354 #endif 355 356 #ifdef SYSTIMER2_ARMV8_M_S 357 static const struct systimer_armv8_m_dev_cfg_t 358 SYSTIMER2_ARMV8_M_DEV_CFG_S = { 359 .base = SYSTIMER2_ARMV8_M_BASE_S, 360 .default_freq_hz = SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ 361 }; 362 static struct systimer_armv8_m_dev_data_t 363 SYSTIMER2_ARMV8_M_DEV_DATA_S = { 364 .is_initialized = false 365 }; 366 struct systimer_armv8_m_dev_t SYSTIMER2_ARMV8_M_DEV_S = { 367 &(SYSTIMER2_ARMV8_M_DEV_CFG_S), 368 &(SYSTIMER2_ARMV8_M_DEV_DATA_S) 369 }; 370 #endif 371 372 #ifdef SYSTIMER2_ARMV8_M_NS 373 static const struct systimer_armv8_m_dev_cfg_t 374 SYSTIMER2_ARMV8_M_DEV_CFG_NS = { 375 .base = SYSTIMER2_ARMV8_M_BASE_NS, 376 .default_freq_hz = SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ 377 }; 378 static struct systimer_armv8_m_dev_data_t 379 SYSTIMER2_ARMV8_M_DEV_DATA_NS = { 380 .is_initialized = false 381 }; 382 struct systimer_armv8_m_dev_t SYSTIMER2_ARMV8_M_DEV_NS = { 383 &(SYSTIMER2_ARMV8_M_DEV_CFG_NS), 384 &(SYSTIMER2_ARMV8_M_DEV_DATA_NS) 385 }; 386 #endif 387 388 #ifdef SYSTIMER3_ARMV8_M_S 389 static const struct systimer_armv8_m_dev_cfg_t 390 SYSTIMER3_ARMV8_M_DEV_CFG_S = { 391 .base = SYSTIMER3_ARMV8_M_BASE_S, 392 .default_freq_hz = SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ 393 }; 394 static struct systimer_armv8_m_dev_data_t 395 SYSTIMER3_ARMV8_M_DEV_DATA_S = { 396 .is_initialized = false 397 }; 398 struct systimer_armv8_m_dev_t SYSTIMER3_ARMV8_M_DEV_S = { 399 &(SYSTIMER3_ARMV8_M_DEV_CFG_S), 400 &(SYSTIMER3_ARMV8_M_DEV_DATA_S) 401 }; 402 #endif 403 404 #ifdef SYSTIMER3_ARMV8_M_NS 405 static const struct systimer_armv8_m_dev_cfg_t 406 SYSTIMER3_ARMV8_M_DEV_CFG_NS = { 407 .base = SYSTIMER3_ARMV8_M_BASE_NS, 408 .default_freq_hz = SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ 409 }; 410 static struct systimer_armv8_m_dev_data_t 411 SYSTIMER3_ARMV8_M_DEV_DATA_NS = { 412 .is_initialized = false 413 }; 414 struct systimer_armv8_m_dev_t SYSTIMER3_ARMV8_M_DEV_NS = { 415 &(SYSTIMER3_ARMV8_M_DEV_CFG_NS), 416 &(SYSTIMER3_ARMV8_M_DEV_DATA_NS) 417 }; 418 #endif 419 420 /* System Watchdogs */ 421 #ifdef SYSWDOG_ARMV8_M_S 422 static const struct syswdog_armv8_m_dev_cfg_t 423 SYSWDOG_ARMV8_M_DEV_CFG_S = { 424 .base = SYSWDOG_ARMV8_M_CNTRL_BASE_S 425 }; 426 struct syswdog_armv8_m_dev_t SYSWDOG_ARMV8_M_DEV_S = { 427 &(SYSWDOG_ARMV8_M_DEV_CFG_S) 428 }; 429 #endif 430 431 #ifdef SYSWDOG_ARMV8_M_NS 432 static const struct syswdog_armv8_m_dev_cfg_t 433 SYSWDOG_ARMV8_M_DEV_CFG_NS = { 434 .base = SYSWDOG_ARMV8_M_CNTRL_BASE_NS 435 }; 436 struct syswdog_armv8_m_dev_t SYSWDOG_ARMV8_M_DEV_NS = { 437 &(SYSWDOG_ARMV8_M_DEV_CFG_NS) 438 }; 439 #endif 440 441 /* ARM MPC RSS driver structures */ 442 #ifdef MPC_VM0_S 443 static const struct mpc_sie_dev_cfg_t MPC_VM0_DEV_CFG_S = { 444 .base = MPC_VM0_BASE_S}; 445 static struct mpc_sie_dev_data_t MPC_VM0_DEV_DATA_S = { 446 .range_list = 0, 447 .nbr_of_ranges = 0, 448 .is_initialized = false }; 449 struct mpc_sie_dev_t MPC_VM0_DEV_S = { 450 &(MPC_VM0_DEV_CFG_S), 451 &(MPC_VM0_DEV_DATA_S)}; 452 #endif 453 454 #ifdef MPC_VM1_S 455 static const struct mpc_sie_dev_cfg_t MPC_VM1_DEV_CFG_S = { 456 .base = MPC_VM1_BASE_S}; 457 static struct mpc_sie_dev_data_t MPC_VM1_DEV_DATA_S = { 458 .range_list = 0, 459 .nbr_of_ranges = 0, 460 .is_initialized = false }; 461 struct mpc_sie_dev_t MPC_VM1_DEV_S = { 462 &(MPC_VM1_DEV_CFG_S), 463 &(MPC_VM1_DEV_DATA_S)}; 464 #endif 465 466 /* Message Handling Units (MHU) */ 467 #ifdef MHU_AP_TO_RSS 468 struct mhu_v2_x_dev_t MHU_AP_TO_RSS_DEV = { 469 MHU0_RECEIVER_BASE_S, 470 MHU_V2_X_RECEIVER_FRAME}; 471 #endif 472 473 #ifdef MHU_RSS_TO_AP 474 struct mhu_v2_x_dev_t MHU_RSS_TO_AP_DEV = { 475 MHU0_SENDER_BASE_S, 476 MHU_V2_X_SENDER_FRAME}; 477 #endif 478 479 #ifdef MHU_SCP_TO_RSS 480 struct mhu_v2_x_dev_t MHU_SCP_TO_RSS_DEV = { 481 MHU2_RECEIVER_BASE_S, 482 MHU_V2_X_RECEIVER_FRAME}; 483 #endif 484 485 #ifdef MHU_RSS_TO_SCP 486 struct mhu_v2_x_dev_t MHU_RSS_TO_SCP_DEV = { 487 MHU2_SENDER_BASE_S, 488 MHU_V2_X_SENDER_FRAME}; 489 #endif 490 491 #ifdef KMU_S 492 static struct kmu_dev_cfg_t KMU_DEV_CFG_S = { 493 .base = KMU_BASE_S 494 }; 495 struct kmu_dev_t KMU_DEV_S = { 496 .cfg = &(KMU_DEV_CFG_S) 497 }; 498 #endif 499 500 #ifdef LCM_S 501 static struct lcm_dev_cfg_t LCM_DEV_CFG_S = { 502 .base = LCM_BASE_S 503 }; 504 struct lcm_dev_t LCM_DEV_S = { 505 .cfg = &(LCM_DEV_CFG_S) 506 }; 507 #endif 508 509 #ifdef DMA350_DMA0_S 510 static const struct dma350_dev_cfg_t DMA350_DMA0_DEV_CFG_S = { 511 .dma_sec_cfg = (DMASECCFG_TypeDef*) (DMA_350_BASE_S + 0x0UL), 512 .dma_sec_ctrl = (DMASECCTRL_TypeDef*) (DMA_350_BASE_S + 0x100UL), 513 .dma_nsec_ctrl = (DMANSECCTRL_TypeDef*) (DMA_350_BASE_S + 0x200UL), 514 .dma_info = (DMAINFO_TypeDef*) (DMA_350_BASE_S + 0xF00UL) 515 }; 516 static struct dma350_dev_data_t DMA350_DMA0_DEV_DATA_S = { 517 .state = 0 518 }; 519 struct dma350_dev_t DMA350_DMA0_DEV_S = { 520 &(DMA350_DMA0_DEV_CFG_S), 521 &(DMA350_DMA0_DEV_DATA_S) 522 }; 523 #endif 524 525 #ifdef DMA350_DMA0_CH0_S 526 struct dma350_ch_dev_t DMA350_DMA0_CH0_DEV_S = { 527 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1000UL), 528 .channel = 0}, 529 .data = {0} 530 }; 531 #endif 532 533 #ifdef DMA350_DMA0_CH1_S 534 struct dma350_ch_dev_t DMA350_DMA0_CH1_DEV_S = { 535 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1100UL), 536 .channel = 1}, 537 .data = {0} 538 }; 539 #endif 540 541 #ifdef DMA350_DMA0_CH2_S 542 struct dma350_ch_dev_t DMA350_DMA0_CH2_DEV_S = { 543 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1200UL), 544 .channel = 2}, 545 .data = {0} 546 }; 547 #endif 548 549 #ifdef DMA350_DMA0_CH3_S 550 struct dma350_ch_dev_t DMA350_DMA0_CH3_DEV_S = { 551 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1300UL), 552 .channel = 3}, 553 .data = {0} 554 }; 555 #endif 556
