1 /*
2 * Copyright (c) 2022 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c
21 * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
22 */
23
24 #include "cmsis.h"
25
26 /*----------------------------------------------------------------------------
27 External References
28 *----------------------------------------------------------------------------*/
29 extern uint32_t __INITIAL_SP;
30 extern uint32_t __STACK_LIMIT;
31 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
32 extern uint64_t __STACK_SEAL;
33 #endif
34
35 extern void __PROGRAM_START(void) __NO_RETURN;
36
37 /*----------------------------------------------------------------------------
38 Internal References
39 *----------------------------------------------------------------------------*/
40 void Reset_Handler (void) __NO_RETURN;
41
42 /*----------------------------------------------------------------------------
43 Exception / Interrupt Handler
44 *----------------------------------------------------------------------------*/
45 #define DEFAULT_IRQ_HANDLER(handler_name) \
46 void __WEAK handler_name(void) __NO_RETURN; \
47 void handler_name(void) { \
48 while(1); \
49 }
50
51 /* Exceptions */
52 DEFAULT_IRQ_HANDLER(NMI_Handler)
53 DEFAULT_IRQ_HANDLER(HardFault_Handler)
54 DEFAULT_IRQ_HANDLER(MemManage_Handler)
55 DEFAULT_IRQ_HANDLER(BusFault_Handler)
56 DEFAULT_IRQ_HANDLER(UsageFault_Handler)
57 DEFAULT_IRQ_HANDLER(SecureFault_Handler)
58 DEFAULT_IRQ_HANDLER(SVC_Handler)
59 DEFAULT_IRQ_HANDLER(DebugMon_Handler)
60 DEFAULT_IRQ_HANDLER(PendSV_Handler)
61 DEFAULT_IRQ_HANDLER(SysTick_Handler)
62
63 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
64 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
65 DEFAULT_IRQ_HANDLER(S32K_TIMER_Handler)
66 DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
67 DEFAULT_IRQ_HANDLER(TIMER1_Handler)
68 DEFAULT_IRQ_HANDLER(DUALTIMER_Handler)
69 DEFAULT_IRQ_HANDLER(MHU0_Handler)
70 DEFAULT_IRQ_HANDLER(MHU1_Handler)
71 DEFAULT_IRQ_HANDLER(CRYPTOCELL_Handler)
72 DEFAULT_IRQ_HANDLER(MPC_Handler)
73 DEFAULT_IRQ_HANDLER(PPC_Handler)
74 DEFAULT_IRQ_HANDLER(MSC_Handler)
75 DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
76 DEFAULT_IRQ_HANDLER(INVALID_INSTR_CACHE_Handler)
77 DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
78 DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
79 DEFAULT_IRQ_HANDLER(CPU1_PPU_Handler)
80 DEFAULT_IRQ_HANDLER(CPU0_DBG_PPU_Handler)
81 DEFAULT_IRQ_HANDLER(CPU1_DBG_PPU_Handler)
82 DEFAULT_IRQ_HANDLER(CRYPT_PPU_Handler)
83 DEFAULT_IRQ_HANDLER(RAM0_PPU_Handler)
84 DEFAULT_IRQ_HANDLER(RAM1_PPU_Handler)
85 DEFAULT_IRQ_HANDLER(RAM2_PPU_Handler)
86 DEFAULT_IRQ_HANDLER(RAM3_PPU_Handler)
87 DEFAULT_IRQ_HANDLER(DBG_PPU_Handler)
88 DEFAULT_IRQ_HANDLER(CPU0_CTI_Handler)
89 DEFAULT_IRQ_HANDLER(CPU1_CTI_Handler)
90
91 DEFAULT_IRQ_HANDLER(GpTimer_IRQHandler)
92 DEFAULT_IRQ_HANDLER(I2C0_IRQHandler)
93 DEFAULT_IRQ_HANDLER(I2C1_IRQHandler)
94 DEFAULT_IRQ_HANDLER(I2S_IRQHandler)
95 DEFAULT_IRQ_HANDLER(SPI_IRQHandler)
96 DEFAULT_IRQ_HANDLER(QSPI_IRQHandler)
97 DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
98 DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
99 DEFAULT_IRQ_HANDLER(UART0_RxTimeout_IRQHandler)
100 DEFAULT_IRQ_HANDLER(UART0_ModemStatus_IRQHandler)
101 DEFAULT_IRQ_HANDLER(UART0_Error_IRQHandler)
102 DEFAULT_IRQ_HANDLER(UART0_IRQHandler)
103 DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
104 DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
105 DEFAULT_IRQ_HANDLER(UART1_RxTimeout_IRQHandler)
106 DEFAULT_IRQ_HANDLER(UART1_ModemStatus_IRQHandler)
107 DEFAULT_IRQ_HANDLER(UART1_Error_IRQHandler)
108 DEFAULT_IRQ_HANDLER(UART1_IRQHandler)
109 DEFAULT_IRQ_HANDLER(GPIO_0_IRQHandler)
110 DEFAULT_IRQ_HANDLER(GPIO_1_IRQHandler)
111 DEFAULT_IRQ_HANDLER(GPIO_2_IRQHandler)
112 DEFAULT_IRQ_HANDLER(GPIO_3_IRQHandler)
113 DEFAULT_IRQ_HANDLER(GPIO_4_IRQHandler)
114 DEFAULT_IRQ_HANDLER(GPIO_5_IRQHandler)
115 DEFAULT_IRQ_HANDLER(GPIO_6_IRQHandler)
116 DEFAULT_IRQ_HANDLER(GPIO_7_IRQHandler)
117 DEFAULT_IRQ_HANDLER(GPIO_8_IRQHandler)
118 DEFAULT_IRQ_HANDLER(GPIO_9_IRQHandler)
119 DEFAULT_IRQ_HANDLER(GPIO_10_IRQHandler)
120 DEFAULT_IRQ_HANDLER(GPIO_11_IRQHandler)
121 DEFAULT_IRQ_HANDLER(GPIO_12_IRQHandler)
122 DEFAULT_IRQ_HANDLER(GPIO_13_IRQHandler)
123 DEFAULT_IRQ_HANDLER(GPIO_14_IRQHandler)
124 DEFAULT_IRQ_HANDLER(GPIO_15_IRQHandler)
125 DEFAULT_IRQ_HANDLER(Combined_IRQHandler)
126 DEFAULT_IRQ_HANDLER(PVT_IRQHandler)
127 DEFAULT_IRQ_HANDLER(PWM_0_IRQHandler)
128 DEFAULT_IRQ_HANDLER(RTC_IRQHandler)
129 DEFAULT_IRQ_HANDLER(GpTimer0_IRQHandler)
130 DEFAULT_IRQ_HANDLER(GpTimer1_IRQHandler)
131 DEFAULT_IRQ_HANDLER(PWM_1_IRQHandler)
132 DEFAULT_IRQ_HANDLER(PWM_2_IRQHandler)
133 DEFAULT_IRQ_HANDLER(IOMUX_IRQHandler)
134
135 /*----------------------------------------------------------------------------
136 Exception / Interrupt Vector table
137 *----------------------------------------------------------------------------*/
138
139 #if defined ( __GNUC__ )
140 #pragma GCC diagnostic push
141 #pragma GCC diagnostic ignored "-Wpedantic"
142 #endif
143
144 extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
145 const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
146 (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
147 Reset_Handler, /* Reset Handler */
148 NMI_Handler, /* -14: NMI Handler */
149 HardFault_Handler, /* -13: Hard Fault Handler */
150 MemManage_Handler, /* -12: MPU Fault Handler */
151 BusFault_Handler, /* -11: Bus Fault Handler */
152 UsageFault_Handler, /* -10: Usage Fault Handler */
153 SecureFault_Handler, /* -9: Secure Fault Handler */
154 0, /* -8: Reserved */
155 0, /* -7: Reserved */
156 0, /* -6: Reserved */
157 SVC_Handler, /* -5: SVCall Handler */
158 DebugMon_Handler, /* -4: Debug Monitor Handler */
159 0, /* -3: Reserved */
160 PendSV_Handler, /* -2: PendSV Handler */
161 SysTick_Handler, /* -1: SysTick Handler */
162
163 NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
164 NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Interrupt Handler */
165 S32K_TIMER_Handler, /* 2: S32K Timer Handler */
166 TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
167 TIMER1_Handler, /* 4: TIMER 1 Handler */
168 DUALTIMER_Handler, /* 5: Dual Timer Handler */
169 MHU0_Handler, /* 6: Message Handling Unit 0 */
170 MHU1_Handler, /* 7: Message Handling Unit 1 */
171 CRYPTOCELL_Handler, /* 8: CryptoCell-312 Handler */
172 MPC_Handler, /* 9: MPC Combined (Secure) Handler */
173 PPC_Handler, /* 10: PPC Combined (Secure) Handler */
174 MSC_Handler, /* 11: MSC Combined (Secure) Handler */
175 BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
176 INVALID_INSTR_CACHE_Handler, /* 13: CPU Instruction Cache Invalidation Handler */
177 0, /* 14: Reserved */
178 SYS_PPU_Handler, /* 15: SYS PPU Handler */
179 CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
180 CPU1_PPU_Handler, /* 17: CPU1 PPU Handler */
181 CPU0_DBG_PPU_Handler, /* 18: CPU0 DBG PPU_Handler */
182 CPU1_DBG_PPU_Handler, /* 19: CPU1 DBG PPU_Handler */
183 CRYPT_PPU_Handler, /* 20: CRYPT PPU Handler */
184 0, /* 21: Reserved */
185 RAM0_PPU_Handler, /* 22: RAM0 PPU Handler */
186 RAM1_PPU_Handler, /* 23: RAM1 PPU Handler */
187 RAM2_PPU_Handler, /* 24: RAM2 PPU Handler */
188 RAM3_PPU_Handler, /* 25: RAM3 PPU Handler */
189 DBG_PPU_Handler, /* 26: DBG PPU Handler */
190 0, /* 27: Reserved */
191 CPU0_CTI_Handler, /* 28: CPU0 CTI Handler */
192 CPU1_CTI_Handler, /* 29: CPU1 CTI Handler */
193 0, /* 30: Reserved */
194 0, /* 31: Reserved */
195
196 /* External interrupts */
197 0, /* 32: Reserved */
198 GpTimer_IRQHandler, /* 33: General Purpose Timer */
199 I2C0_IRQHandler, /* 34: I2C0 */
200 I2C1_IRQHandler, /* 35: I2C1 */
201 I2S_IRQHandler, /* 36: I2S */
202 SPI_IRQHandler, /* 37: SPI */
203 QSPI_IRQHandler, /* 38: QSPI */
204 UARTRX0_Handler, /* 39: UART0 receive FIFO interrupt */
205 UARTTX0_Handler, /* 40: UART0 transmit FIFO interrupt */
206 UART0_RxTimeout_IRQHandler, /* 41: UART0 receive timeout interrupt */
207 UART0_ModemStatus_IRQHandler, /* 42: UART0 modem status interrupt */
208 UART0_Error_IRQHandler, /* 43: UART0 error interrupt */
209 UART0_IRQHandler, /* 44: UART0 interrupt */
210 UARTRX1_Handler, /* 45: UART0 receive FIFO interrupt */
211 UARTTX1_Handler, /* 46: UART0 transmit FIFO interrupt */
212 UART1_RxTimeout_IRQHandler, /* 47: UART0 receive timeout interrupt */
213 UART1_ModemStatus_IRQHandler, /* 48: UART0 modem status interrupt */
214 UART1_Error_IRQHandler, /* 49: UART0 error interrupt */
215 UART1_IRQHandler, /* 50: UART0 interrupt */
216 GPIO_0_IRQHandler, /* 51: GPIO 0 interrupt */
217 GPIO_1_IRQHandler, /* 52: GPIO 1 interrupt */
218 GPIO_2_IRQHandler, /* 53: GPIO 2 interrupt */
219 GPIO_3_IRQHandler, /* 54: GPIO 3 interrupt */
220 GPIO_4_IRQHandler, /* 55: GPIO 4 interrupt */
221 GPIO_5_IRQHandler, /* 56: GPIO 5 interrupt */
222 GPIO_6_IRQHandler, /* 57: GPIO 6 interrupt */
223 GPIO_7_IRQHandler, /* 58: GPIO 7 interrupt */
224 GPIO_8_IRQHandler, /* 59: GPIO 8 interrupt */
225 GPIO_9_IRQHandler, /* 60: GPIO 9 interrupt */
226 GPIO_10_IRQHandler, /* 61: GPIO 10 interrupt */
227 GPIO_11_IRQHandler, /* 62: GPIO 11 interrupt */
228 GPIO_12_IRQHandler, /* 63: GPIO 12 interrupt */
229 GPIO_13_IRQHandler, /* 64: GPIO 13 interrupt */
230 GPIO_14_IRQHandler, /* 65: GPIO 14 interrupt */
231 GPIO_15_IRQHandler, /* 66: GPIO 15 interrupt */
232 Combined_IRQHandler, /* 67: Combined interrupt */
233 PVT_IRQHandler, /* 68: PVT sensor interrupt */
234 0, /* 69: Reserved */
235 PWM_0_IRQHandler, /* 70: PWM0 interrupt */
236 RTC_IRQHandler, /* 71: RTC interrupt */
237 GpTimer0_IRQHandler, /* 72: General Purpose Timer0 */
238 GpTimer1_IRQHandler, /* 73: General Purpose Timer1 */
239 PWM_1_IRQHandler, /* 74: PWM1 interrupt */
240 PWM_2_IRQHandler, /* 75: PWM2 interrupt */
241 IOMUX_IRQHandler, /* 76: IOMUX interrupt */
242 };
243
244 #if defined ( __GNUC__ )
245 #pragma GCC diagnostic pop
246 #endif
247
248 /*----------------------------------------------------------------------------
249 Reset Handler called on controller reset
250 *----------------------------------------------------------------------------*/
Reset_Handler(void)251 void Reset_Handler(void)
252 {
253 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
254 __disable_irq();
255 #endif
256 __set_PSP((uint32_t)(&__INITIAL_SP));
257
258 __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
259 __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
260
261 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
262 __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
263 #endif
264
265 SystemInit(); /* CMSIS System Initialization */
266 __PROGRAM_START(); /* Enter PreMain (C library entry point) */
267 }
268
