1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file device_definition.c 19 * \brief This file defines exports the structures based on the peripheral 20 * definitions from device_cfg.h. 21 * This file is meant to be used as a helper for baremetal 22 * applications and/or as an example of how to configure the generic 23 * driver structures. 24 */ 25 26 #include "device_definition.h" 27 #include "platform_base_address.h" 28 #include "platform/include/tfm_plat_defs.h" 29 30 /* UART CMSDK driver structures */ 31 #ifdef UART0_CMSDK_S 32 static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = { 33 .base = UART0_BASE_S, 34 .default_baudrate = DEFAULT_UART_BAUDRATE 35 }; 36 static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = { 37 .state = 0, 38 .system_clk = 0, 39 .baudrate = 0 40 }; 41 struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S = { 42 &(UART0_CMSDK_DEV_CFG_S), 43 &(UART0_CMSDK_DEV_DATA_S) 44 }; 45 #endif 46 #ifdef UART0_CMSDK_NS 47 static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_NS = { 48 .base = UART0_BASE_NS, 49 .default_baudrate = DEFAULT_UART_BAUDRATE 50 }; 51 static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = { 52 .state = 0, 53 .system_clk = 0, 54 .baudrate = 0 55 }; 56 struct uart_cmsdk_dev_t UART0_CMSDK_DEV_NS = { 57 &(UART0_CMSDK_DEV_CFG_NS), 58 &(UART0_CMSDK_DEV_DATA_NS) 59 }; 60 #endif 61 62 #ifdef UART1_CMSDK_S 63 static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_S = { 64 .base = UART1_BASE_S, 65 .default_baudrate = DEFAULT_UART_BAUDRATE 66 }; 67 static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_S = { 68 .state = 0, 69 .system_clk = 0, 70 .baudrate = 0 71 }; 72 struct uart_cmsdk_dev_t UART1_CMSDK_DEV_S = { 73 &(UART1_CMSDK_DEV_CFG_S), 74 &(UART1_CMSDK_DEV_DATA_S) 75 }; 76 #endif 77 #ifdef UART1_CMSDK_NS 78 static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_NS = { 79 .base = UART1_BASE_NS, 80 .default_baudrate = DEFAULT_UART_BAUDRATE 81 }; 82 static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_NS = { 83 .state = 0, 84 .system_clk = 0, 85 .baudrate = 0 86 }; 87 struct uart_cmsdk_dev_t UART1_CMSDK_DEV_NS = { 88 &(UART1_CMSDK_DEV_CFG_NS), 89 &(UART1_CMSDK_DEV_DATA_NS) 90 }; 91 #endif 92 93 #ifdef UART2_CMSDK_S 94 static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_S = { 95 .base = UART2_BASE_S, 96 .default_baudrate = DEFAULT_UART_BAUDRATE 97 }; 98 static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_S = { 99 .state = 0, 100 .system_clk = 0, 101 .baudrate = 0 102 }; 103 struct uart_cmsdk_dev_t UART2_CMSDK_DEV_S = { 104 &(UART2_CMSDK_DEV_CFG_S), 105 &(UART2_CMSDK_DEV_DATA_S) 106 }; 107 #endif 108 #ifdef UART2_CMSDK_NS 109 static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_NS = { 110 .base = UART2_BASE_NS, 111 .default_baudrate = DEFAULT_UART_BAUDRATE 112 }; 113 static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_NS = { 114 .state = 0, 115 .system_clk = 0, 116 .baudrate = 0 117 }; 118 struct uart_cmsdk_dev_t UART2_CMSDK_DEV_NS = { 119 &(UART2_CMSDK_DEV_CFG_NS), 120 &(UART2_CMSDK_DEV_DATA_NS) 121 }; 122 #endif 123 124 #ifdef UART3_CMSDK_S 125 static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_S = { 126 .base = UART3_BASE_S, 127 .default_baudrate = DEFAULT_UART_BAUDRATE 128 }; 129 static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_S = { 130 .state = 0, 131 .system_clk = 0, 132 .baudrate = 0 133 }; 134 struct uart_cmsdk_dev_t UART3_CMSDK_DEV_S = { 135 &(UART3_CMSDK_DEV_CFG_S), 136 &(UART3_CMSDK_DEV_DATA_S) 137 }; 138 #endif 139 #ifdef UART3_CMSDK_NS 140 static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_NS = { 141 .base = UART3_BASE_NS, 142 .default_baudrate = DEFAULT_UART_BAUDRATE 143 }; 144 static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_NS = { 145 .state = 0, 146 .system_clk = 0, 147 .baudrate = 0 148 }; 149 struct uart_cmsdk_dev_t UART3_CMSDK_DEV_NS = { 150 &(UART3_CMSDK_DEV_CFG_NS), 151 &(UART3_CMSDK_DEV_DATA_NS) 152 }; 153 #endif 154 155 #ifdef UART4_CMSDK_S 156 static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_S = { 157 .base = UART4_BASE_S, 158 .default_baudrate = DEFAULT_UART_BAUDRATE 159 }; 160 static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_S = { 161 .state = 0, 162 .system_clk = 0, 163 .baudrate = 0 164 }; 165 struct uart_cmsdk_dev_t UART4_CMSDK_DEV_S = { 166 &(UART4_CMSDK_DEV_CFG_S), 167 &(UART4_CMSDK_DEV_DATA_S) 168 }; 169 #endif 170 #ifdef UART4_CMSDK_NS 171 static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_NS = { 172 .base = UART4_BASE_NS, 173 .default_baudrate = DEFAULT_UART_BAUDRATE 174 }; 175 static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_NS = { 176 .state = 0, 177 .system_clk = 0, 178 .baudrate = 0 179 }; 180 struct uart_cmsdk_dev_t UART4_CMSDK_DEV_NS = { 181 &(UART4_CMSDK_DEV_CFG_NS), 182 &(UART4_CMSDK_DEV_DATA_NS) 183 }; 184 #endif 185 186 #ifdef UART5_CMSDK_S 187 static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_S = { 188 .base = UART5_BASE_S, 189 .default_baudrate = DEFAULT_UART_BAUDRATE 190 }; 191 static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_S = { 192 .state = 0, 193 .system_clk = 0, 194 .baudrate = 0 195 }; 196 struct uart_cmsdk_dev_t UART5_CMSDK_DEV_S = { 197 &(UART5_CMSDK_DEV_CFG_S), 198 &(UART5_CMSDK_DEV_DATA_S) 199 }; 200 #endif 201 #ifdef UART5_CMSDK_NS 202 static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_NS = { 203 .base = UART5_BASE_NS, 204 .default_baudrate = DEFAULT_UART_BAUDRATE 205 }; 206 static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_NS = { 207 .state = 0, 208 .system_clk = 0, 209 .baudrate = 0 210 }; 211 struct uart_cmsdk_dev_t UART5_CMSDK_DEV_NS = { 212 &(UART5_CMSDK_DEV_CFG_NS), 213 &(UART5_CMSDK_DEV_DATA_NS) 214 }; 215 #endif 216 217 /* SSE-300 PPC driver structures */ 218 #ifdef PPC_SSE300_MAIN0_S 219 static struct ppc_sse300_dev_cfg_t PPC_SSE300_MAIN0_CFG_S = { 220 .sacfg_base = SSE300_SACFG_BASE_S, 221 .nsacfg_base = SSE300_NSACFG_BASE_NS, 222 .ppc_name = PPC_SSE300_MAIN0}; 223 static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN0_DATA_S = { 224 .sacfg_ns_ppc = 0, 225 .sacfg_sp_ppc = 0, 226 .nsacfg_nsp_ppc = 0, 227 .int_bit_mask = 0, 228 .is_initialized = false }; 229 struct ppc_sse300_dev_t PPC_SSE300_MAIN0_DEV_S = { 230 &PPC_SSE300_MAIN0_CFG_S, 231 &PPC_SSE300_MAIN0_DATA_S }; 232 #endif 233 234 #ifdef PPC_SSE300_MAIN_EXP0_S 235 static struct ppc_sse300_dev_cfg_t PPC_SSE300_MAIN_EXP0_CFG_S = { 236 .sacfg_base = SSE300_SACFG_BASE_S, 237 .nsacfg_base = SSE300_NSACFG_BASE_NS, 238 .ppc_name = PPC_SSE300_MAIN_EXP0}; 239 static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP0_DATA_S = { 240 .sacfg_ns_ppc = 0, 241 .sacfg_sp_ppc = 0, 242 .nsacfg_nsp_ppc = 0, 243 .int_bit_mask = 0, 244 .is_initialized = false }; 245 struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP0_DEV_S = { 246 &PPC_SSE300_MAIN_EXP0_CFG_S, 247 &PPC_SSE300_MAIN_EXP0_DATA_S }; 248 #endif 249 250 #ifdef PPC_SSE300_MAIN_EXP1_S 251 static struct ppc_sse300_dev_cfg_t PPC_SSE300_MAIN_EXP1_CFG_S = { 252 .sacfg_base = SSE300_SACFG_BASE_S, 253 .nsacfg_base = SSE300_NSACFG_BASE_NS, 254 .ppc_name = PPC_SSE300_MAIN_EXP1}; 255 static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP1_DATA_S = { 256 .sacfg_ns_ppc = 0, 257 .sacfg_sp_ppc = 0, 258 .nsacfg_nsp_ppc = 0, 259 .int_bit_mask = 0, 260 .is_initialized = false }; 261 struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP1_DEV_S = { 262 &PPC_SSE300_MAIN_EXP1_CFG_S, 263 &PPC_SSE300_MAIN_EXP1_DATA_S }; 264 #endif 265 266 #ifdef PPC_SSE300_MAIN_EXP2_S 267 static struct ppc_sse300_dev_cfg_t PPC_SSE300_MAIN_EXP2_CFG_S = { 268 .sacfg_base = SSE300_SACFG_BASE_S, 269 .nsacfg_base = SSE300_NSACFG_BASE_NS, 270 .ppc_name = PPC_SSE300_MAIN_EXP2}; 271 static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP2_DATA_S = { 272 .sacfg_ns_ppc = 0, 273 .sacfg_sp_ppc = 0, 274 .nsacfg_nsp_ppc = 0, 275 .int_bit_mask = 0, 276 .is_initialized = false }; 277 struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP2_DEV_S = { 278 &PPC_SSE300_MAIN_EXP2_CFG_S, 279 &PPC_SSE300_MAIN_EXP2_DATA_S }; 280 #endif 281 282 #ifdef PPC_SSE300_MAIN_EXP3_S 283 static struct ppc_sse300_dev_cfg_t PPC_SSE300_MAIN_EXP3_CFG_S = { 284 .sacfg_base = SSE300_SACFG_BASE_S, 285 .nsacfg_base = SSE300_NSACFG_BASE_NS, 286 .ppc_name = PPC_SSE300_MAIN_EXP3}; 287 static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP3_DATA_S = { 288 .sacfg_ns_ppc = 0, 289 .sacfg_sp_ppc = 0, 290 .nsacfg_nsp_ppc = 0, 291 .int_bit_mask = 0, 292 .is_initialized = false }; 293 struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP3_DEV_S = { 294 &PPC_SSE300_MAIN_EXP3_CFG_S, 295 &PPC_SSE300_MAIN_EXP3_DATA_S }; 296 #endif 297 298 #ifdef PPC_SSE300_PERIPH0_S 299 static struct ppc_sse300_dev_cfg_t PPC_SSE300_PERIPH0_CFG_S = { 300 .sacfg_base = SSE300_SACFG_BASE_S, 301 .nsacfg_base = SSE300_NSACFG_BASE_NS, 302 .ppc_name = PPC_SSE300_PERIPH0}; 303 static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH0_DATA_S = { 304 .sacfg_ns_ppc = 0, 305 .sacfg_sp_ppc = 0, 306 .nsacfg_nsp_ppc = 0, 307 .int_bit_mask = 0, 308 .is_initialized = false }; 309 struct ppc_sse300_dev_t PPC_SSE300_PERIPH0_DEV_S = { 310 &PPC_SSE300_PERIPH0_CFG_S, 311 &PPC_SSE300_PERIPH0_DATA_S }; 312 #endif 313 314 #ifdef PPC_SSE300_PERIPH1_S 315 static struct ppc_sse300_dev_cfg_t PPC_SSE300_PERIPH1_CFG_S = { 316 .sacfg_base = SSE300_SACFG_BASE_S, 317 .nsacfg_base = SSE300_NSACFG_BASE_NS, 318 .ppc_name = PPC_SSE300_PERIPH1}; 319 static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH1_DATA_S = { 320 .sacfg_ns_ppc = 0, 321 .sacfg_sp_ppc = 0, 322 .nsacfg_nsp_ppc = 0, 323 .int_bit_mask = 0, 324 .is_initialized = false }; 325 struct ppc_sse300_dev_t PPC_SSE300_PERIPH1_DEV_S = { 326 &PPC_SSE300_PERIPH1_CFG_S, 327 &PPC_SSE300_PERIPH1_DATA_S }; 328 #endif 329 330 #ifdef PPC_SSE300_PERIPH_EXP0_S 331 static struct ppc_sse300_dev_cfg_t PPC_SSE300_PERIPH_EXP0_CFG_S = { 332 .sacfg_base = SSE300_SACFG_BASE_S, 333 .nsacfg_base = SSE300_NSACFG_BASE_NS, 334 .ppc_name = PPC_SSE300_PERIPH_EXP0}; 335 static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP0_DATA_S = { 336 .sacfg_ns_ppc = 0, 337 .sacfg_sp_ppc = 0, 338 .nsacfg_nsp_ppc = 0, 339 .int_bit_mask = 0, 340 .is_initialized = false }; 341 struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP0_DEV_S = { 342 &PPC_SSE300_PERIPH_EXP0_CFG_S, 343 &PPC_SSE300_PERIPH_EXP0_DATA_S }; 344 #endif 345 346 #ifdef PPC_SSE300_PERIPH_EXP1_S 347 static struct ppc_sse300_dev_cfg_t PPC_SSE300_PERIPH_EXP1_CFG_S = { 348 .sacfg_base = SSE300_SACFG_BASE_S, 349 .nsacfg_base = SSE300_NSACFG_BASE_NS, 350 .ppc_name = PPC_SSE300_PERIPH_EXP1}; 351 static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP1_DATA_S = { 352 .sacfg_ns_ppc = 0, 353 .sacfg_sp_ppc = 0, 354 .nsacfg_nsp_ppc = 0, 355 .int_bit_mask = 0, 356 .is_initialized = false }; 357 struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP1_DEV_S = { 358 &PPC_SSE300_PERIPH_EXP1_CFG_S, 359 &PPC_SSE300_PERIPH_EXP1_DATA_S }; 360 #endif 361 362 #ifdef PPC_SSE300_PERIPH_EXP2_S 363 static struct ppc_sse300_dev_cfg_t PPC_SSE300_PERIPH_EXP2_CFG_S = { 364 .sacfg_base = SSE300_SACFG_BASE_S, 365 .nsacfg_base = SSE300_NSACFG_BASE_NS, 366 .ppc_name = PPC_SSE300_PERIPH_EXP2}; 367 static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP2_DATA_S = { 368 .sacfg_ns_ppc = 0, 369 .sacfg_sp_ppc = 0, 370 .nsacfg_nsp_ppc = 0, 371 .int_bit_mask = 0, 372 .is_initialized = false }; 373 struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP2_DEV_S = { 374 &PPC_SSE300_PERIPH_EXP2_CFG_S, 375 &PPC_SSE300_PERIPH_EXP2_DATA_S }; 376 #endif 377 378 #ifdef PPC_SSE300_PERIPH_EXP3_S 379 static struct ppc_sse300_dev_cfg_t PPC_SSE300_PERIPH_EXP3_CFG_S = { 380 .sacfg_base = SSE300_SACFG_BASE_S, 381 .nsacfg_base = SSE300_NSACFG_BASE_NS, 382 .ppc_name = PPC_SSE300_PERIPH_EXP3}; 383 static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP3_DATA_S = { 384 .sacfg_ns_ppc = 0, 385 .sacfg_sp_ppc = 0, 386 .nsacfg_nsp_ppc = 0, 387 .int_bit_mask = 0, 388 .is_initialized = false }; 389 struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP3_DEV_S = { 390 &PPC_SSE300_PERIPH_EXP3_CFG_S, 391 &PPC_SSE300_PERIPH_EXP3_DATA_S }; 392 #endif 393 394 /* System counters */ 395 #ifdef SYSCOUNTER_CNTRL_ARMV8_M_S 396 397 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT > \ 398 SYSCOUNTER_ARMV8_M_SCALE_VAL_INT_MAX 399 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT is invalid. 400 #endif 401 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT > \ 402 SYSCOUNTER_ARMV8_M_SCALE_VAL_FRACT_MAX 403 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT is invalid. 404 #endif 405 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT > \ 406 SYSCOUNTER_ARMV8_M_SCALE_VAL_INT_MAX 407 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT is invalid. 408 #endif 409 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT > \ 410 SYSCOUNTER_ARMV8_M_SCALE_VAL_FRACT_MAX 411 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT is invalid. 412 #endif 413 414 static const struct syscounter_armv8_m_cntrl_dev_cfg_t 415 SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_S = { 416 .base = SYSCNTR_CNTRL_BASE_S, 417 .scale0.integer = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT, 418 .scale0.fixed_point_fraction = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT, 419 .scale1.integer = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT, 420 .scale1.fixed_point_fraction = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 421 }; 422 static struct syscounter_armv8_m_cntrl_dev_data_t 423 SYSCOUNTER_CNTRL_ARMV8_M_DEV_DATA_S = { 424 .is_initialized = false 425 }; 426 struct syscounter_armv8_m_cntrl_dev_t SYSCOUNTER_CNTRL_ARMV8_M_DEV_S = { 427 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_S), 428 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_DATA_S) 429 }; 430 #endif 431 432 #ifdef SYSCOUNTER_READ_ARMV8_M_S 433 static const struct syscounter_armv8_m_read_dev_cfg_t 434 SYSCOUNTER_READ_ARMV8_M_DEV_CFG_S = { 435 .base = SYSCNTR_READ_BASE_S, 436 }; 437 struct syscounter_armv8_m_read_dev_t SYSCOUNTER_READ_ARMV8_M_DEV_S = { 438 &(SYSCOUNTER_READ_ARMV8_M_DEV_CFG_S), 439 }; 440 #endif 441 #ifdef SYSCOUNTER_READ_ARMV8_M_NS 442 static const struct syscounter_armv8_m_read_dev_cfg_t 443 SYSCOUNTER_READ_ARMV8_M_DEV_CFG_NS = { 444 .base = SYSCNTR_READ_BASE_NS, 445 }; 446 struct syscounter_armv8_m_read_dev_t SYSCOUNTER_READ_ARMV8_M_DEV_NS = { 447 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_NS), 448 }; 449 #endif 450 451 /* System timers */ 452 #ifdef SYSTIMER0_ARMV8_M_S 453 static const struct systimer_armv8_m_dev_cfg_t SYSTIMER0_ARMV8_M_DEV_CFG_S 454 #ifdef TEST_NS_SLIH_IRQ 455 TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 456 #elif defined(TEST_NS_FLIH_IRQ) 457 TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") 458 #endif 459 = { 460 .base = SYSTIMER0_ARMV8_M_BASE_S, 461 .default_freq_hz = SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ 462 }; 463 static struct systimer_armv8_m_dev_data_t SYSTIMER0_ARMV8_M_DEV_DATA_S 464 #ifdef TEST_NS_SLIH_IRQ 465 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 466 #elif defined(TEST_NS_FLIH_IRQ) 467 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") 468 #endif 469 = { 470 .is_initialized = false 471 }; 472 struct systimer_armv8_m_dev_t SYSTIMER0_ARMV8_M_DEV_S 473 #ifdef TEST_NS_SLIH_IRQ 474 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 475 #elif defined(TEST_NS_FLIH_IRQ) 476 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") 477 #endif 478 = { 479 &(SYSTIMER0_ARMV8_M_DEV_CFG_S), 480 &(SYSTIMER0_ARMV8_M_DEV_DATA_S) 481 }; 482 #endif 483 484 #ifdef SYSTIMER0_ARMV8_M_NS 485 static const struct systimer_armv8_m_dev_cfg_t 486 SYSTIMER0_ARMV8_M_DEV_CFG_NS = { 487 .base = SYSTIMER0_ARMV8_M_BASE_NS, 488 .default_freq_hz = SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ 489 }; 490 static struct systimer_armv8_m_dev_data_t 491 SYSTIMER0_ARMV8_M_DEV_DATA_NS = { 492 .is_initialized = false 493 }; 494 struct systimer_armv8_m_dev_t SYSTIMER0_ARMV8_M_DEV_NS = { 495 &(SYSTIMER0_ARMV8_M_DEV_CFG_NS), 496 &(SYSTIMER0_ARMV8_M_DEV_DATA_NS) 497 }; 498 #endif 499 500 #ifdef SYSTIMER1_ARMV8_M_S 501 static const struct systimer_armv8_m_dev_cfg_t 502 SYSTIMER1_ARMV8_M_DEV_CFG_S = { 503 .base = SYSTIMER1_ARMV8_M_BASE_S, 504 .default_freq_hz = SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ 505 }; 506 static struct systimer_armv8_m_dev_data_t 507 SYSTIMER1_ARMV8_M_DEV_DATA_S = { 508 .is_initialized = false 509 }; 510 struct systimer_armv8_m_dev_t SYSTIMER1_ARMV8_M_DEV_S = { 511 &(SYSTIMER1_ARMV8_M_DEV_CFG_S), 512 &(SYSTIMER1_ARMV8_M_DEV_DATA_S) 513 }; 514 #endif 515 516 #ifdef SYSTIMER1_ARMV8_M_NS 517 static const struct systimer_armv8_m_dev_cfg_t 518 SYSTIMER1_ARMV8_M_DEV_CFG_NS = { 519 .base = SYSTIMER1_ARMV8_M_BASE_NS, 520 .default_freq_hz = SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ 521 }; 522 static struct systimer_armv8_m_dev_data_t 523 SYSTIMER1_ARMV8_M_DEV_DATA_NS = { 524 .is_initialized = false 525 }; 526 struct systimer_armv8_m_dev_t SYSTIMER1_ARMV8_M_DEV_NS = { 527 &(SYSTIMER1_ARMV8_M_DEV_CFG_NS), 528 &(SYSTIMER1_ARMV8_M_DEV_DATA_NS) 529 }; 530 #endif 531 532 #ifdef SYSTIMER2_ARMV8_M_S 533 static const struct systimer_armv8_m_dev_cfg_t 534 SYSTIMER2_ARMV8_M_DEV_CFG_S = { 535 .base = SYSTIMER2_ARMV8_M_BASE_S, 536 .default_freq_hz = SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ 537 }; 538 static struct systimer_armv8_m_dev_data_t 539 SYSTIMER2_ARMV8_M_DEV_DATA_S = { 540 .is_initialized = false 541 }; 542 struct systimer_armv8_m_dev_t SYSTIMER2_ARMV8_M_DEV_S = { 543 &(SYSTIMER2_ARMV8_M_DEV_CFG_S), 544 &(SYSTIMER2_ARMV8_M_DEV_DATA_S) 545 }; 546 #endif 547 548 #ifdef SYSTIMER2_ARMV8_M_NS 549 static const struct systimer_armv8_m_dev_cfg_t 550 SYSTIMER2_ARMV8_M_DEV_CFG_NS = { 551 .base = SYSTIMER2_ARMV8_M_BASE_NS, 552 .default_freq_hz = SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ 553 }; 554 static struct systimer_armv8_m_dev_data_t 555 SYSTIMER2_ARMV8_M_DEV_DATA_NS = { 556 .is_initialized = false 557 }; 558 struct systimer_armv8_m_dev_t SYSTIMER2_ARMV8_M_DEV_NS = { 559 &(SYSTIMER2_ARMV8_M_DEV_CFG_NS), 560 &(SYSTIMER2_ARMV8_M_DEV_DATA_NS) 561 }; 562 #endif 563 564 #ifdef SYSTIMER3_ARMV8_M_S 565 static const struct systimer_armv8_m_dev_cfg_t 566 SYSTIMER3_ARMV8_M_DEV_CFG_S = { 567 .base = SYSTIMER3_ARMV8_M_BASE_S, 568 .default_freq_hz = SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ 569 }; 570 static struct systimer_armv8_m_dev_data_t 571 SYSTIMER3_ARMV8_M_DEV_DATA_S = { 572 .is_initialized = false 573 }; 574 struct systimer_armv8_m_dev_t SYSTIMER3_ARMV8_M_DEV_S = { 575 &(SYSTIMER3_ARMV8_M_DEV_CFG_S), 576 &(SYSTIMER3_ARMV8_M_DEV_DATA_S) 577 }; 578 #endif 579 580 #ifdef SYSTIMER3_ARMV8_M_NS 581 static const struct systimer_armv8_m_dev_cfg_t 582 SYSTIMER3_ARMV8_M_DEV_CFG_NS = { 583 .base = SYSTIMER3_ARMV8_M_BASE_NS, 584 .default_freq_hz = SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ 585 }; 586 static struct systimer_armv8_m_dev_data_t 587 SYSTIMER3_ARMV8_M_DEV_DATA_NS = { 588 .is_initialized = false 589 }; 590 struct systimer_armv8_m_dev_t SYSTIMER3_ARMV8_M_DEV_NS = { 591 &(SYSTIMER3_ARMV8_M_DEV_CFG_NS), 592 &(SYSTIMER3_ARMV8_M_DEV_DATA_NS) 593 }; 594 #endif 595 596 /* System Watchdogs */ 597 #ifdef SYSWDOG_ARMV8_M_S 598 static const struct syswdog_armv8_m_dev_cfg_t 599 SYSWDOG_ARMV8_M_DEV_CFG_S = { 600 .base = SYSWDOG_ARMV8_M_CNTRL_BASE_S 601 }; 602 struct syswdog_armv8_m_dev_t SYSWDOG_ARMV8_M_DEV_S = { 603 &(SYSWDOG_ARMV8_M_DEV_CFG_S) 604 }; 605 #endif 606 607 #ifdef SYSWDOG_ARMV8_M_NS 608 static const struct syswdog_armv8_m_dev_cfg_t 609 SYSWDOG_ARMV8_M_DEV_CFG_NS = { 610 .base = SYSWDOG_ARMV8_M_CNTRL_BASE_NS 611 }; 612 struct syswdog_armv8_m_dev_t SYSWDOG_ARMV8_M_DEV_NS = { 613 &(SYSWDOG_ARMV8_M_DEV_CFG_NS) 614 }; 615 #endif 616 617 /* ARM MPC SSE 300 driver structures */ 618 #ifdef MPC_SRAM_S 619 static const struct mpc_sie_dev_cfg_t MPC_SRAM_DEV_CFG_S = { 620 .base = MPC_SRAM_BASE_S}; 621 static struct mpc_sie_dev_data_t MPC_SRAM_DEV_DATA_S = { 622 .range_list = 0, 623 .nbr_of_ranges = 0, 624 .is_initialized = false }; 625 struct mpc_sie_dev_t MPC_SRAM_DEV_S = { 626 &(MPC_SRAM_DEV_CFG_S), 627 &(MPC_SRAM_DEV_DATA_S)}; 628 #endif 629 630 #ifdef MPC_QSPI_S 631 static const struct mpc_sie_dev_cfg_t MPC_QSPI_DEV_CFG_S = { 632 .base = MPC_QSPI_BASE_S}; 633 static struct mpc_sie_dev_data_t MPC_QSPI_DEV_DATA_S = { 634 .range_list = 0, 635 .nbr_of_ranges = 0, 636 .is_initialized = false }; 637 struct mpc_sie_dev_t MPC_QSPI_DEV_S = { 638 &(MPC_QSPI_DEV_CFG_S), 639 &(MPC_QSPI_DEV_DATA_S)}; 640 #endif 641 642 #ifdef MPC_DDR4_S 643 static const struct mpc_sie_dev_cfg_t MPC_DDR4_DEV_CFG_S = { 644 .base = MPC_DDR4_BASE_S}; 645 static struct mpc_sie_dev_data_t MPC_DDR4_DEV_DATA_S = { 646 .range_list = 0, 647 .nbr_of_ranges = 0, 648 .is_initialized = false }; 649 struct mpc_sie_dev_t MPC_DDR4_DEV_S = { 650 &(MPC_DDR4_DEV_CFG_S), 651 &(MPC_DDR4_DEV_DATA_S)}; 652 #endif 653 654 #ifdef MPC_ISRAM0_S 655 static const struct mpc_sie_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = { 656 .base = MPC_ISRAM0_BASE_S}; 657 static struct mpc_sie_dev_data_t MPC_ISRAM0_DEV_DATA_S = { 658 .range_list = 0, 659 .nbr_of_ranges = 0, 660 .is_initialized = false }; 661 struct mpc_sie_dev_t MPC_ISRAM0_DEV_S = { 662 &(MPC_ISRAM0_DEV_CFG_S), 663 &(MPC_ISRAM0_DEV_DATA_S)}; 664 #endif 665 666 #ifdef MPC_ISRAM1_S 667 static const struct mpc_sie_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = { 668 .base = MPC_ISRAM1_BASE_S}; 669 static struct mpc_sie_dev_data_t MPC_ISRAM1_DEV_DATA_S = { 670 .range_list = 0, 671 .nbr_of_ranges = 0, 672 .is_initialized = false }; 673 struct mpc_sie_dev_t MPC_ISRAM1_DEV_S = { 674 &(MPC_ISRAM1_DEV_CFG_S), 675 &(MPC_ISRAM1_DEV_DATA_S)}; 676 #endif 677 678 #ifdef MPS3_IO_S 679 static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_S = { 680 .base = FPGA_IO_BASE_S 681 }; 682 struct arm_mps3_io_dev_t MPS3_IO_DEV_S = { 683 .cfg = &(MPS3_IO_DEV_CFG_S) 684 }; 685 #endif 686 687 #ifdef MPS3_IO_NS 688 static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_NS = { 689 .base = FPGA_IO_BASE_NS 690 }; 691 struct arm_mps3_io_dev_t MPS3_IO_DEV_NS = { 692 .cfg = &(MPS3_IO_DEV_CFG_NS) 693 }; 694 #endif 695
