1/*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 *     http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19#include "region_defs.h"
20
21/* Include file with definitions for section alignments.
22 * Note: it should be included after region_defs.h to let platform define
23 * default values if needed. */
24#include "tfm_s_linker_alignments.h"
25
26LR_CODE S_CODE_START S_CODE_SIZE {
27
28    /****  This initial section contains common code for secure binary */
29    ER_VECTORS S_CODE_START S_CODE_VECTOR_TABLE_SIZE {
30        *.o (RESET +First)
31    }
32#ifdef CONFIG_TFM_USE_TRUSTZONE
33    ER_VECTORS_FILL +0 EMPTY (S_CODE_VECTOR_TABLE_SIZE - ImageLength(ER_VECTORS)) {
34    }
35    /*
36     * Place the CMSE Veneers (containing the SG instruction) in a separate
37     * 32 bytes aligned region so that the SAU can be programmed to
38     * just set this region as Non-Secure Callable.
39     */
40    ER_VENEER +0 FIXED ALIGN TFM_LINKER_VENEERS_ALIGNMENT {
41        *(Veneer$$CMSE)
42    }
43    /*
44     * The Limit of the VENEER_ALIGN region should be at least 32 bytes aligned
45     * so that the SAU can set this region as Non-Secure Callable.
46     */
47    VENEER_ALIGN +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT EMPTY 0x0 {
48    }
49#endif
50
51    ER_TFM_CODE +0 {
52        *startup*(.text*)
53        *libplatform_s* (.text*, .rodata*)
54        *libtfm_spm* (+RO)
55    }
56
57    /**** Unprivileged Secure code start here */
58    TFM_UNPRIV_CODE +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
59        *(SFN)
60        * (+RO)
61    }
62
63    /**** Section for holding partition RO load data */
64    /*
65     * Sort the partition info by priority to guarantee the initing order.
66     * The first loaded partition will be inited at last in SFN model.
67     */
68    TFM_SP_LOAD_LIST +0 ALIGN 4 {
69        *(.part_load_priority_lowest)
70        *(.part_load_priority_low)
71        *(.part_load_priority_normal)
72        *(.part_load_priority_high)
73    }
74
75    /**** PSA RoT RO part (CODE + RODATA) start here */
76    /*
77     * This empty, zero long execution region is here to mark the start address
78     * of PSA RoT code.
79     */
80    TFM_PSA_CODE_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
81    }
82
83    TFM_PSA_ROT_LINKER +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT {
84        *tfm_psa_rot_partition* (+RO-CODE, +RO-DATA)
85        *libplatform_s* (TFM_*_PSA-ROT_ATTR_FN)
86        *.o (TFM_*_PSA-ROT_ATTR_FN)
87    }
88
89    /*
90     * This empty, zero long execution region is here to mark the end address
91     * of PSA RoT code.
92     */
93    TFM_PSA_CODE_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
94    }
95
96    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
97    /*
98     * This empty, zero long execution region is here to mark the start address
99     * of APP RoT code.
100     */
101    TFM_APP_CODE_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
102    }
103
104    TFM_APP_ROT_LINKER +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT {
105        *tfm_app_rot_partition* (+RO-CODE, +RO-DATA)
106        *libplatform_s* (TFM_*_APP-ROT_ATTR_FN)
107        *.o (TFM_*_APP-ROT_ATTR_FN)
108    }
109
110    /*
111     * This empty, zero long execution region is here to mark the end address
112     * of APP RoT code.
113     */
114    TFM_APP_CODE_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
115    }
116
117#if defined(S_CODE_SRAM_ALIAS_BASE)
118    /* eFlash driver code that gets copied from Flash to SRAM */
119    ER_CODE_SRAM S_CODE_SRAM_ALIAS_BASE ALIGN 4 {
120        Driver_GFC100_EFlash.o (.text, .text.*, .rodata, .rodata.*)
121        gfc100_eflash_drv.o (.text, .text.*, .rodata, .rodata.*)
122        musca_b1_eflash_drv.o (.text, .text.*, .rodata, .rodata.*)
123    }
124#endif
125
126    /**** Base address of secure data area */
127    TFM_SECURE_DATA_START S_DATA_START {
128    }
129
130    /*
131     * MPU on Armv6-M/v7-M core in multi-core topology may require more strict
132     * alignment that MPU region base address must align with the MPU region
133     * size.
134     * As a result, on Armv6-M/v7-M cores, to save memory resource and MPU
135     * regions, unprivileged data sections and privileged data sections are
136     * separated and gathered in unprivileged/privileged data area respectively.
137     * Keep BL2 shared data and MSP stack at the beginning of the secure data
138     * area on Armv8-M cores, while move the two areas to the beginning of
139     * privileged data region on Armv6-M/v7-M cores.
140     */
141#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \
142    defined(__ARM_ARCH_8_1M_MAIN__)
143#ifdef CODE_SHARING
144    /* The code sharing between bootloader and runtime requires to share the
145     * global variables.
146     */
147    TFM_SHARED_SYMBOLS +0 ALIGN TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT EMPTY SHARED_SYMBOL_AREA_SIZE {
148    }
149#endif
150
151    /* Shared area between BL2 and runtime to exchange data */
152    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
153    }
154
155    /* MSP */
156    ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
157    }
158
159    STACKSEAL +0 EMPTY 0x8 {
160    }
161
162#endif /* defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \
163        * defined(__ARM_ARCH_8_1M_MAIN__) */
164
165#if defined(CONFIG_TFM_PARTITION_META)
166    TFM_SP_META_PTR +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT {
167        *(.bss.SP_META_PTR_SPRTL_INST)
168    }
169#endif
170
171    /**** APP RoT DATA start here */
172    /*
173     * This empty, zero long execution region is here to mark the start address
174     * of APP RoT RW and Stack.
175     */
176    TFM_APP_RW_STACK_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
177    }
178
179    TFM_APP_ROT_LINKER_DATA +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
180        *tfm_app_rot_partition* (+RW +ZI)
181        *.o(TFM_*_APP-ROT_ATTR_RW)
182        *.o(TFM_*_APP-ROT_ATTR_ZI)
183    }
184
185    /*
186     * This empty, zero long execution region is here to mark the end address
187     * of APP RoT RW and Stack.
188     */
189    TFM_APP_RW_STACK_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
190    }
191
192#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
193    defined(__ARM_ARCH_7EM__)
194#ifdef S_DATA_PRIV_START
195    /**** Privileged data area base address specified by Armv6-M/v7-M platform */
196    TFM_SECURE_PRIV_DATA_BOUNDARY S_DATA_PRIV_START {
197    }
198#endif
199
200    /*
201     * Move BL2 shared area and MSP stack to the beginning of privileged data
202     * area on Armv6-M/v7-M platforms.
203     */
204    /* Shared area between BL2 and runtime to exchange data */
205    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
206    }
207
208    /* MSP */
209    ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE {
210    }
211#endif /* defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
212        * defined(__ARM_ARCH_7EM__) */
213
214    ER_TFM_DATA +0 {
215        * (+RW +ZI)
216    }
217
218    /**** The runtime partition placed order is same as load partition */
219    ER_PART_RT_POOL +0 ALIGN 4 {
220        *(.bss.part_runtime_priority_lowest)
221        *(.bss.part_runtime_priority_low)
222        *(.bss.part_runtime_priority_normal)
223        *(.bss.part_runtime_priority_high)
224    }
225
226    /**** The runtime service placed order is same as load partition */
227    ER_SERV_RT_POOL +0 ALIGN 4 {
228        *(.bss.serv_runtime_priority_lowest)
229        *(.bss.serv_runtime_priority_low)
230        *(.bss.serv_runtime_priority_normal)
231        *(.bss.serv_runtime_priority_high)
232    }
233
234    /**** PSA RoT DATA start here */
235    /*
236     * This empty, zero long execution region is here to mark the start address
237     * of PSA RoT RW and Stack.
238     */
239    TFM_PSA_RW_STACK_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
240    }
241
242    TFM_PSA_ROT_LINKER_DATA +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
243        *tfm_psa_rot_partition* (+RW +ZI)
244        *.o(TFM_*_PSA-ROT_ATTR_RW)
245        *.o(TFM_*_PSA-ROT_ATTR_ZI)
246    }
247
248    /*
249     * This empty, zero long execution region is here to mark the end address
250     * of PSA RoT RW and Stack.
251     */
252    TFM_PSA_RW_STACK_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
253    }
254
255#ifdef RAM_VECTORS_SUPPORT
256    ER_RAM_VECTORS +0 ALIGN TFM_LINKER_RAM_VECTORS_ALIGNMENT UNINIT {
257        * (RESET_RAM)
258    }
259#endif
260
261#if defined (S_RAM_CODE_START)
262    /* Executable code allocated in RAM */
263    TFM_RAM_CODE S_RAM_CODE_START {
264        * (.ramfunc)
265    }
266#endif
267
268    /* This empty, zero long execution region is here to mark the limit address
269     * of the last execution region that is allocated in SRAM.
270     */
271    SRAM_WATERMARK +0 EMPTY 0x0 {
272    }
273
274    /* Make sure that the sections allocated in the SRAM does not exceed the
275     * size of the SRAM available.
276     */
277    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
278}
279
280LR_NS_PARTITION NS_PARTITION_START {
281    /* Reserved place for NS application.
282     * No code will be placed here, just address of this region is used in the
283     * secure code to configure certain HW components. This generates an empty
284     * execution region description warning during linking.
285     */
286    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
287    }
288}
289
290#ifdef BL2
291LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
292    /* Reserved place for new image in case of firmware upgrade.
293     * No code will be placed here, just address of this region is used in the
294     * secure code to configure certain HW components. This generates an empty
295     * execution region description warning during linking.
296     */
297    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
298        UNINIT SECONDARY_PARTITION_SIZE {
299    }
300}
301#endif /* BL2 */
302