1 /*
2  * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef  CC_PLAT_H
8 #define  CC_PLAT_H
9 
10 #define NULL_SRAM_ADDR ((CCSramAddr_t)0xFFFFFFFF)
11 
12 #define _WriteWordsToSram(addr, data, size) \
13 do { \
14     uint32_t ii; \
15     volatile uint32_t dummy; \
16     CC_HAL_WRITE_REGISTER( CC_REG_OFFSET (HOST_RGF,SRAM_ADDR), (addr)); \
17     for( ii = 0 ; ii < size/sizeof(uint32_t) ; ii++ ) { \
18            CC_HAL_WRITE_REGISTER( CC_REG_OFFSET (HOST_RGF,SRAM_DATA), SWAP_TO_LE(((uint32_t *)data)[ii])); \
19            do { \
20              dummy = CC_HAL_READ_REGISTER( CC_REG_OFFSET (HOST_RGF, SRAM_DATA_READY)); \
21            }while(!(dummy & 0x1)); \
22     } \
23 }while(0)
24 
25 #define _ReadWordsFromSram( addr , data , size ) \
26 do { \
27     uint32_t ii; \
28     volatile uint32_t dummy; \
29     CC_HAL_WRITE_REGISTER( CC_REG_OFFSET (HOST_RGF,SRAM_ADDR) ,(addr) ); \
30     dummy = CC_HAL_READ_REGISTER( CC_REG_OFFSET (HOST_RGF,SRAM_DATA)); \
31     for( ii = 0 ; ii < size/sizeof(uint32_t) ; ii++ ) { \
32         do { \
33             dummy = CC_HAL_READ_REGISTER( CC_REG_OFFSET (HOST_RGF, SRAM_DATA_READY)); \
34         }while(!(dummy & 0x1)); \
35         dummy = CC_HAL_READ_REGISTER( CC_REG_OFFSET (HOST_RGF,SRAM_DATA));\
36         ((uint32_t*)data)[ii] = SWAP_TO_LE(dummy); \
37     } \
38     do { \
39         dummy = CC_HAL_READ_REGISTER( CC_REG_OFFSET (HOST_RGF, SRAM_DATA_READY)); \
40     }while(!(dummy & 0x1)); \
41 }while(0)
42 
43 #define CLEAR_TRNG_SRC()
44 
45 #endif
46