1####################################### 2Trusted Firmware-M Generic Threat Model 3####################################### 4 5************ 6Introduction 7************ 8 9This document introduces a generic threat model of Trusted Firmware-M (TF-M). 10This generic threat model provides an overall analysis of TF-M implementation 11and identifies general threats and mitigation. 12 13There is also a dedicated document for physical attacks mitigations which can be found 14:doc:`here </technical_references/design_docs/tfm_physical_attack_mitigation>`. 15 16.. note:: 17 18 If you think a security vulnerability is found, please follow 19 Trustedfirmware.org [Security-Incident-Process]_ to contact TF-M security 20 team. 21 22Scope 23===== 24 25TF-M supports diverse models and topologies. It also implements multiple 26isolation levels. Each case may focus on different target of evaluation (TOE) 27and identify different assets and threats. 28TF-M implementation consists of several secure services, defined as 29Root of Trust (RoT) service. Those RoT services belong to diverse RoT 30(Application RoT or PSA RoT) and access different assets and hardware. Therefore 31each RoT service may require a dedicated threat model. 32 33The analysis on specific models, topologies or RoT services may be covered in 34dedicated threat model documents. Those threat models are out of the scope of 35this document. 36 37Methodology 38=========== 39 40The threat modeling in this document follows the process listed below to 41build up the threat model. 42 43- Target of Evaluation (TOE) 44- Assets identification 45- Data Flow Diagram (DFD) 46- Threats Prioritization 47- Threats identification 48 49TOE is the entity on which threat modeling is performed. The logic behind this 50process is to firstly investigate the TOE which could be a system, solution or 51use case. This first step helps to identify the assets to be protected in TOE. 52 53According to TOE and assets, Trust Boundaries can be determined. The Data Flow 54Diagram (DFD) across Trust Boundaries is then defined to help identify the 55threats. 56 57Those threats should be prioritized based on a specific group of principals and 58metrics. The principals and metrics should also be specified. 59 60******************** 61Target of Evaluation 62******************** 63 64A typical TF-M system diagram from a high-level overview is shown below. TF-M is 65running in the Secure Processing Environment (SPE) and NS software is running in 66Non-secure Processing Environment (NSPE). For more details, please refer to 67Platform Security Architecture Firmware Framework for M (FF-M) [FF-M]_ and 68FF-M 1.1 Extensions [FF-M 1.1 Extensions]_. 69 70.. figure:: TF-M-block-diagram.png 71 72The TOE in this general model is the SPE, including TF-M and other components 73running in SPE. 74 75The TOE can vary in different TF-M models, RoT services and usage scenarios. 76Refer to dedicated threat models for the specific TOE definitions. 77 78******************** 79Asset identification 80******************** 81 82In this threat model, assets include the general items listed below: 83 84- Hardware Root of Trust data, e.g. 85 86 - Hardware Unique Key (HUK) 87 - Root authentication key 88 - Other embedded root keys 89 90- Software RoT data, e.g. 91 92 - Secure Partition Manager (SPM) code and data 93 - Secure partition code and data 94 - NSPE data stored in SPE 95 - Data generated in SPE as requested by NSPE 96 97- Availability of entire RoT service 98 99- Secure logs, including event logs 100 101Assets may vary in different use cases and implementations. Additional assets 102can be defined in an actual usage scenario and a dedicated threat model. 103 104For example, in a network camera use case, the following data can be defined as 105assets too: 106 107- Certificate for connecting to cloud 108- Session keys for encryption/decryption in the communication with cloud 109- Keys to encrypt/decrypt the videos and photos 110 111***************** 112Data Flow Diagram 113***************** 114 115The Trust Boundary isolates SPE from NSPE, according to the TOE definition in 116`Target of Evaluation`_. The Trust Boundary mapped to block diagram is shown 117in the figure below. Other modules inside SPE stay in the same TOE as TF-M does. 118 119Valid Data flows across the Trust Boundary are also shown in the figure below. 120This threat model only focuses on the data flows related to TF-M. 121 122.. figure:: overall-DFD.png 123 124More details of data flows are listed below. 125 126.. _data-flow-table: 127 128.. table:: TF-M Data Flows between NSPE and SPE 129 130 +-----------+----------------------------------------------------------------+ 131 | Data flow | Description | 132 +===========+================================================================+ 133 | ``DF1`` | TF-M initializes NS entry and activates NSPE. | 134 | | | 135 | | - On single Armv8-M core platforms, TF-M will hand over the | 136 | | control to Non-secure state. | 137 | | - On dual-cpu platforms, Secure core starts NS core booting. | 138 +-----------+----------------------------------------------------------------+ 139 | ``DF2`` | NSPE requests TF-M RoT services. | 140 | | | 141 | | NSPE requests RoT services via PSA Client APIs defined in | 142 | | [FF-M]_. | 143 | | | 144 | | In single Armv8-M core scenarios, SG instruction is executed | 145 | | in Non-secure Callable region to trigger a transition from | 146 | | Non-secure state to Secure state. | 147 | | | 148 | | On dual-cpu platforms, non-secure core sends PSA Client calls | 149 | | to secure core via mailbox. | 150 +-----------+----------------------------------------------------------------+ 151 | ``DF3`` | Secure Partitions fetch input data from NS and write back | 152 | | output data to NS. | 153 | | | 154 | | As required in [FF-M]_, Secure Partitions should not directly | 155 | | access NSPE memory. Instead, RoT services relies on TF-M SPM | 156 | | to access NSPE memory. | 157 +-----------+----------------------------------------------------------------+ 158 | ``DF4`` | TF-M returns RoT service results to NSPE after NS request to | 159 | | RoT service is completed. | 160 | | | 161 | | In single Armv8-M core scenarios, it also trigger a transition | 162 | | from Secure state back to Non-secure state. | 163 | | | 164 | | On dual-cpu platforms, secure core returns the result to | 165 | | non-secure core via mailbox. | 166 +-----------+----------------------------------------------------------------+ 167 | ``DF5`` | Non-secure interrupts preempt SPE execution in single Armv8-M | 168 | | core scenarios. | 169 +-----------+----------------------------------------------------------------+ 170 | ``DF6`` | Secure interrupts preempt NSPE execution in single Armv8-M | 171 | | core scenarios. | 172 +-----------+----------------------------------------------------------------+ 173 174.. note:: 175 176 All the other data flows across the Trusted Boundary besides the valid ones 177 mentioned above should be prohibited by default. 178 Proper isolation must be configured to prevent NSPE directly accessing SPE. 179 180 Threats irrelevant to data flows in 181 :ref:`TF-M Data Flows between NSPE and SPE <data-flow-table>` may be specified 182 in `Miscellaneous threats`_. 183 184Data flows inside SPE (informative) 185=================================== 186 187Since all the SPE components stay in the TOE within the same Trust Boundary in 188this threat model, the data flows between SPE components are not covered in this 189threat model. Instead, those data flows and corresponding threats will be 190identified in the dedicated threat model documents of TF-M RoT services and 191usage scenarios. 192 193Those data flows inside SPE include following examples: 194 195- Data flows between TF-M and BL2 196- Data flows between RoT services and SPM 197- Data flows between RoT services and corresponding secure hardware and assets, 198 such as secure storage device, crypto hardware accelerator and Hardware Unique 199 Key (HUK). 200 201********************* 202Threat identification 203********************* 204 205Threat priority 206=============== 207 208Threat priority is indicated by the score calculated via Common Vulnerability 209Scoring System (CVSS) Version 3.1 [CVSS]_. The higher the threat scores, the 210greater severity the threat is with and the higher the priority is. 211 212CVSS scores can be mapped to qualitative severity ratings defined in CVSS 3.1 213specification [CVSS_SPEC]_. This threat model follows the same mapping between 214CVSS scores and threat priority rating. 215 216As a generic threat model, this document focuses on *Base Score* which reflects 217the constant and general severity of a threat according to its intrinsic 218characteristics. 219 220The *Impacted Component* defined in [CVSS_SPEC]_ refers to the assets listed in 221`Asset identification`_. 222 223Threats and mitigation list 224=========================== 225 226This section lists generic threats and corresponding mitigation, based on the 227the analysis of data flows in `Data Flow Diagram`_. 228 229Threats are identified following ``STRIDE`` model. Please refer to [STRIDE]_ for 230more details. 231 232The field ``CVSS Score`` reflects the threat priority defined in 233`Threat priority`_. The field ``CVSS Vector String`` contains the textual 234representation of the CVSS metric values used to score the threat. Refer to 235[CVSS_SPEC]_ for more details of CVSS vector string. 236 237.. note:: 238 239 A generic threat may have different behaviors and therefore require different 240 mitigation, in diverse TF-M models and usage scenarios. 241 242 This threat model document focuses on general analysis of the following 243 threats. For the details in a specific configuration and usage scenario, 244 please refer to the dedicated threat model document. 245 246NS entry initialization 247----------------------- 248 249This section identifies threats on ``DF1`` defined in `Data Flow Diagram`_. 250 251.. table:: TFM-GENERIC-NS-INIT-T-1 252 :widths: 10 50 253 254 +---------------+------------------------------------------------------------+ 255 | Index | **TFM-GENERIC-NS-INIT-T-1** | 256 +---------------+------------------------------------------------------------+ 257 | Description | The NS image can be tampered by an attacker | 258 +---------------+------------------------------------------------------------+ 259 | Justification | An attack may tamper the NS image to inject malicious code | 260 +---------------+------------------------------------------------------------+ 261 | Category | Tampering | 262 +---------------+------------------------------------------------------------+ 263 | Mitigation | By default TF-M relies on MCUBoot to validate NS image. | 264 | | The validation of NS image integrity and authenticity is | 265 | | completed in secure boot before jumping to NS entry or | 266 | | booting up NS core. | 267 | | Refer to [SECURE-BOOT]_ for more details. | 268 | | | 269 | | The validation may vary in diverse vendor platforms | 270 | | specific Chain of Trust (CoT) implementation. | 271 +---------------+------------------------------------------------------------+ 272 | CVSS Score | 3.5 (Low) | 273 +---------------+------------------------------------------------------------+ 274 | CVSS Vector | CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:N | 275 | String | | 276 +---------------+------------------------------------------------------------+ 277 278.. table:: TFM-GENERIC-NS-INIT-T-2 279 :widths: 10 50 280 281 +---------------+------------------------------------------------------------+ 282 | Index | **TFM-GENERIC-NS-INIT-T-2** | 283 +---------------+------------------------------------------------------------+ 284 | Description | An attacker may replace the current NS image with an older | 285 | | version. | 286 +---------------+------------------------------------------------------------+ 287 | Justification | The attacker downgrades the NS image with an older version | 288 | | which has been deprecated due to known security issues. | 289 | | | 290 | | The older version image can pass the image signature | 291 | | validation and its vulnerabilities can be exploited by | 292 | | attackers. | 293 +---------------+------------------------------------------------------------+ 294 | Category | Tampering | 295 +---------------+------------------------------------------------------------+ 296 | Mitigation | TF-M relies on MCUBoot to perform anti-rollback | 297 | | protection. | 298 | | | 299 | | TF-M defines a non-volatile counter API to support | 300 | | anti-rollback. Each platform must implement it using | 301 | | specific trusted hardware non-volatile counters. | 302 | | For more details, refer to [ROLLBACK-PROTECT]_. | 303 | | | 304 | | The anti-rollback protection implementation can vary on | 305 | | diverse platforms. | 306 +---------------+------------------------------------------------------------+ 307 | CVSS Score | 3.5 (Low) | 308 +---------------+------------------------------------------------------------+ 309 | CVSS Vector | CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:N | 310 | String | | 311 +---------------+------------------------------------------------------------+ 312 313.. table:: TFM-GENERIC-NS-INIT-T-I-1 314 :widths: 10 50 315 316 +---------------+------------------------------------------------------------+ 317 | Index | **TFM-GENERIC-NS-INIT-T-I-1** | 318 +---------------+------------------------------------------------------------+ 319 | Description | If SPE doesn't complete isolation configuration before | 320 | | NSPE starts, NSPE can access secure regions which it is | 321 | | disallowed to. | 322 +---------------+------------------------------------------------------------+ 323 | Justification | Secure data can be tampered or disclosed if NSPE is | 324 | | activated and accesses secure regions before isolation | 325 | | configuration is completed by SPE. | 326 +---------------+------------------------------------------------------------+ 327 | Category | Tampering/Information disclosure | 328 +---------------+------------------------------------------------------------+ 329 | Mitigation | SPE must complete and enable proper isolation to protect | 330 | | secure regions from being accessed by NSPE, before jumping | 331 | | to NS entry or booting up NS core. | 332 | | | 333 | | TF-M executes isolation configuration at early stage of | 334 | | secure initialization before NS initialization starts. | 335 | | | 336 | | On dual-cpu platform, platform specific initialization | 337 | | must halt NS core until isolation is completed, as defined | 338 | | in [DUAL-CPU-BOOT]_. | 339 | | | 340 | | TF-M defines isolation configuration HALs for platform | 341 | | implementation. The specific isolation configuration | 342 | | depends on platform specific implementation. | 343 +---------------+------------------------------------------------------------+ 344 | CVSS Score | 9.0 (Critical) | 345 +---------------+------------------------------------------------------------+ 346 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N | 347 | String | | 348 +---------------+------------------------------------------------------------+ 349 350.. table:: TFM-GENERIC-NS-INIT-T-I-2 351 :widths: 10 50 352 353 +---------------+------------------------------------------------------------+ 354 | Index | **TFM-GENERIC-NS-INIT-T-I-2** | 355 +---------------+------------------------------------------------------------+ 356 | Description | If SPE doesn't complete isolation configuration before | 357 | | NSPE starts, NSPE can control devices or peripherals which | 358 | | it is disallowed to. | 359 +---------------+------------------------------------------------------------+ 360 | Justification | On some platforms, devices and peripherals can be | 361 | | configured as Secure state in runtime. If security status | 362 | | configuration of those device and peripherals are not | 363 | | properly completed before NSPE starts, NSPE can control | 364 | | those device and peripherals and may be able to tamper | 365 | | data or access secure data. | 366 +---------------+------------------------------------------------------------+ 367 | Category | Tampering/Information disclosure | 368 +---------------+------------------------------------------------------------+ 369 | Mitigation | SPE must complete and enable proper configuration and | 370 | | isolation to protect critical devices and peripherals from | 371 | | being accessed by NSPE, before jumping to NS entry or | 372 | | booting up NS core. | 373 | | | 374 | | TF-M executes isolation configuration of devices and | 375 | | peripherals at early stage of secure initialization before | 376 | | NS initialization starts. | 377 | | | 378 | | The specific isolation configuration depends on platform | 379 | | specific implementation. | 380 +---------------+------------------------------------------------------------+ 381 | CVSS Score | 9.0 (Critical) | 382 +---------------+------------------------------------------------------------+ 383 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N | 384 | String | | 385 +---------------+------------------------------------------------------------+ 386 387.. table:: TFM-GENERIC-NS-INIT-I-2 388 :widths: 10 50 389 390 +---------------+------------------------------------------------------------+ 391 | Index | **TFM-GENERIC-NS-INIT-I-2** | 392 +---------------+------------------------------------------------------------+ 393 | Description | If SPE leaves some SPE information in non-secure memory | 394 | | or shared registers when NSPE starts, NSPE may access | 395 | | those SPE information. | 396 +---------------+------------------------------------------------------------+ 397 | Justification | If NSPE can access those SPE information from shared | 398 | | registers or non-secure memory, secure information may be | 399 | | disclosed. | 400 +---------------+------------------------------------------------------------+ 401 | Category | Information disclosure | 402 +---------------+------------------------------------------------------------+ 403 | Mitigation | SPE must clean up the secure information from shared | 404 | | registers before NS starts. | 405 | | | 406 | | TF-M invalidates registers not banked before handing over | 407 | | the system to NSPE on single Armv8-M platform. | 408 | | | 409 | | On dual-cpu platforms, shared registers are implementation | 410 | | defined, such as Inter-Processor Communication registers. | 411 | | Dual-cpu platforms must not store any data which may | 412 | | disclose secure information in the shared registers. | 413 | | | 414 | | SPE must avoid storing SPE information in non-secure | 415 | | memory. | 416 +---------------+------------------------------------------------------------+ 417 | CVSS Score | 4.3 (Medium) | 418 +---------------+------------------------------------------------------------+ 419 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N | 420 | String | | 421 +---------------+------------------------------------------------------------+ 422 423.. table:: TFM-GENERIC-NS-INIT-D-1 424 :widths: 10 50 425 426 +---------------+------------------------------------------------------------+ 427 | Index | **TFM-GENERIC-NS-INIT-D-1** | 428 +---------------+------------------------------------------------------------+ 429 | Description | An attacker may block NS to boot up | 430 +---------------+------------------------------------------------------------+ 431 | Justification | An attacker may block NS to boot up, such as by corrupting | 432 | | NS image, to stop the whole system from performing normal | 433 | | functionalities. | 434 +---------------+------------------------------------------------------------+ 435 | Category | Denial of service | 436 +---------------+------------------------------------------------------------+ 437 | Mitigation | No SPE information will be disclosed and TF-M won't be | 438 | | directly impacted. | 439 | | | 440 | | It relies on NSPE and platform specific implementation to | 441 | | mitigate this threat. It is out of scope of this threat | 442 | | model. | 443 +---------------+------------------------------------------------------------+ 444 | CVSS Score | 4.0 (Medium) | 445 +---------------+------------------------------------------------------------+ 446 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L | 447 | String | | 448 +---------------+------------------------------------------------------------+ 449 450NSPE requests TF-M secure service 451--------------------------------- 452 453This section identifies threats on ``DF2`` defined in `Data Flow Diagram`_. 454 455.. table:: TFM-GENERIC-REQUEST-SERVICE-S-1 456 :widths: 10 50 457 458 +---------------+------------------------------------------------------------+ 459 | Index | **TFM-GENERIC-REQUEST-SERVICE-S-1** | 460 +---------------+------------------------------------------------------------+ 461 | Description | A malicious NS application may pretend as a secure client | 462 | | to access secure data which NSPE must not directly access. | 463 +---------------+------------------------------------------------------------+ 464 | Justification | [FF-M]_ defines ``Client ID`` to distinguish clients which | 465 | | request RoT services. Secure clients are assigned with | 466 | | positive IDs and non-secure clients are assigned with | 467 | | negative ones. | 468 | | | 469 | | A malicious NS application may provide a positive | 470 | | ``Client ID`` to pretend as a secure client to access | 471 | | secure data. | 472 +---------------+------------------------------------------------------------+ 473 | Category | Spoofing | 474 +---------------+------------------------------------------------------------+ 475 | Mitigation | TF-M checks the ``Client ID`` from NSPE. If the NS | 476 | | ``Client ID`` is not a valid one, TF-M will report this as | 477 | | a security error. | 478 +---------------+------------------------------------------------------------+ 479 | CVSS Score | 8.4 (High) | 480 +---------------+------------------------------------------------------------+ 481 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:N | 482 | String | | 483 +---------------+------------------------------------------------------------+ 484 485.. table:: TFM-GENERIC-REQUEST-SERVICE-T-1 486 :widths: 10 50 487 488 +---------------+------------------------------------------------------------+ 489 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-1** | 490 +---------------+------------------------------------------------------------+ 491 | Description | An attacker in NSPE may tamper the service request input | 492 | | or output vectors between check and use | 493 | | (Time-Of-Check-to-Time-Of-Use (TOCTOU)). | 494 +---------------+------------------------------------------------------------+ 495 | Justification | If SPE validates the content in input/output vectors | 496 | | locally in NSPE memory, an attacker in NSPE can have a | 497 | | chance to tamper the content after the validation | 498 | | successfully passes. Then SPE will provide RoT service | 499 | | according to the corrupted parameters and it may cause | 500 | | further security issues. | 501 +---------------+------------------------------------------------------------+ 502 | Category | Tampering | 503 +---------------+------------------------------------------------------------+ 504 | Mitigation | In TF-M implementation, the validation of NS input/output | 505 | | vectors are only executed after those vectors are copied | 506 | | from NSPE into SPE. It prevents an attack from NSPE to | 507 | | tamper those parameters after validation in TF-M. | 508 +---------------+------------------------------------------------------------+ 509 | CVSS Score | 7.8 (High) | 510 +---------------+------------------------------------------------------------+ 511 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:H/I:H/A:N | 512 | String | | 513 +---------------+------------------------------------------------------------+ 514 515.. table:: TFM-GENERIC-REQUEST-SERVICE-T-2 516 :widths: 10 50 517 518 +---------------+------------------------------------------------------------+ 519 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-2** | 520 +---------------+------------------------------------------------------------+ 521 | Description | A malicious NS application may request to tamper data | 522 | | belonging to SPE. | 523 +---------------+------------------------------------------------------------+ 524 | Justification | A malicious NS application may request SPE RoT services to | 525 | | write malicious value to SPE data. The malicious NS | 526 | | application may try to tamper SPE assets, such as keys, or | 527 | | modify configurations in SPE. The SPE data belongs to | 528 | | components in SPE and must not be accessed by NSPE. | 529 +---------------+------------------------------------------------------------+ 530 | Category | Tampering | 531 +---------------+------------------------------------------------------------+ 532 | Mitigation | TF-M executes memory access check to all the RoT service | 533 | | requests. If a request doesn't have enough permission to | 534 | | access the target memory region, TF-M will refuse this | 535 | | request and assert a security error. | 536 +---------------+------------------------------------------------------------+ 537 | CVSS Score | 7.1 (High) | 538 +---------------+------------------------------------------------------------+ 539 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:H/A:N | 540 | String | | 541 +---------------+------------------------------------------------------------+ 542 543.. table:: TFM-GENERIC-REQUEST-SERVICE-R-1 544 :widths: 10 50 545 546 +---------------+------------------------------------------------------------+ 547 | Index | **TFM-GENERIC-REQUEST-SERVICE-R-1** | 548 +---------------+------------------------------------------------------------+ 549 | Description | A NS application may repudiate that it has requested | 550 | | services from a RoT service. | 551 +---------------+------------------------------------------------------------+ 552 | Justification | A malicious NS application may call a RoT service to | 553 | | access critical data in SPE, which it is disallowed to, | 554 | | via a non-public vulnerability. It may refuse to admit | 555 | | that it has accessed that data. | 556 +---------------+------------------------------------------------------------+ 557 | Category | Repudiation | 558 +---------------+------------------------------------------------------------+ 559 | Mitigation | TF-M implements an event logging secure service to record | 560 | | the critical events, such as the access to critical data. | 561 +---------------+------------------------------------------------------------+ 562 | CVSS Score | 0.0 (None) | 563 +---------------+------------------------------------------------------------+ 564 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:N/A:N | 565 | String | | 566 +---------------+------------------------------------------------------------+ 567 568.. table:: TFM-GENERIC-REQUEST-SERVICE-I-1 569 :widths: 10 50 570 571 +---------------+------------------------------------------------------------+ 572 | Index | **TFM-GENERIC-REQUEST-SERVICE-I-1** | 573 +---------------+------------------------------------------------------------+ 574 | Description | A malicious NS application may request to read data | 575 | | belonging to SPE. | 576 +---------------+------------------------------------------------------------+ 577 | Justification | A malicious NS application may request SPE RoT services to | 578 | | copy SPE data to NS memory. The SPE data belongs to | 579 | | components in SPE and must not be disclosed to NSPE, such | 580 | | as root keys. | 581 +---------------+------------------------------------------------------------+ 582 | Category | Information disclosure | 583 +---------------+------------------------------------------------------------+ 584 | Mitigation | TF-M executes memory access check to all the RoT service | 585 | | requests. If a request doesn't have enough permission to | 586 | | access the target memory region, TF-M will refuse this | 587 | | request and assert a security error. | 588 +---------------+------------------------------------------------------------+ 589 | CVSS Score | 7.1 (High) | 590 +---------------+------------------------------------------------------------+ 591 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:N/A:N | 592 | String | | 593 +---------------+------------------------------------------------------------+ 594 595.. table:: TFM-GENERIC-REQUEST-SERVICE-T-I-1 596 :widths: 10 50 597 598 +---------------+------------------------------------------------------------+ 599 | Index | **TFM-GENERIC-REQUEST-SERVICE-T-I-1** | 600 +---------------+------------------------------------------------------------+ 601 | Description | A malicious NS application may request to control secure | 602 | | device and peripherals, on which it doesn't have the | 603 | | permission. | 604 +---------------+------------------------------------------------------------+ 605 | Justification | A malicious NS application may request RoT services to | 606 | | control secure device and peripherals, on which it doesn't | 607 | | have the permission. | 608 +---------------+------------------------------------------------------------+ 609 | Category | Tampering/Information disclose | 610 +---------------+------------------------------------------------------------+ 611 | Mitigation | TF-M performs client check to validate whether the client | 612 | | has the permission to access the secure device and | 613 | | peripherals. | 614 +---------------+------------------------------------------------------------+ 615 | CVSS Score | 9.0 (Critical) | 616 +---------------+------------------------------------------------------------+ 617 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:N | 618 | String | | 619 +---------------+------------------------------------------------------------+ 620 621.. table:: TFM-GENERIC-REQUEST-SERVICE-D-1 622 :widths: 10 50 623 624 +---------------+------------------------------------------------------------+ 625 | Index | **TFM-GENERIC-REQUEST-SERVICE-D-1** | 626 +---------------+------------------------------------------------------------+ 627 | Description | A Malicious NS applications may frequently call secure | 628 | | services to block secure service requests from other NS | 629 | | applications. | 630 +---------------+------------------------------------------------------------+ 631 | Justification | TF-M runs on IoT devices with constrained resource. Even | 632 | | though multiple outstanding NS PSA Client calls can be | 633 | | supported in system, the number of NS PSA client calls | 634 | | served by TF-M simultaneously are still limited. | 635 | | | 636 | | Therefore, if a malicious NS application or multiple | 637 | | malicious NS applications continue calling TF-M secure | 638 | | services frequently, it may block other NS applications to | 639 | | request secure service from TF-M. | 640 +---------------+------------------------------------------------------------+ 641 | Category | Denial of service | 642 +---------------+------------------------------------------------------------+ 643 | Mitigation | TF-M is unable to manage behavior of NS applications. | 644 | | Assets are not disclosed and TF-M is neither directly | 645 | | impacted in this threat. | 646 | | | 647 | | It relies on NS OS to enhance scheduling policy and | 648 | | prevent a single NS application to occupy entire CPU time. | 649 | | It is beyond the scope of this threat model. | 650 +---------------+------------------------------------------------------------+ 651 | CVSS Score | 4.0 (Medium) | 652 +---------------+------------------------------------------------------------+ 653 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L | 654 | String | | 655 +---------------+------------------------------------------------------------+ 656 657.. table:: TFM-GENERIC-REQUEST-SERVICE-D-2 658 :widths: 10 50 659 660 +---------------+------------------------------------------------------------+ 661 | Index | **TFM-GENERIC-REQUEST-SERVICE-D-2** | 662 +---------------+------------------------------------------------------------+ 663 | Description | A malicious NS application may provide invalid NS memory | 664 | | addresses as the addresses of input and output data in RoT | 665 | | service requests. | 666 +---------------+------------------------------------------------------------+ 667 | Justification | SPE may be unable to achieve full knowledge of NS memory | 668 | | mapping. SPE may fail to capture those invalid NS memory | 669 | | addresses during memory access check since those invalid | 670 | | addresses may not be included in isolation configuration. | 671 | | | 672 | | In that case, SPE will access those invalid NS memory | 673 | | addresses later to read or write data. It may trigger a | 674 | | system error to crash the whole system immediately. | 675 | | | 676 | | The malicious NS application may be blocked by NS MPU from | 677 | | directly accessing that invalid NS memory address. But it | 678 | | may manipulate SPE to access that address instead. | 679 +---------------+------------------------------------------------------------+ 680 | Category | Denial of service | 681 +---------------+------------------------------------------------------------+ 682 | Mitigation | TF-M executes memory access check to the memory addresses | 683 | | in all the NS requests. | 684 | | | 685 | | On single Armv8-M core platforms, TF-M invokes ``TT`` | 686 | | instructions to execute memory address check. If a NS | 687 | | memory area is not matched in any valid SAU or MPU region, | 688 | | it will be marked as invalid and any access permission is | 689 | | disallowed. Therefore, SPM will reject any NS request | 690 | | containing invalid NS memory addresses and reports it as | 691 | | as a security error. | 692 | | | 693 | | On dual-core platforms, TF-M implements a default memory | 694 | | access check. If a NS memory area is not found in any | 695 | | memory region configured for isolation, it will be marked | 696 | | as invalid and therefore SPM will reject the corresponding | 697 | | NS request. It will be reported as a security error. | 698 | | | 699 | | Dual-core platforms may implement platform specific memory | 700 | | check to replace the default one. It relies on platform | 701 | | specific implementation to capture invalid memory address. | 702 | | It is out of the scope of this document. | 703 +---------------+------------------------------------------------------------+ 704 | CVSS Score | 3.2 (Low) | 705 +---------------+------------------------------------------------------------+ 706 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:N/A:L | 707 | String | | 708 +---------------+------------------------------------------------------------+ 709 710RoT services read and write NS data 711----------------------------------- 712 713This section identifies threats on ``DF3`` defined in `Data Flow Diagram`_. 714 715RoT services can either directly access NS memory or rely on TF-M SPM to obtain NS input data and 716send response data back to NS memory. 717 718.. _TFM-GENERIC-SECURE-SERVICE-RW-T-1: 719 720.. table:: TFM-GENERIC-SECURE-SERVICE-RW-T-1 721 :widths: 10 50 722 723 +---------------+------------------------------------------------------------+ 724 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-T-1** | 725 +---------------+------------------------------------------------------------+ 726 | Description | An attacker may tamper NS input data while the RoT service | 727 | | is processing those data. | 728 +---------------+------------------------------------------------------------+ 729 | Justification | A RoT service may access NS input data multiple times | 730 | | during its data processing. For example, it may validate | 731 | | or authenticate the NS input data before it performs | 732 | | further processing. | 733 | | | 734 | | If the NS input data remains in NSPE memory during the RoT | 735 | | service execution, an attacker may tamper the NS input | 736 | | data in NSPE memory after the validation passes. | 737 +---------------+------------------------------------------------------------+ 738 | Category | Tampering | 739 +---------------+------------------------------------------------------------+ 740 | Mitigation | If RoT services request SPM to read and write NS data. | 741 | | TF-M SPM follows [FF-M]_ to copy the NS input data into | 742 | | SPE memory region owned by the RoT service, before the RoT | 743 | | service processes the data. | 744 | | Therefore, the NS input data is protected during the RoT | 745 | | service execution from being tampered. | 746 | | | 747 | | If RoT services can directly access NS memory and read NS | 748 | | input data multiple times during data processing, it is | 749 | | required to review and confirm the implementation of the | 750 | | RoT service copies NS input data into SPE memory area | 751 | | before it processes the data. | 752 +---------------+------------------------------------------------------------+ 753 | CVSS Score | 3.2 (Low) | 754 +---------------+------------------------------------------------------------+ 755 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:L/A:N | 756 | String | | 757 +---------------+------------------------------------------------------------+ 758 759.. _TFM-GENERIC-SECURE-SERVICE-RW-T-2: 760 761.. table:: TFM-GENERIC-SECURE-SERVICE-RW-T-2 762 :widths: 10 50 763 764 +---------------+------------------------------------------------------------+ 765 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-T-2** | 766 +---------------+------------------------------------------------------------+ 767 | Description | A malicious NS application may embed secure memory | 768 | | addresses into a structure in RoT service request input | 769 | | vectors, to tamper secure memory which the NS application | 770 | | must not access. | 771 +---------------+------------------------------------------------------------+ 772 | Justification | [FF-M]_ limits the total number of input/output vectors to | 773 | | 4. If a RoT service requires more input/output vectors, it | 774 | | may define a parameter structure which embeds multiple | 775 | | input/output buffers addresses. | 776 | | | 777 | | However, as a potential security risk, a malicious NS | 778 | | application can put secure memory addresses into a valid | 779 | | parameter structure to bypass TF-M validation on those | 780 | | memory addresses. | 781 | | | 782 | | The parameter structure can pass TF-M memory access check | 783 | | since itself is valid. However, if the RoT service parses | 784 | | the structure and directly write malicious data from NSPE | 785 | | to the secure memory addresses in parameter structure, the | 786 | | secure data will be tampered. | 787 +---------------+------------------------------------------------------------+ 788 | Category | Tampering | 789 +---------------+------------------------------------------------------------+ 790 | Mitigation | It should be avoided to embed memory addresses into a | 791 | | single input/output vector. If more than 4 memory | 792 | | addresses are required in a RoT service request, it is | 793 | | recommended to split this request into two or multiple | 794 | | service calls and therefore each service call requires no | 795 | | more than 4 input/output vectors. | 796 | | | 797 | | If RoT services request SPM to read and write NS data. | 798 | | SPM will validate the target addresses and can detect the | 799 | | invalid addresses to mitigate this threat. | 800 | | | 801 | | If RoT services can directly access NS memory, it is | 802 | | required to review and confirm the implementation of RoT | 803 | | service request doesn't embed memory addresses. | 804 +---------------+------------------------------------------------------------+ 805 | CVSS Score | 7.1 (High) | 806 +---------------+------------------------------------------------------------+ 807 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:N/I:H/A:N | 808 | String | | 809 +---------------+------------------------------------------------------------+ 810 811.. table:: TFM-GENERIC-SECURE-SERVICE-RW-I-1 812 :widths: 10 50 813 814 +---------------+------------------------------------------------------------+ 815 | Index | **TFM-GENERIC-SECURE-SERVICE-RW-I-1** | 816 +---------------+------------------------------------------------------------+ 817 | Description | Similar to TFM-GENERIC-SECURE-SERVICE-RW-T-2_, a malicious | 818 | | NS application can embed secure memory addresses in a | 819 | | parameter structure in RoT service request input vectors, | 820 | | to read secure data which the NS application must not | 821 | | access. | 822 +---------------+------------------------------------------------------------+ 823 | Justification | Similar to the description in | 824 | | TFM-GENERIC-SECURE-SERVICE-RW-T-2_, the secure memory | 825 | | addresses hidden in the RoT service input/output vector | 826 | | structure may bypass TF-M validation. Without a proper | 827 | | check, the RoT service may copy secure data to NSPE | 828 | | according to the secure memory addresses in structure, | 829 | | secure information can be disclosed. | 830 +---------------+------------------------------------------------------------+ 831 | Category | Information disclosure | 832 +---------------+------------------------------------------------------------+ 833 | Mitigation | It should be avoided to embed memory addresses into a | 834 | | single input/output vector. If more than 4 memory | 835 | | addresses are required in a RoT service request, it is | 836 | | recommended to split this request into two or multiple | 837 | | service calls and therefore each service call requires no | 838 | | more than 4 input/output vectors. | 839 | | | 840 | | If RoT services request SPM to read and write NS data. | 841 | | SPM will validate the target addresses and can detect the | 842 | | invalid addresses to mitigate this threat. | 843 | | | 844 | | If RoT services can directly access NS memory, it is | 845 | | required to review and confirm the implementation of RoT | 846 | | service request doesn't embed memory addresses. | 847 +---------------+------------------------------------------------------------+ 848 | CVSS Score | 7.1 (High) | 849 +---------------+------------------------------------------------------------+ 850 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:N/A:N | 851 | String | | 852 +---------------+------------------------------------------------------------+ 853 854TF-M returns secure service result 855---------------------------------- 856 857This section identifies threats on ``DF4`` defined in `Data Flow Diagram`_. 858 859When RoT service completes the request from NSPE, TF-M returns the success or 860failure error code to NS application. 861 862In single Armv8-M core scenario, TF-M writes the return code value in the 863general purpose register and returns to Non-secure state. 864 865On dual-cpu platforms, TF-M writes the return code to NSPE mailbox message queue 866via mailbox. 867 868.. table:: TFM-GENERIC-RETURN-CODE-I-1 869 :widths: 10 50 870 871 +---------------+------------------------------------------------------------+ 872 | Index | **TFM-GENERIC-RETURN-CODE-I-1** | 873 +---------------+------------------------------------------------------------+ 874 | Description | SPE may leave secure data in the registers not banked | 875 | | after the SPE completes PSA Client calls and executes | 876 | | ``BXNS`` to switch Armv8-M back to Non-secure state. | 877 +---------------+------------------------------------------------------------+ 878 | Justification | If SPE doesn't clean up the secure data in registers not | 879 | | banked before switching into NSPE in Armv8-M core, NSPE | 880 | | can read the SPE context from those registers. | 881 +---------------+------------------------------------------------------------+ 882 | Category | Information disclosure | 883 +---------------+------------------------------------------------------------+ 884 | Mitigation | In single Armv8-M core scenario, TF-M cleans general | 885 | | purpose registers not banked before switching into NSPE to | 886 | | prevent NSPE probing secure context from the registers. | 887 | | | 888 | | When FPU is enabled in TF-M, secure FP context belonging to| 889 | | a secure partition will be saved on this partition's stack | 890 | | and cleaned by hardware during context switching. Also TF-M| 891 | | cleans secure FP context in FP registers before switching | 892 | | into NSPE to prevent NSPE from probing secure FP context. | 893 +---------------+------------------------------------------------------------+ 894 | CVSS Score | 4.3 (Medium) | 895 +---------------+------------------------------------------------------------+ 896 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N | 897 | String | | 898 +---------------+------------------------------------------------------------+ 899 900NS interrupts preempts SPE execution 901------------------------------------ 902 903This section identifies threats on ``DF5`` defined in `Data Flow Diagram`_. 904 905.. table:: TFM-GENERIC-NS-INTERRUPT-I-1 906 :widths: 10 50 907 908 +---------------+------------------------------------------------------------+ 909 | Index | **TFM-GENERIC-NS-INTERRUPT-I-1** | 910 +---------------+------------------------------------------------------------+ 911 | Description | Shared registers may contain secure data when NS | 912 | | interrupts occur. | 913 +---------------+------------------------------------------------------------+ 914 | Justification | The secure data in shared registers should be cleaned up | 915 | | before NSPE can access shared registers. Otherwise, secure | 916 | | data leakage may occur. | 917 +---------------+------------------------------------------------------------+ 918 | Category | Information disclosure | 919 +---------------+------------------------------------------------------------+ 920 | Mitigation | In single Armv8-M core scenario, Armv8-M architecture | 921 | | automatically cleans up the registers not banked before | 922 | | switching to Non-secure state while taking NS interrupts. | 923 | | | 924 | | When FPU is enabled in TF-M, with setting of FPCCR_S.TS = 1| 925 | | besides secure FP context in FP caller registers, FP | 926 | | context in FP callee registers will also be cleaned by | 927 | | hardware automatically when NS interrupts occur, to prevent| 928 | | NSPE from probing secure FP context in FP registers. Refer | 929 | | to Armv8-M Architecture Reference Manual[ARM arm]_ for | 930 | | details. | 931 | | | 932 | | On dual-cpu platforms, shared registers are implementation | 933 | | defined, such as Inter-Processor Communication registers. | 934 | | Dual-cpu platforms must not store any data which may | 935 | | disclose secure information in the shared registers. | 936 +---------------+------------------------------------------------------------+ 937 | CVSS Score | 4.3 (Medium) | 938 +---------------+------------------------------------------------------------+ 939 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N | 940 | String | | 941 +---------------+------------------------------------------------------------+ 942 943.. table:: TFM-GENERIC-NS-INTERRUPT-D-1 944 :widths: 10 50 945 946 +---------------+------------------------------------------------------------+ 947 | Index | **TFM-GENERIC-NS-INTERRUPT-D-1** | 948 +---------------+------------------------------------------------------------+ 949 | Description | An attacker may trigger spurious NS interrupts frequently | 950 | | to block SPE execution. | 951 +---------------+------------------------------------------------------------+ 952 | Justification | In single Armv8-M core scenario, an attacker may inject a | 953 | | malicious NS application or hijack a NS hardware to | 954 | | frequently trigger spurious NS interrupts to keep | 955 | | preempting SPE and block SPE to perform normal secure | 956 | | execution. | 957 +---------------+------------------------------------------------------------+ 958 | Category | Denial of service | 959 +---------------+------------------------------------------------------------+ 960 | Mitigation | It is out of scope of TF-M. | 961 | | | 962 | | Assets protected by TF-M won't be leaked. TF-M won't be | 963 | | directly impacted. | 964 +---------------+------------------------------------------------------------+ 965 | CVSS Score | 4.0 (Medium) | 966 +---------------+------------------------------------------------------------+ 967 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L | 968 | String | | 969 +---------------+------------------------------------------------------------+ 970 971Secure interrupts preempts NSPE execution 972----------------------------------------- 973 974This section identifies threats on ``DF6`` defined in `Data Flow Diagram`_. 975 976.. table:: TFM-GENERIC-S-INTERRUPT-I-1 977 :widths: 10 50 978 979 +---------------+------------------------------------------------------------+ 980 | Index | **TFM-GENERIC-S-INTERRUPT-I-1** | 981 +---------------+------------------------------------------------------------+ 982 | Description | Shared registers may contain secure data when Armv8-M core | 983 | | switches back to Non-secure state on Secure interrupt | 984 | | return. | 985 +---------------+------------------------------------------------------------+ 986 | Justification | Armv8-M architecture doesn't automatically clean up shared | 987 | | registers while returning to Non-secure state during | 988 | | Secure interrupt return. | 989 | | | 990 | | If SPE leaves critical data in the Armv8-M registers not | 991 | | banked, NSPE can read secure context from those registers | 992 | | and secure data leakage may occur. | 993 +---------------+------------------------------------------------------------+ 994 | Category | Information disclosure | 995 +---------------+------------------------------------------------------------+ 996 | Mitigation | TF-M saves NPSE context in general purpose register R4~R11 | 997 | | into secure stack during secure interrupt entry. | 998 | | After secure interrupt handling completes, TF-M unstacks | 999 | | NSPE context from secure stack to overwrite secure context | 1000 | | in R4~R11 before secure interrupt return. | 1001 | | | 1002 | | Armv8-M architecture will automatically unstack NSPE | 1003 | | context from non-secure stack to overwrite other registers | 1004 | | not banked, such as R0~R3 and R12, during secure interrupt | 1005 | | return, before NSPE software can access those registers. | 1006 | | | 1007 | | When FPU is enabled in TF-M, with setting of | 1008 | | FPCCR_S.TS = 1 and FPCCR_S.CLRONRET = 1, besides secure FP | 1009 | | context in FP caller registers, FP context in callee | 1010 | | registers will also be cleaned by hardware automatically | 1011 | | during S exception return, to prevent NSPE from probing | 1012 | | secure FP context in FP registers. Refer to Armv8-M | 1013 | | Architecture Reference Manual [ARM arm]_ for details. | 1014 +---------------+------------------------------------------------------------+ 1015 | CVSS Score | 4.3 (Medium) | 1016 +---------------+------------------------------------------------------------+ 1017 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N | 1018 | String | | 1019 +---------------+------------------------------------------------------------+ 1020 1021Miscellaneous threats 1022--------------------- 1023 1024This section collects threats irrelevant to the valid TF-M data flows shown 1025above. 1026 1027.. table:: TFM-GENERIC-STACK-SEAL 1028 :widths: 10 50 1029 1030 +---------------+------------------------------------------------------------+ 1031 | Index | **TFM-GENERIC-STACK_SEAL** | 1032 +---------------+------------------------------------------------------------+ 1033 | Description | Armv8-M processor Secure software Stack Sealing | 1034 | | vulnerability. | 1035 +---------------+------------------------------------------------------------+ 1036 | Justification | On Armv8-M based processors with TrustZone, if Secure | 1037 | | software does not properly manage the Secure stacks when | 1038 | | the stacks are created, or when performing non-standard | 1039 | | transitioning between states or modes, for example, | 1040 | | creating a fake exception return stack frame to | 1041 | | de-privilege an interrupt, it is possible for Non-secure | 1042 | | world software to manipulate the Secure Stacks, and | 1043 | | potentially influence Secure control flow. | 1044 | | | 1045 | | Refer to [STACK-SEAL]_ for details. | 1046 +---------------+------------------------------------------------------------+ 1047 | Category | Elevation of privilege | 1048 +---------------+------------------------------------------------------------+ 1049 | Mitigation | TF-M has implemented common mitigation against stack seal | 1050 | | vulnerability. | 1051 | | | 1052 | | Refer to [ADVISORY-TFMV-1]_ for details on analysis and | 1053 | | mitigation in TF-M. | 1054 +---------------+------------------------------------------------------------+ 1055 | CVSS Score | 5.3 (Medium) | 1056 +---------------+------------------------------------------------------------+ 1057 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:L/I:L/A:L | 1058 | String | | 1059 +---------------+------------------------------------------------------------+ 1060 1061.. table:: TFM-GENERIC-SVC-CALL-SP-FETCH 1062 :widths: 10 50 1063 1064 +---------------+------------------------------------------------------------+ 1065 | Index | **TFM-GENERIC-SVC-CALL-SP-FETCH** | 1066 +---------------+------------------------------------------------------------+ 1067 | Description | Invoking Secure functions from handler mode may cause TF-M | 1068 | | IPC model to behave unexpectedly. | 1069 +---------------+------------------------------------------------------------+ 1070 | Justification | On Armv8-M based processors with TrustZone, if NSPE calls | 1071 | | a secure function via Secure Gateway (SG) from non-secure | 1072 | | Handler mode , TF-M selects secure process stack by | 1073 | | mistake for SVC handling. | 1074 | | It will most likely trigger a crash in secure world or | 1075 | | reset the whole system, with a very low likelihood of | 1076 | | overwriting some memory contents. | 1077 +---------------+------------------------------------------------------------+ 1078 | Category | Denial of service/Tampering | 1079 +---------------+------------------------------------------------------------+ 1080 | Mitigation | TF-M has enhanced implementation to mitigate this | 1081 | | vulnerability. | 1082 | | | 1083 | | Refer to [ADVISORY-TFMV-2]_ for details on analysis and | 1084 | | mitigation in TF-M. | 1085 +---------------+------------------------------------------------------------+ 1086 | CVSS Score | 4.5 (Medium) | 1087 +---------------+------------------------------------------------------------+ 1088 | CVSS Vector | CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:N/I:L/A:L | 1089 | String | | 1090 +---------------+------------------------------------------------------------+ 1091 1092.. table:: VLLDM instruction security vulnerability 1093 :widths: 10 50 1094 1095 +---------------+------------------------------------------------------------+ 1096 | Index | **TFM-GENERIC-FP-VLLDM** | 1097 +---------------+------------------------------------------------------------+ 1098 | Description | Secure data in FP registers may be disclosed to NSPE when | 1099 | | VLLDM instruction is abandoned due to an exception mid-way.| 1100 +---------------+------------------------------------------------------------+ 1101 | Justification | Refer to [VLLDM Vulnerability]_ for details. | 1102 +---------------+------------------------------------------------------------+ 1103 | Category | Tampering/Information disclosure | 1104 +---------------+------------------------------------------------------------+ 1105 | Mitigation | In current TF-M implementation, when FPU is enabled in SPE,| 1106 | | TF-M configures NSACR to disable NSPE to access FPU. | 1107 | | Therefore, secure data in FP registers is protected from | 1108 | | NSPE. | 1109 | | | 1110 | | Refer to [VLLDM Vulnerability]_, for details on analysis | 1111 | | and mitigation. | 1112 +---------------+------------------------------------------------------------+ 1113 | CVSS Score | 3.4 (Low) | 1114 +---------------+------------------------------------------------------------+ 1115 | CVSS Vector | CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:U/C:L/I:L/A:N | 1116 | String | | 1117 +---------------+------------------------------------------------------------+ 1118 1119*************** 1120Version control 1121*************** 1122 1123.. table:: Version control 1124 1125 +---------+--------------------------------------------------+---------------+ 1126 | Version | Description | TF-M version | 1127 +=========+==================================================+===============+ 1128 | v0.1 | Initial draft | TF-M v1.1 | 1129 +---------+--------------------------------------------------+---------------+ 1130 | v1.0 | First version | TF-M v1.2.0 | 1131 +---------+--------------------------------------------------+---------------+ 1132 | v1.1 | Update version | TF-M v1.5.0 | 1133 +---------+--------------------------------------------------+---------------+ 1134 | v1.2 | Update details to align FP support in NSPE. | TF-M v1.5.0 | 1135 +---------+--------------------------------------------------+---------------+ 1136 1137********* 1138Reference 1139********* 1140 1141.. [Security-Incident-Process] `Security Incident Process <https://developer.trustedfirmware.org/w/collaboration/security_center/reporting/>`_ 1142 1143.. [FF-M] `Arm® Platform Security Architecture Firmware Framework 1.0 <https://developer.arm.com/-/media/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf?revision=2d1429fa-4b5b-461a-a60e-4ef3d8f7f4b4>`_ 1144 1145.. [FF-M 1.1 Extensions] `Arm® Firmware Framework for M 1.1 Extensions <https://documentation-service.arm.com/static/600067c09b9c2d1bb22cd1c5?token=>`_ 1146 1147.. [DUAL-CPU-BOOT] :doc:`Booting a dual core system </technical_references/design_docs/dual-cpu/booting_a_dual_core_system>` 1148 1149.. [CVSS] `Common Vulnerability Scoring System Version 3.1 Calculator <https://www.first.org/cvss/calculator/3.1>`_ 1150 1151.. [CVSS_SPEC] `CVSS v3.1 Specification Document <https://www.first.org/cvss/v3-1/cvss-v31-specification_r1.pdf>`_ 1152 1153.. [STRIDE] `The STRIDE Threat Model <https://docs.microsoft.com/en-us/previous-versions/commerce-server/ee823878(v=cs.20)?redirectedfrom=MSDN>`_ 1154 1155.. [SECURE-BOOT] :doc:`Secure boot </technical_references/design_docs/tfm_secure_boot>` 1156 1157.. [ROLLBACK-PROTECT] :doc:`Rollback protection in TF-M secure boot </technical_references/design_docs/secure_boot_rollback_protection>` 1158 1159.. [ARM arm] `Armv8-M Architecture Reference Manual <https://developer.arm.com/documentation/ddi0553/latest>`_ 1160 1161.. [STACK-SEAL] `Armv8-M processor Secure software Stack Sealing vulnerability <https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing>`_ 1162 1163.. [ADVISORY-TFMV-1] :doc:`Advisory TFMV-1 </security/security_advisories/stack_seal_vulnerability>` 1164 1165.. [ADVISORY-TFMV-2] :doc:`Advisory TFMV-2 </security/security_advisories/svc_caller_sp_fetching_vulnerability>` 1166 1167.. [VLLDM Vulnerability] : `VLLDM instruction Security Vulnerability <https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability>`_ 1168 1169-------------------- 1170 1171*Copyright (c) 2020-2022 Arm Limited. All Rights Reserved.* 1172
