1 /*
2  * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
3  * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /* Versal IPI management enums and defines */
9 
10 #ifndef PLAT_IPI_H
11 #define PLAT_IPI_H
12 
13 #include <stdint.h>
14 
15 #include <ipi.h>
16 
17 /*********************************************************************
18  * IPI agent IDs macros
19  ********************************************************************/
20 #define IPI_ID_PMC	1U
21 #define IPI_ID_APU	2U
22 #define IPI_ID_RPU0	3U
23 #define IPI_ID_RPU1	4U
24 #define IPI_ID_3	5U
25 #define IPI_ID_4	6U
26 #define IPI_ID_5	7U
27 #define IPI_ID_MAX	8U
28 
29 /*********************************************************************
30  * IPI message buffers
31  ********************************************************************/
32 #define IPI_BUFFER_BASEADDR	(0xEB3F0000U)
33 
34 #define IPI_LOCAL_ID		IPI_ID_APU
35 #define IPI_REMOTE_ID		IPI_ID_PMC
36 
37 #define IPI_BUFFER_LOCAL_BASE	(IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
38 #define IPI_BUFFER_REMOTE_BASE	(IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
39 
40 #define IPI_BUFFER_TARGET_LOCAL_OFFSET	(IPI_LOCAL_ID * 0x40U)
41 #define IPI_BUFFER_TARGET_REMOTE_OFFSET	(IPI_REMOTE_ID * 0x40U)
42 
43 #define IPI_BUFFER_MAX_WORDS	8
44 
45 #define IPI_BUFFER_REQ_OFFSET	0x0U
46 #define IPI_BUFFER_RESP_OFFSET	0x20U
47 
48 /*********************************************************************
49  * Platform specific IPI API declarations
50  ********************************************************************/
51 
52 /* Configure IPI table for versal_net */
53 void versal_net_ipi_config_table_init(void);
54 
55 /*******************************************************************************
56  * IPI registers and bitfields
57  ******************************************************************************/
58 #define IPI0_REG_BASE		(0xEB330000U)
59 #define IPI0_TRIG_BIT		(1 << 2)
60 #define PMC_IPI_TRIG_BIT	(1 << 1)
61 #define IPI1_REG_BASE		(0xEB340000U)
62 #define IPI1_TRIG_BIT		(1 << 3)
63 #define IPI2_REG_BASE		(0xEB350000U)
64 #define IPI2_TRIG_BIT		(1 << 4)
65 #define IPI3_REG_BASE		(0xEB360000U)
66 #define IPI3_TRIG_BIT		(1 << 5)
67 #define IPI4_REG_BASE		(0xEB370000U)
68 #define IPI4_TRIG_BIT		(1 << 6)
69 #define IPI5_REG_BASE		(0xEB380000U)
70 #define IPI5_TRIG_BIT		(1 << 7)
71 
72 #endif /* PLAT_IPI_H */
73