1# Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
2# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5
6override PROGRAMMABLE_RESET_ADDRESS := 1
7PSCI_EXTENDED_STATE_ID := 1
8A53_DISABLE_NON_TEMPORAL_HINT := 0
9SEPARATE_CODE_AND_RODATA := 1
10override RESET_TO_BL31 := 1
11PL011_GENERIC_UART := 1
12IPI_CRC_CHECK := 0
13HARDEN_SLS_ALL := 0
14
15# A72 Erratum for SoC
16ERRATA_A72_859971 := 1
17ERRATA_A72_1319367 := 1
18
19ifdef VERSAL_ATF_MEM_BASE
20    $(eval $(call add_define,VERSAL_ATF_MEM_BASE))
21
22    ifndef VERSAL_ATF_MEM_SIZE
23        $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
24    endif
25    $(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
26
27    ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
28        $(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
29    endif
30endif
31
32ifdef VERSAL_BL32_MEM_BASE
33    $(eval $(call add_define,VERSAL_BL32_MEM_BASE))
34
35    ifndef VERSAL_BL32_MEM_SIZE
36        $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
37    endif
38    $(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
39endif
40
41ifdef IPI_CRC_CHECK
42    $(eval $(call add_define,IPI_CRC_CHECK))
43endif
44
45VERSAL_PLATFORM ?= silicon
46$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
47
48ifdef XILINX_OF_BOARD_DTB_ADDR
49$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
50endif
51
52PLAT_XLAT_TABLES_DYNAMIC := 0
53ifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
54$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
55endif
56
57# enable assert() for release/debug builds
58ENABLE_ASSERTIONS := 1
59
60PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
61				-Iplat/xilinx/common/include/			\
62				-Iplat/xilinx/common/ipi_mailbox_service/	\
63				-Iplat/xilinx/versal/include/			\
64				-Iplat/xilinx/versal/pm_service/
65
66include lib/libfdt/libfdt.mk
67# Include GICv3 driver files
68include drivers/arm/gic/v3/gicv3.mk
69include lib/xlat_tables_v2/xlat_tables.mk
70
71PLAT_BL_COMMON_SOURCES	:= 	drivers/arm/dcc/dcc_console.c			\
72				drivers/delay_timer/delay_timer.c		\
73				drivers/delay_timer/generic_delay_timer.c	\
74				${GICV3_SOURCES}				\
75				drivers/arm/pl011/aarch64/pl011_console.S	\
76				plat/common/aarch64/crash_console_helpers.S	\
77				plat/arm/common/arm_cci.c			\
78				plat/arm/common/arm_common.c			\
79				plat/common/plat_gicv3.c			\
80				plat/xilinx/versal/aarch64/versal_helpers.S	\
81				plat/xilinx/versal/aarch64/versal_common.c	\
82				${XLAT_TABLES_LIB_SRCS}
83
84VERSAL_CONSOLE	?=	pl011
85ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
86else
87  $(error "Please define VERSAL_CONSOLE")
88endif
89
90$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
91
92BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
93				lib/cpus/aarch64/cortex_a72.S			\
94				common/fdt_wrappers.c                           \
95				plat/common/plat_psci_common.c			\
96				plat/xilinx/common/ipi.c			\
97				plat/xilinx/common/plat_fdt.c			\
98				plat/xilinx/common/plat_console.c               \
99				plat/xilinx/common/plat_startup.c		\
100				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
101				plat/xilinx/common/pm_service/pm_ipi.c		\
102				plat/xilinx/common/pm_service/pm_api_sys.c	\
103				plat/xilinx/common/pm_service/pm_svc_main.c	\
104				plat/xilinx/common/versal.c			\
105				plat/xilinx/versal/bl31_versal_setup.c		\
106				plat/xilinx/versal/plat_psci.c			\
107				plat/xilinx/versal/plat_versal.c		\
108				plat/xilinx/versal/plat_topology.c		\
109				plat/xilinx/versal/sip_svc_setup.c		\
110				plat/xilinx/versal/versal_gicv3.c		\
111				plat/xilinx/versal/versal_ipi.c			\
112				plat/xilinx/versal/pm_service/pm_client.c	\
113				common/fdt_fixup.c				\
114				${LIBFDT_SRCS}
115
116ifeq ($(HARDEN_SLS_ALL), 1)
117TF_CFLAGS_aarch64      +=      -mharden-sls=all
118endif
119
120ifeq (${ERRATA_ABI_SUPPORT}, 1)
121# enable the cpu macros for errata abi interface
122CORTEX_A72_H_INC	:= 1
123$(eval $(call add_define, CORTEX_A72_H_INC))
124endif
125