1
2 /*
3 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <platform_def.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <lib/xlat_tables/xlat_tables_v2.h>
13 #include <services/el3_spmc_ffa_memory.h>
14
15 #include <plat/common/platform.h>
16 #include "qemu_private.h"
17
18 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
19 DEVICE0_SIZE, \
20 MT_DEVICE | MT_RW | MT_SECURE)
21
22 #ifdef DEVICE1_BASE
23 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
24 DEVICE1_SIZE, \
25 MT_DEVICE | MT_RW | MT_SECURE)
26 #endif
27
28 #ifdef DEVICE2_BASE
29 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
30 DEVICE2_SIZE, \
31 MT_DEVICE | MT_RW | MT_SECURE)
32 #endif
33
34 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
35 SHARED_RAM_SIZE, \
36 MT_DEVICE | MT_RW | MT_SECURE)
37
38 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
39 MT_MEMORY | MT_RW | MT_SECURE)
40
41 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
42 MT_MEMORY | MT_RW | MT_NS)
43
44 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
45 MT_MEMORY | MT_RO | MT_SECURE)
46
47 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
48 MT_MEMORY | MT_RO | MT_SECURE)
49
50 #ifdef FW_HANDOFF_BASE
51 #define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \
52 MT_MEMORY | MT_RW | MT_SECURE)
53 #endif
54 #ifdef FW_NS_HANDOFF_BASE
55 #define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE, \
56 MT_MEMORY | MT_RW | MT_NS)
57 #endif
58 /*
59 * Table of regions for various BL stages to map using the MMU.
60 * This doesn't include TZRAM as the 'mem_layout' argument passed to
61 * arm_configure_mmu_elx() will give the available subset of that,
62 */
63 #ifdef IMAGE_BL1
64 static const mmap_region_t plat_qemu_mmap[] = {
65 MAP_FLASH0,
66 MAP_FLASH1,
67 MAP_SHARED_RAM,
68 MAP_DEVICE0,
69 #ifdef MAP_DEVICE1
70 MAP_DEVICE1,
71 #endif
72 #ifdef MAP_DEVICE2
73 MAP_DEVICE2,
74 #endif
75 {0}
76 };
77 #endif
78 #ifdef IMAGE_BL2
79 static const mmap_region_t plat_qemu_mmap[] = {
80 MAP_FLASH0,
81 MAP_FLASH1,
82 MAP_SHARED_RAM,
83 MAP_DEVICE0,
84 #ifdef MAP_DEVICE1
85 MAP_DEVICE1,
86 #endif
87 #ifdef MAP_DEVICE2
88 MAP_DEVICE2,
89 #endif
90 MAP_NS_DRAM0,
91 #if SPM_MM
92 QEMU_SP_IMAGE_MMAP,
93 #else
94 MAP_BL32_MEM,
95 #endif
96 #ifdef MAP_FW_HANDOFF
97 MAP_FW_HANDOFF,
98 #endif
99 {0}
100 };
101 #endif
102 #ifdef IMAGE_BL31
103 static const mmap_region_t plat_qemu_mmap[] = {
104 MAP_SHARED_RAM,
105 MAP_DEVICE0,
106 #ifdef MAP_DEVICE1
107 MAP_DEVICE1,
108 #endif
109 #ifdef MAP_DEVICE2
110 MAP_DEVICE2,
111 #endif
112 #ifdef MAP_FW_HANDOFF
113 MAP_FW_HANDOFF,
114 #endif
115 #ifdef MAP_FW_NS_HANDOFF
116 MAP_FW_NS_HANDOFF,
117 #endif
118 #if SPM_MM
119 MAP_NS_DRAM0,
120 QEMU_SPM_BUF_EL3_MMAP,
121 #elif !SPMC_AT_EL3
122 MAP_BL32_MEM,
123 #endif
124 {0}
125 };
126 #endif
127 #ifdef IMAGE_BL32
128 static const mmap_region_t plat_qemu_mmap[] = {
129 MAP_SHARED_RAM,
130 MAP_DEVICE0,
131 #ifdef MAP_DEVICE1
132 MAP_DEVICE1,
133 #endif
134 #ifdef MAP_DEVICE2
135 MAP_DEVICE2,
136 #endif
137 {0}
138 };
139 #endif
140
141 /*******************************************************************************
142 * Returns QEMU platform specific memory map regions.
143 ******************************************************************************/
plat_qemu_get_mmap(void)144 const mmap_region_t *plat_qemu_get_mmap(void)
145 {
146 return plat_qemu_mmap;
147 }
148
149 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)150 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
151 {
152 return get_mbedtls_heap_helper(heap_addr, heap_size);
153 }
154 #endif
155
156 #if SPMC_AT_EL3
157 /*
158 * When using the EL3 SPMC implementation allocate the datastore
159 * for tracking shared memory descriptors in normal memory.
160 */
161 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024
162
163 uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE];
164
plat_spmc_shmem_datastore_get(uint8_t ** datastore,size_t * size)165 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
166 {
167 *datastore = plat_spmc_shmem_datastore;
168 *size = PLAT_SPMC_SHMEM_DATASTORE_SIZE;
169 return 0;
170 }
171
plat_spmc_shmem_begin(struct ffa_mtd * desc)172 int plat_spmc_shmem_begin(struct ffa_mtd *desc)
173 {
174 return 0;
175 }
176
plat_spmc_shmem_reclaim(struct ffa_mtd * desc)177 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
178 {
179 return 0;
180 }
181 #endif
182
183 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
184 /*
185 * A dummy implementation of the platform handler for Group0 secure interrupt.
186 */
plat_spmd_handle_group0_interrupt(uint32_t intid)187 int plat_spmd_handle_group0_interrupt(uint32_t intid)
188 {
189 (void)intid;
190 return -1;
191 }
192 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
193
