1# Copyright 2020-2022 NXP
2#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
6# Adding SoC specific defines
7
8ifneq (${CACHE_LINE},)
9$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
10$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
11$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
12endif
13
14ifneq (${INTERCONNECT},)
15$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
16ifeq (${INTERCONNECT}, CCI400)
17ICNNCT_ID := 0x420
18$(eval $(call add_define,ICNNCT_ID))
19endif
20endif
21
22ifneq (${CHASSIS},)
23$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
24endif
25
26ifneq (${PLAT_DDR_PHY},)
27$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
28endif
29
30ifneq (${PHYS_SYS},)
31$(eval $(call add_define,CONFIG_PHYS_64BIT))
32endif
33
34ifneq (${CSF_HDR_SZ},)
35$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
36endif
37
38ifneq (${OCRAM_START_ADDR},)
39$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
40endif
41
42ifneq (${OCRAM_SIZE},)
43$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
44endif
45
46ifneq (${NXP_ROM_RSVD},)
47$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
48endif
49
50ifneq (${BL2_BASE},)
51$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
52endif
53
54ifeq (${SEC_MEM_NON_COHERENT},yes)
55$(eval $(call add_define,SEC_MEM_NON_COHERENT))
56endif
57
58ifneq (${NXP_ESDHC_ENDIANNESS},)
59$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
60endif
61
62ifneq (${NXP_SFP_VER},)
63$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
64endif
65
66ifneq (${NXP_SFP_ENDIANNESS},)
67$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
68endif
69
70ifneq (${NXP_GPIO_ENDIANNESS},)
71$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
72endif
73
74ifneq (${NXP_SNVS_ENDIANNESS},)
75$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
76endif
77
78ifneq (${NXP_GUR_ENDIANNESS},)
79$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
80endif
81
82ifneq (${NXP_FSPI_ENDIANNESS},)
83$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
84endif
85
86ifneq (${NXP_SEC_ENDIANNESS},)
87$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
88endif
89
90ifneq (${NXP_DDR_ENDIANNESS},)
91$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
92endif
93
94ifneq (${NXP_QSPI_ENDIANNESS},)
95$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
96endif
97
98ifneq (${NXP_SCFG_ENDIANNESS},)
99$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
100endif
101
102ifneq (${NXP_IFC_ENDIANNESS},)
103$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
104endif
105
106ifneq (${NXP_DDR_INTLV_256B},)
107$(eval $(call add_define,NXP_DDR_INTLV_256B))
108endif
109
110ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
111$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
112endif
113
114ifeq (${OCRAM_ECC_EN},yes)
115$(eval $(call add_define,CONFIG_OCRAM_ECC_EN))
116include ${PLAT_COMMON_PATH}/ocram/ocram.mk
117endif
118