1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __MT_SPM_VCOREFS__H__ 7 #define __MT_SPM_VCOREFS__H__ 8 9 int spm_vcorefs_get_vcore(unsigned int gear); 10 uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3, 11 u_register_t *x4); 12 13 enum vcorefs_smc_cmd { 14 VCOREFS_SMC_CMD_0 = 0, 15 VCOREFS_SMC_CMD_1, 16 VCOREFS_SMC_CMD_2, 17 VCOREFS_SMC_CMD_3, 18 VCOREFS_SMC_CMD_4, 19 /* check spmfw status */ 20 VCOREFS_SMC_CMD_5, 21 22 /* get spmfw type */ 23 VCOREFS_SMC_CMD_6, 24 25 /* get spm reg status */ 26 VCOREFS_SMC_CMD_7, 27 28 NUM_VCOREFS_SMC_CMD, 29 }; 30 31 enum vcorefs_smc_cmd_new { 32 VCOREFS_SMC_CMD_INIT = 0, 33 VCOREFS_SMC_CMD_KICK = 1, 34 VCOREFS_SMC_CMD_OPP_TYPE = 2, 35 VCOREFS_SMC_CMD_FW_TYPE = 3, 36 VCOREFS_SMC_CMD_GET_UV = 4, 37 VCOREFS_SMC_CMD_GET_FREQ = 5, 38 VCOREFS_SMC_CMD_GET_NUM_V = 6, 39 VCOREFS_SMC_CMD_GET_NUM_F = 7, 40 VCOREFS_SMC_CMD_FB_ACTION = 8, 41 /*chip specific setting */ 42 VCOREFS_SMC_CMD_SET_FREQ = 16, 43 VCOREFS_SMC_CMD_SET_EFUSE = 17, 44 VCOREFS_SMC_CMD_GET_EFUSE = 18, 45 VCOREFS_SMC_CMD_DVFS_HOPPING = 19, 46 VCOREFS_SMC_CMD_DVFS_HOPPING_STATE = 20, 47 }; 48 49 enum dvfsrc_channel { 50 DVFSRC_CHANNEL_1 = 1, 51 DVFSRC_CHANNEL_2, 52 DVFSRC_CHANNEL_3, 53 DVFSRC_CHANNEL_4, 54 NUM_DVFSRC_CHANNEL, 55 }; 56 57 #define _VCORE_BASE_UV 400000 58 #define _VCORE_STEP_UV 6250 59 60 /* PMIC */ 61 #define __vcore_pmic_to_uv(pmic) \ 62 (((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV) 63 64 #define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \ 65 ((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV) 66 67 struct reg_config { 68 uint32_t offset; 69 uint32_t val; 70 }; 71 72 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0) 73 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4) 74 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8) 75 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC) 76 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10) 77 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) 78 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18) 79 #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C) 80 #define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20) 81 #define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24) 82 #define DVFSRC_EMI_REQUEST2 (DVFSRC_BASE + 0x28) 83 #define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x2C) 84 #define DVFSRC_EMI_REQUEST4 (DVFSRC_BASE + 0x30) 85 #define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x34) 86 #define DVFSRC_EMI_REQUEST6 (DVFSRC_BASE + 0x38) 87 #define DVFSRC_EMI_HRT (DVFSRC_BASE + 0x3C) 88 #define DVFSRC_EMI_HRT2 (DVFSRC_BASE + 0x40) 89 #define DVFSRC_EMI_HRT3 (DVFSRC_BASE + 0x44) 90 #define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x48) 91 #define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x4C) 92 #define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x50) 93 #define DVFSRC_EMI_MD2SPM0 (DVFSRC_BASE + 0x54) 94 #define DVFSRC_EMI_MD2SPM1 (DVFSRC_BASE + 0x58) 95 #define DVFSRC_EMI_MD2SPM2 (DVFSRC_BASE + 0x5C) 96 #define DVFSRC_EMI_MD2SPM0_T (DVFSRC_BASE + 0x60) 97 #define DVFSRC_EMI_MD2SPM1_T (DVFSRC_BASE + 0x64) 98 #define DVFSRC_EMI_MD2SPM2_T (DVFSRC_BASE + 0x68) 99 #define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x6C) 100 #define DVFSRC_VCORE_REQUEST2 (DVFSRC_BASE + 0x70) 101 #define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x74) 102 #define DVFSRC_VCORE_REQUEST4 (DVFSRC_BASE + 0x78) 103 #define DVFSRC_VCORE_HRT (DVFSRC_BASE + 0x7C) 104 #define DVFSRC_VCORE_HRT2 (DVFSRC_BASE + 0x80) 105 #define DVFSRC_VCORE_HRT3 (DVFSRC_BASE + 0x84) 106 #define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x88) 107 #define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x8C) 108 #define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x90) 109 #define DVFSRC_VCORE_MD2SPM0 (DVFSRC_BASE + 0x94) 110 #define DVFSRC_VCORE_MD2SPM1 (DVFSRC_BASE + 0x98) 111 #define DVFSRC_VCORE_MD2SPM2 (DVFSRC_BASE + 0x9C) 112 #define DVFSRC_VCORE_MD2SPM0_T (DVFSRC_BASE + 0xA0) 113 #define DVFSRC_VCORE_MD2SPM1_T (DVFSRC_BASE + 0xA4) 114 #define DVFSRC_VCORE_MD2SPM2_T (DVFSRC_BASE + 0xA8) 115 #define DVFSRC_MD_VSRAM_REMAP (DVFSRC_BASE + 0xBC) 116 #define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC0) 117 #define DVFSRC_INT (DVFSRC_BASE + 0xC4) 118 #define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8) 119 #define DVFSRC_INT_CLR (DVFSRC_BASE + 0xCC) 120 #define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD0) 121 #define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD4) 122 #define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xD8) 123 #define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC) 124 #define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0) 125 #define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4) 126 #define DVFSRC_DEBOUNCE_FOUR (DVFSRC_BASE + 0xF0) 127 #define DVFSRC_DEBOUNCE_RISE_FALL (DVFSRC_BASE + 0xF4) 128 #define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8) 129 #define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100) 130 #define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104) 131 #define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108) 132 #define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C) 133 #define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110) 134 #define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114) 135 #define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118) 136 #define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C) 137 #define DVFSRC_MM_BW_0 (DVFSRC_BASE + 0x200) 138 #define DVFSRC_MM_BW_1 (DVFSRC_BASE + 0x204) 139 #define DVFSRC_MM_BW_2 (DVFSRC_BASE + 0x208) 140 #define DVFSRC_MM_BW_3 (DVFSRC_BASE + 0x20C) 141 #define DVFSRC_MM_BW_4 (DVFSRC_BASE + 0x210) 142 #define DVFSRC_MM_BW_5 (DVFSRC_BASE + 0x214) 143 #define DVFSRC_MM_BW_6 (DVFSRC_BASE + 0x218) 144 #define DVFSRC_MM_BW_7 (DVFSRC_BASE + 0x21C) 145 #define DVFSRC_MM_BW_8 (DVFSRC_BASE + 0x220) 146 #define DVFSRC_MM_BW_9 (DVFSRC_BASE + 0x224) 147 #define DVFSRC_MM_BW_10 (DVFSRC_BASE + 0x228) 148 #define DVFSRC_MM_BW_11 (DVFSRC_BASE + 0x22C) 149 #define DVFSRC_MM_BW_12 (DVFSRC_BASE + 0x230) 150 #define DVFSRC_MM_BW_13 (DVFSRC_BASE + 0x234) 151 #define DVFSRC_MM_BW_14 (DVFSRC_BASE + 0x238) 152 #define DVFSRC_MM_BW_15 (DVFSRC_BASE + 0x23C) 153 #define DVFSRC_MD_BW_0 (DVFSRC_BASE + 0x240) 154 #define DVFSRC_MD_BW_1 (DVFSRC_BASE + 0x244) 155 #define DVFSRC_MD_BW_2 (DVFSRC_BASE + 0x248) 156 #define DVFSRC_MD_BW_3 (DVFSRC_BASE + 0x24C) 157 #define DVFSRC_MD_BW_4 (DVFSRC_BASE + 0x250) 158 #define DVFSRC_MD_BW_5 (DVFSRC_BASE + 0x254) 159 #define DVFSRC_MD_BW_6 (DVFSRC_BASE + 0x258) 160 #define DVFSRC_MD_BW_7 (DVFSRC_BASE + 0x25C) 161 #define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x260) 162 #define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x264) 163 #define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x268) 164 #define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x26C) 165 #define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x270) 166 #define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x274) 167 #define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x278) 168 #define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280) 169 #define DVFSRC_MD_BW_URG (DVFSRC_BASE + 0x284) 170 #define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x290) 171 #define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294) 172 #define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x304) 173 #define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x308) 174 #define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x30C) 175 #define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x310) 176 #define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x314) 177 #define DVFSRC_LEVEL_MASK (DVFSRC_BASE + 0x318) 178 #define DVFSRC_DEFAULT_OPP (DVFSRC_BASE + 0x31C) 179 #define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x500) 180 #define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x504) 181 #define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x508) 182 #define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x50C) 183 #define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x510) 184 #define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x514) 185 #define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x518) 186 #define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x51C) 187 #define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x520) 188 #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524) 189 #define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x528) 190 #define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x52C) 191 #define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x530) 192 #define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x534) 193 #define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x538) 194 #define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x53C) 195 #define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x540) 196 #define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x544) 197 #define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x548) 198 #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600) 199 #define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x604) 200 #define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x608) 201 #define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x60C) 202 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) 203 #define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614) 204 #define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x630) 205 #define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x700) 206 #define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x704) 207 #define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x708) 208 #define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x70C) 209 #define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x710) 210 #define DVFSRC_DEBUG_STA_5 (DVFSRC_BASE + 0x714) 211 #define DVFSRC_EMI_REQUEST7 (DVFSRC_BASE + 0x800) 212 #define DVFSRC_EMI_HRT_1 (DVFSRC_BASE + 0x804) 213 #define DVFSRC_EMI_HRT2_1 (DVFSRC_BASE + 0x808) 214 #define DVFSRC_EMI_HRT3_1 (DVFSRC_BASE + 0x80C) 215 #define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x810) 216 #define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x814) 217 #define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00) 218 #define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04) 219 #define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08) 220 #define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C) 221 #define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10) 222 #define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14) 223 #define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18) 224 #define DVFSRC_DDR_HRT (DVFSRC_BASE + 0xA1C) 225 #define DVFSRC_DDR_HRT2 (DVFSRC_BASE + 0xA20) 226 #define DVFSRC_DDR_HRT3 (DVFSRC_BASE + 0xA24) 227 #define DVFSRC_DDR_HRT_1 (DVFSRC_BASE + 0xA28) 228 #define DVFSRC_DDR_HRT2_1 (DVFSRC_BASE + 0xA2C) 229 #define DVFSRC_DDR_HRT3_1 (DVFSRC_BASE + 0xA30) 230 #define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34) 231 #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) 232 #define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C) 233 #define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40) 234 #define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44) 235 #define DVFSRC_DDR_MD2SPM0 (DVFSRC_BASE + 0xA48) 236 #define DVFSRC_DDR_MD2SPM1 (DVFSRC_BASE + 0xA4C) 237 #define DVFSRC_DDR_MD2SPM2 (DVFSRC_BASE + 0xA50) 238 #define DVFSRC_DDR_MD2SPM0_T (DVFSRC_BASE + 0xA54) 239 #define DVFSRC_DDR_MD2SPM1_T (DVFSRC_BASE + 0xA58) 240 #define DVFSRC_DDR_MD2SPM2_T (DVFSRC_BASE + 0xA5C) 241 #define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60) 242 #define DVSFRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0xA64) 243 #define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0xA68) 244 #define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0xA6C) 245 #define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0xA70) 246 #define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0xA74) 247 #define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0xA78) 248 #define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0xA7C) 249 #define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0xA80) 250 #define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0xA84) 251 #define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0xA88) 252 #define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0xA8C) 253 #define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0xA90) 254 #define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0xA94) 255 #define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0xA98) 256 #define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0xA9C) 257 #define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0xAA0) 258 #define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0xAA4) 259 #define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0xAA8) 260 #define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0xAAC) 261 #define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0xAB0) 262 #define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0xAB4) 263 #define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0xAB8) 264 #define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0xABC) 265 #define DVFSRC_HRT_REQ_BW_SW_REG (DVFSRC_BASE + 0xAC0) 266 #define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4) 267 #define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8) 268 #define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC) 269 #define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0) 270 #define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4) 271 #define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8) 272 #define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC) 273 #define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0) 274 #define DVFSRC_LAST (DVFSRC_BASE + 0xAE4) 275 #define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8) 276 #define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC) 277 #define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0) 278 #define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4) 279 #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) 280 #define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC) 281 #define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00) 282 #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) 283 #define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08) 284 #define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C) 285 #define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0) 286 #define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4) 287 #define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8) 288 #define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC) 289 #define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00) 290 #define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04) 291 #define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08) 292 #define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C) 293 #define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0) 294 #define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4) 295 #define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8) 296 #define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC) 297 #define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00) 298 #define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04) 299 #define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08) 300 #define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C) 301 #define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10) 302 #define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14) 303 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) 304 #define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C) 305 #define DVFSRC_VCORE_REQUEST5 (DVFSRC_BASE + 0xD20) 306 #define DVFSRC_VCORE_HRT_1 (DVFSRC_BASE + 0xD24) 307 #define DVFSRC_VCORE_HRT2_1 (DVFSRC_BASE + 0xD28) 308 #define DVFSRC_VCORE_HRT3_1 (DVFSRC_BASE + 0xD2C) 309 #define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xD30) 310 #define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xD34) 311 #define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38) 312 #define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C) 313 #define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0xD40) 314 #define DVFSRC_CURRENT_LEVEL (DVFSRC_BASE + 0xD44) 315 #define DVFSRC_TARGET_LEVEL (DVFSRC_BASE + 0xD48) 316 #define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C) 317 #define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50) 318 #define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54) 319 #define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58) 320 #define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C) 321 #define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60) 322 #define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64) 323 #define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68) 324 #define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C) 325 #define DVFSRC_TARGET_FORCE (DVFSRC_BASE + 0xD70) 326 #define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0xD74) 327 328 #endif /* __MT_SPM_VCOREFS__H__ */ 329
