1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <stddef.h>
7 #include <string.h>
8 #include <common/debug.h>
9 #include <lib/bakery_lock.h>
10 #include <lib/mmio.h>
11 #include <mt_spm.h>
12 #include <mt_spm_internal.h>
13 #include <mt_spm_pmic_wrap.h>
14 #include <mt_spm_reg.h>
15 #include <mt_spm_vcorefs.h>
16 #include <mtk_plat_common.h>
17 #include <mtk_sip_svc.h>
18 #include <platform_def.h>
19
20 #define VCORE_MAX_OPP 4
21 #define DRAM_MAX_OPP 7
22
23 static bool spm_dvfs_init_done;
24 static bool dvfs_enable_done;
25 static int vcore_opp_0_uv = 750000;
26 static int vcore_opp_1_uv = 650000;
27 static int vcore_opp_2_uv = 600000;
28 static int vcore_opp_3_uv = 550000;
29
30 static struct reg_config dvfsrc_init_configs[] = {
31 { DVFSRC_HRT_REQ_UNIT, 0x0000001E },
32 { DVFSRC_DEBOUNCE_TIME, 0x19651965 },
33 { DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
34 { DVFSRC_LEVEL_MASK, 0x000EE000 },
35 { DVFSRC_DDR_QOS0, 0x00000019 },
36 { DVFSRC_DDR_QOS1, 0x00000026 },
37 { DVFSRC_DDR_QOS2, 0x00000033 },
38 { DVFSRC_DDR_QOS3, 0x0000003B },
39 { DVFSRC_DDR_QOS4, 0x0000004C },
40 { DVFSRC_DDR_QOS5, 0x00000066 },
41 { DVFSRC_DDR_QOS6, 0x00660066 },
42 { DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
43 { DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
44 { DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
45 { DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
46 { DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
47 { DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
48 { DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
49 { DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
50 { DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
51 { DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
52 { DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
53 { DVFSRC_MD_LATENCY_IMPROVE, 0x00000040 },
54 { DVFSRC_DDR_REQUEST, 0x00004321 },
55 { DVFSRC_DDR_REQUEST3, 0x00000065 },
56 { DVFSRC_DDR_ADD_REQUEST, 0x66543210 },
57 { DVFSRC_HRT_REQUEST, 0x66654321 },
58 { DVFSRC_DDR_REQUEST5, 0x54321000 },
59 { DVFSRC_DDR_REQUEST7, 0x66000000 },
60 { DVFSRC_VCORE_USER_REQ, 0x00010A29 },
61 { DVFSRC_HRT_HIGH_3, 0x18A618A6 },
62 { DVFSRC_HRT_HIGH_2, 0x18A61183 },
63 { DVFSRC_HRT_HIGH_1, 0x0D690B80 },
64 { DVFSRC_HRT_HIGH, 0x070804B0 },
65 { DVFSRC_HRT_LOW_3, 0x18A518A5 },
66 { DVFSRC_HRT_LOW_2, 0x18A51182 },
67 { DVFSRC_HRT_LOW_1, 0x0D680B7F },
68 { DVFSRC_HRT_LOW, 0x070704AF },
69 { DVFSRC_BASIC_CONTROL_3, 0x00000006 },
70 { DVFSRC_INT_EN, 0x00000002 },
71 { DVFSRC_QOS_EN, 0x0000407C },
72 { DVFSRC_HRT_BW_BASE, 0x00000004 },
73 { DVFSRC_PCIE_VCORE_REQ, 0x65908101 },
74 { DVFSRC_CURRENT_FORCE, 0x00000001 },
75 { DVFSRC_BASIC_CONTROL, 0x6698444B },
76 { DVFSRC_BASIC_CONTROL, 0x6698054B },
77 { DVFSRC_CURRENT_FORCE, 0x00000000 },
78 };
79
80 static struct pwr_ctrl vcorefs_ctrl = {
81 .wake_src = R12_REG_CPU_WAKEUP,
82
83 /* default VCORE DVFS is disabled */
84 .pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
85 SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS),
86
87 /* SPM_AP_STANDBY_CON */
88 /* [0] */
89 .reg_wfi_op = 0,
90 /* [1] */
91 .reg_wfi_type = 0,
92 /* [2] */
93 .reg_mp0_cputop_idle_mask = 0,
94 /* [3] */
95 .reg_mp1_cputop_idle_mask = 0,
96 /* [4] */
97 .reg_mcusys_idle_mask = 0,
98 /* [25] */
99 .reg_md_apsrc_1_sel = 0,
100 /* [26] */
101 .reg_md_apsrc_0_sel = 0,
102 /* [29] */
103 .reg_conn_apsrc_sel = 0,
104
105 /* SPM_SRC_REQ */
106 /* [0] */
107 .reg_spm_apsrc_req = 0,
108 /* [1] */
109 .reg_spm_f26m_req = 0,
110 /* [3] */
111 .reg_spm_infra_req = 0,
112 /* [4] */
113 .reg_spm_vrf18_req = 0,
114 /* [7] FIXME: default disable HW Auto S1*/
115 .reg_spm_ddr_en_req = 1,
116 /* [8] */
117 .reg_spm_dvfs_req = 0,
118 /* [9] */
119 .reg_spm_sw_mailbox_req = 0,
120 /* [10] */
121 .reg_spm_sspm_mailbox_req = 0,
122 /* [11] */
123 .reg_spm_adsp_mailbox_req = 0,
124 /* [12] */
125 .reg_spm_scp_mailbox_req = 0,
126
127 /* SPM_SRC_MASK */
128 /* [0] */
129 .reg_sspm_srcclkena_0_mask_b = 1,
130 /* [1] */
131 .reg_sspm_infra_req_0_mask_b = 1,
132 /* [2] */
133 .reg_sspm_apsrc_req_0_mask_b = 1,
134 /* [3] */
135 .reg_sspm_vrf18_req_0_mask_b = 1,
136 /* [4] */
137 .reg_sspm_ddr_en_0_mask_b = 1,
138 /* [5] */
139 .reg_scp_srcclkena_mask_b = 1,
140 /* [6] */
141 .reg_scp_infra_req_mask_b = 1,
142 /* [7] */
143 .reg_scp_apsrc_req_mask_b = 1,
144 /* [8] */
145 .reg_scp_vrf18_req_mask_b = 1,
146 /* [9] */
147 .reg_scp_ddr_en_mask_b = 1,
148 /* [10] */
149 .reg_audio_dsp_srcclkena_mask_b = 1,
150 /* [11] */
151 .reg_audio_dsp_infra_req_mask_b = 1,
152 /* [12] */
153 .reg_audio_dsp_apsrc_req_mask_b = 1,
154 /* [13] */
155 .reg_audio_dsp_vrf18_req_mask_b = 1,
156 /* [14] */
157 .reg_audio_dsp_ddr_en_mask_b = 1,
158 /* [15] */
159 .reg_apu_srcclkena_mask_b = 1,
160 /* [16] */
161 .reg_apu_infra_req_mask_b = 1,
162 /* [17] */
163 .reg_apu_apsrc_req_mask_b = 1,
164 /* [18] */
165 .reg_apu_vrf18_req_mask_b = 1,
166 /* [19] */
167 .reg_apu_ddr_en_mask_b = 1,
168 /* [20] */
169 .reg_cpueb_srcclkena_mask_b = 1,
170 /* [21] */
171 .reg_cpueb_infra_req_mask_b = 1,
172 /* [22] */
173 .reg_cpueb_apsrc_req_mask_b = 1,
174 /* [23] */
175 .reg_cpueb_vrf18_req_mask_b = 1,
176 /* [24] */
177 .reg_cpueb_ddr_en_mask_b = 1,
178 /* [25] */
179 .reg_bak_psri_srcclkena_mask_b = 0,
180 /* [26] */
181 .reg_bak_psri_infra_req_mask_b = 0,
182 /* [27] */
183 .reg_bak_psri_apsrc_req_mask_b = 0,
184 /* [28] */
185 .reg_bak_psri_vrf18_req_mask_b = 0,
186 /* [29] */
187 .reg_bak_psri_ddr_en_mask_b = 0,
188
189 /* SPM_SRC2_MASK */
190 /* [0] */
191 .reg_msdc0_srcclkena_mask_b = 1,
192 /* [1] */
193 .reg_msdc0_infra_req_mask_b = 1,
194 /* [2] */
195 .reg_msdc0_apsrc_req_mask_b = 1,
196 /* [3] */
197 .reg_msdc0_vrf18_req_mask_b = 1,
198 /* [4] */
199 .reg_msdc0_ddr_en_mask_b = 1,
200 /* [5] */
201 .reg_msdc1_srcclkena_mask_b = 1,
202 /* [6] */
203 .reg_msdc1_infra_req_mask_b = 1,
204 /* [7] */
205 .reg_msdc1_apsrc_req_mask_b = 1,
206 /* [8] */
207 .reg_msdc1_vrf18_req_mask_b = 1,
208 /* [9] */
209 .reg_msdc1_ddr_en_mask_b = 1,
210 /* [10] */
211 .reg_msdc2_srcclkena_mask_b = 1,
212 /* [11] */
213 .reg_msdc2_infra_req_mask_b = 1,
214 /* [12] */
215 .reg_msdc2_apsrc_req_mask_b = 1,
216 /* [13] */
217 .reg_msdc2_vrf18_req_mask_b = 1,
218 /* [14] */
219 .reg_msdc2_ddr_en_mask_b = 1,
220 /* [15] */
221 .reg_ufs_srcclkena_mask_b = 1,
222 /* [16] */
223 .reg_ufs_infra_req_mask_b = 1,
224 /* [17] */
225 .reg_ufs_apsrc_req_mask_b = 1,
226 /* [18] */
227 .reg_ufs_vrf18_req_mask_b = 1,
228 /* [19] */
229 .reg_ufs_ddr_en_mask_b = 1,
230 /* [20] */
231 .reg_usb_srcclkena_mask_b = 1,
232 /* [21] */
233 .reg_usb_infra_req_mask_b = 1,
234 /* [22] */
235 .reg_usb_apsrc_req_mask_b = 1,
236 /* [23] */
237 .reg_usb_vrf18_req_mask_b = 1,
238 /* [24] */
239 .reg_usb_ddr_en_mask_b = 1,
240 /* [25] */
241 .reg_pextp_p0_srcclkena_mask_b = 1,
242 /* [26] */
243 .reg_pextp_p0_infra_req_mask_b = 1,
244 /* [27] */
245 .reg_pextp_p0_apsrc_req_mask_b = 1,
246 /* [28] */
247 .reg_pextp_p0_vrf18_req_mask_b = 1,
248 /* [29] */
249 .reg_pextp_p0_ddr_en_mask_b = 1,
250
251 /* SPM_SRC3_MASK */
252 /* [0] */
253 .reg_pextp_p1_srcclkena_mask_b = 1,
254 /* [1] */
255 .reg_pextp_p1_infra_req_mask_b = 1,
256 /* [2] */
257 .reg_pextp_p1_apsrc_req_mask_b = 1,
258 /* [3] */
259 .reg_pextp_p1_vrf18_req_mask_b = 1,
260 /* [4] */
261 .reg_pextp_p1_ddr_en_mask_b = 1,
262 /* [5] */
263 .reg_gce0_infra_req_mask_b = 1,
264 /* [6] */
265 .reg_gce0_apsrc_req_mask_b = 1,
266 /* [7] */
267 .reg_gce0_vrf18_req_mask_b = 1,
268 /* [8] */
269 .reg_gce0_ddr_en_mask_b = 1,
270 /* [9] */
271 .reg_gce1_infra_req_mask_b = 1,
272 /* [10] */
273 .reg_gce1_apsrc_req_mask_b = 1,
274 /* [11] */
275 .reg_gce1_vrf18_req_mask_b = 1,
276 /* [12] */
277 .reg_gce1_ddr_en_mask_b = 1,
278 /* [13] */
279 .reg_spm_srcclkena_reserved_mask_b = 1,
280 /* [14] */
281 .reg_spm_infra_req_reserved_mask_b = 1,
282 /* [15] */
283 .reg_spm_apsrc_req_reserved_mask_b = 1,
284 /* [16] */
285 .reg_spm_vrf18_req_reserved_mask_b = 1,
286 /* [17] */
287 .reg_spm_ddr_en_reserved_mask_b = 1,
288 /* [18] */
289 .reg_disp0_apsrc_req_mask_b = 1,
290 /* [19] */
291 .reg_disp0_ddr_en_mask_b = 1,
292 /* [20] */
293 .reg_disp1_apsrc_req_mask_b = 1,
294 /* [21] */
295 .reg_disp1_ddr_en_mask_b = 1,
296 /* [22] */
297 .reg_disp2_apsrc_req_mask_b = 1,
298 /* [23] */
299 .reg_disp2_ddr_en_mask_b = 1,
300 /* [24] */
301 .reg_disp3_apsrc_req_mask_b = 1,
302 /* [25] */
303 .reg_disp3_ddr_en_mask_b = 1,
304 /* [26] */
305 .reg_infrasys_apsrc_req_mask_b = 0,
306 /* [27] */
307 .reg_infrasys_ddr_en_mask_b = 1,
308
309 /* [28] */
310 .reg_cg_check_srcclkena_mask_b = 1,
311 /* [29] */
312 .reg_cg_check_apsrc_req_mask_b = 1,
313 /* [30] */
314 .reg_cg_check_vrf18_req_mask_b = 1,
315 /* [31] */
316 .reg_cg_check_ddr_en_mask_b = 1,
317
318 /* SPM_SRC4_MASK */
319 /* [8:0] */
320 .reg_mcusys_merge_apsrc_req_mask_b = 0x11,
321 /* [17:9] */
322 .reg_mcusys_merge_ddr_en_mask_b = 0x11,
323 /* [19:18] */
324 .reg_dramc_md32_infra_req_mask_b = 0,
325 /* [21:20] */
326 .reg_dramc_md32_vrf18_req_mask_b = 0,
327 /* [23:22] */
328 .reg_dramc_md32_ddr_en_mask_b = 0,
329 /* [24] */
330 .reg_dvfsrc_event_trigger_mask_b = 1,
331
332 /* SPM_WAKEUP_EVENT_MASK2 */
333 /* [3:0] */
334 .reg_sc_sw2spm_wakeup_mask_b = 0,
335 /* [4] */
336 .reg_sc_adsp2spm_wakeup_mask_b = 0,
337 /* [8:5] */
338 .reg_sc_sspm2spm_wakeup_mask_b = 0,
339 /* [9] */
340 .reg_sc_scp2spm_wakeup_mask_b = 0,
341 /* [10] */
342 .reg_csyspwrup_ack_mask = 0,
343 /* [11] */
344 .reg_csyspwrup_req_mask = 1,
345
346 /* SPM_WAKEUP_EVENT_MASK */
347 /* [31:0] */
348 .reg_wakeup_event_mask = 0xEFFFFFFF,
349
350 /* SPM_WAKEUP_EVENT_EXT_MASK */
351 /* [31:0] */
352 .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
353 };
354
355 struct spm_lp_scen __spm_vcorefs = {
356 .pwrctrl = &vcorefs_ctrl,
357 };
358
spm_vcorefs_pwarp_cmd(uint64_t cmd,uint64_t val)359 static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
360 {
361 if (cmd < NR_IDX_ALL) {
362 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
363 } else {
364 INFO("cmd out of range!\n");
365 }
366 }
367
spm_dvfsfw_init(uint64_t boot_up_opp,uint64_t dram_issue)368 void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
369 {
370 if (spm_dvfs_init_done == false) {
371 mmio_write_32(SPM_DVFS_MISC, (mmio_read_32(SPM_DVFS_MISC) &
372 ~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
373
374 mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
375 mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
376
377 spm_dvfs_init_done = true;
378 }
379 }
380
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl * dest_pwr_ctrl,const struct pwr_ctrl * src_pwr_ctrl)381 void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
382 const struct pwr_ctrl *src_pwr_ctrl)
383 {
384 uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
385 SPM_FLAG_DISABLE_VCORE_DFS |
386 SPM_FLAG_ENABLE_VOLTAGE_BIN;
387
388 dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
389 (src_pwr_ctrl->pcm_flags & dvfs_mask);
390
391 if (dest_pwr_ctrl->pcm_flags_cust) {
392 dest_pwr_ctrl->pcm_flags_cust = (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
393 (src_pwr_ctrl->pcm_flags & dvfs_mask);
394 }
395 }
396
spm_go_to_vcorefs(uint64_t spm_flags)397 void spm_go_to_vcorefs(uint64_t spm_flags)
398 {
399 __spm_set_power_control(__spm_vcorefs.pwrctrl);
400 __spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
401 __spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
402 __spm_send_cpu_wakeup_event();
403 }
404
spm_vcorefs_args(uint64_t x1,uint64_t x2,uint64_t x3)405 uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3)
406 {
407 uint64_t ret = 0U;
408 uint64_t cmd = x1;
409 uint64_t spm_flags;
410
411 switch (cmd) {
412 case VCOREFS_SMC_CMD_0:
413 spm_dvfsfw_init(x2, x3);
414 break;
415 case VCOREFS_SMC_CMD_1:
416 spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
417 if (x2 & SPM_FLAG_DISABLE_VCORE_DVS)
418 spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
419 if (x2 & SPM_FLAG_DISABLE_VCORE_DFS)
420 spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
421 spm_go_to_vcorefs(spm_flags);
422 break;
423 case VCOREFS_SMC_CMD_3:
424 spm_vcorefs_pwarp_cmd(x2, x3);
425 break;
426 case VCOREFS_SMC_CMD_2:
427 case VCOREFS_SMC_CMD_4:
428 case VCOREFS_SMC_CMD_5:
429 case VCOREFS_SMC_CMD_7:
430 default:
431 break;
432 }
433 return ret;
434 }
435
dvfsrc_init(void)436 static void dvfsrc_init(void)
437 {
438 int i;
439 int count = ARRAY_SIZE(dvfsrc_init_configs);
440
441 if (dvfs_enable_done == false) {
442 for (i = 0; i < count; i++) {
443 mmio_write_32(dvfsrc_init_configs[i].offset,
444 dvfsrc_init_configs[i].val);
445 }
446
447 mmio_write_32(DVFSRC_QOS_EN, 0x0011007C);
448
449 dvfs_enable_done = true;
450 }
451 }
452
spm_vcorefs_vcore_setting(uint64_t flag)453 static void spm_vcorefs_vcore_setting(uint64_t flag)
454 {
455 spm_vcorefs_pwarp_cmd(3, __vcore_uv_to_pmic(vcore_opp_3_uv));
456 spm_vcorefs_pwarp_cmd(2, __vcore_uv_to_pmic(vcore_opp_2_uv));
457 spm_vcorefs_pwarp_cmd(1, __vcore_uv_to_pmic(vcore_opp_1_uv));
458 spm_vcorefs_pwarp_cmd(0, __vcore_uv_to_pmic(vcore_opp_0_uv));
459 }
460
spm_vcorefs_get_vcore(unsigned int gear)461 int spm_vcorefs_get_vcore(unsigned int gear)
462 {
463 int ret_val;
464
465 switch (gear) {
466 case 3:
467 ret_val = vcore_opp_0_uv;
468 break;
469 case 2:
470 ret_val = vcore_opp_1_uv;
471 break;
472 case 1:
473 ret_val = vcore_opp_2_uv;
474 break;
475 case 0:
476 default:
477 ret_val = vcore_opp_3_uv;
478 break;
479 }
480 return ret_val;
481 }
482
spm_vcorefs_v2_args(u_register_t x1,u_register_t x2,u_register_t x3,u_register_t * x4)483 uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3, u_register_t *x4)
484 {
485 uint64_t ret = 0U;
486 uint64_t cmd = x1;
487 uint64_t spm_flags;
488
489 switch (cmd) {
490 case VCOREFS_SMC_CMD_INIT:
491 /* vcore_dvfs init + kick */
492 spm_dvfsfw_init(0, 0);
493 spm_vcorefs_vcore_setting(x3 & 0xF);
494 spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
495 if (x2 & 0x1) {
496 spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
497 }
498 if (x2 & 0x2) {
499 spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
500 }
501 spm_go_to_vcorefs(spm_flags);
502 dvfsrc_init();
503 *x4 = 0U;
504 break;
505 case VCOREFS_SMC_CMD_OPP_TYPE:
506 /* get dram type */
507 *x4 = 0U;
508 break;
509 case VCOREFS_SMC_CMD_FW_TYPE:
510 *x4 = 0U;
511 break;
512 case VCOREFS_SMC_CMD_GET_UV:
513 *x4 = spm_vcorefs_get_vcore(x2);
514 break;
515 case VCOREFS_SMC_CMD_GET_NUM_V:
516 *x4 = VCORE_MAX_OPP;
517 break;
518 case VCOREFS_SMC_CMD_GET_NUM_F:
519 *x4 = DRAM_MAX_OPP;
520 break;
521 default:
522 break;
523 }
524
525 return ret;
526 }
527
