1 /*
2 * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9
10 #include <mt_lp_rm.h>
11 #include <mt_spm.h>
12 #include <mt_spm_cond.h>
13 #include <mt_spm_constraint.h>
14 #include <mt_spm_conservation.h>
15 #include <mt_spm_idle.h>
16 #include <mt_spm_internal.h>
17 #include <mt_spm_notifier.h>
18 #include <mt_spm_rc_internal.h>
19 #include <mt_spm_resource_req.h>
20 #include <mt_spm_reg.h>
21 #include <mt_spm_suspend.h>
22 #include <plat_pm.h>
23 #include <plat_mtk_lpm.h>
24
25 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
26 #include <mt_cirq.h>
27 #include <mt_gic_v3.h>
28 #endif
29
30 #define CONSTRAINT_BUS26M_ALLOW \
31 (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
32 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
33 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
34 MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
35 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
36 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
37
38 #define CONSTRAINT_BUS26M_PCM_FLAG \
39 (SPM_FLAG_DISABLE_INFRA_PDN | \
40 SPM_FLAG_DISABLE_VCORE_DVS | \
41 SPM_FLAG_DISABLE_VCORE_DFS | \
42 SPM_FLAG_SRAM_SLEEP_CTRL | \
43 SPM_FLAG_ENABLE_TIA_WORKAROUND | \
44 SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
45 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
46
47 #define CONSTRAINT_BUS26M_PCM_FLAG1 \
48 (SPM_FLAG1_DISABLE_MD26M_CK_OFF)
49
50 #define CONSTRAINT_BUS26M_RESOURCE_REQ 0U
51
52 static unsigned int bus26m_ext_opand;
53 static struct mt_irqremain *refer2remain_irq;
54 static struct mt_spm_cond_tables cond_bus26m = {
55 .name = "bus26m",
56 .table_cg = {
57 0x07CBF1FC, /* MTCMOS1 */
58 0x0A0D8856, /* INFRA0 */
59 0x03AF9A00, /* INFRA1 */
60 0x86000650, /* INFRA2 */
61 0xC800C000, /* INFRA3 */
62 0x00000000, /* INFRA4 */
63 0x4000007C, /* INFRA5 */
64 0x280E0800, /* MMSYS0 */
65 0x00000001, /* MMSYS1 */
66 0x00000000, /* MMSYS2 */
67 },
68 .table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
69 PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
70 PLL_BIT_MMPLL),
71 };
72
73 static struct mt_spm_cond_tables cond_bus26m_res = {
74 .table_cg = { 0U },
75 .table_pll = 0U,
76 };
77
78 static struct constraint_status status = {
79 .id = MT_RM_CONSTRAINT_ID_BUS26M,
80 .valid = (MT_SPM_RC_VALID_SW |
81 MT_SPM_RC_VALID_COND_LATCH),
82 .cond_block = 0U,
83 .enter_cnt = 0U,
84 .cond_res = &cond_bus26m_res,
85 };
86
87 /*
88 * Cirq will take the place of gic when gic is off.
89 * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
90 * Therefore, we need to set irq pending for specific wakeup source.
91 */
92 #ifdef ATF_PLAT_CIRQ_UNSUPPORT
93 #define do_irqs_delivery()
94 #else
mt_spm_irq_remain_dump(struct mt_irqremain * irqs,unsigned int irq_index,struct wake_status * wakeup)95 static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
96 unsigned int irq_index,
97 struct wake_status *wakeup)
98 {
99 INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
100 wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
101 wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
102 wakeup->tr.comm.b_sw_flag1);
103
104 INFO("irq:%u(0x%08x) set pending\n",
105 irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
106 }
107
do_irqs_delivery(void)108 static void do_irqs_delivery(void)
109 {
110 unsigned int idx;
111 int res = 0;
112 struct wake_status *wakeup = NULL;
113 struct mt_irqremain *irqs = refer2remain_irq;
114
115 res = spm_conservation_get_result(&wakeup);
116
117 if ((res != 0) && (irqs == NULL)) {
118 return;
119 }
120
121 for (idx = 0U; idx < irqs->count; ++idx) {
122 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
123 ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
124 if ((irqs->wakeupsrc_cat[idx] &
125 MT_IRQ_REMAIN_CAT_LOG) != 0U) {
126 mt_spm_irq_remain_dump(irqs, idx, wakeup);
127 }
128
129 mt_irq_set_pending(irqs->irqs[idx]);
130 }
131 }
132 }
133 #endif
134
spm_bus26m_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)135 static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
136 unsigned int *resource_req)
137 {
138 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
139 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
140 *resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
141 }
142
spm_is_valid_rc_bus26m(unsigned int cpu,int state_id)143 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
144 {
145 (void)cpu;
146 (void)state_id;
147
148 return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
149 }
150
spm_update_rc_bus26m(int state_id,int type,const void * val)151 int spm_update_rc_bus26m(int state_id, int type, const void *val)
152 {
153 const struct mt_spm_cond_tables *tlb;
154 const struct mt_spm_cond_tables *tlb_check;
155 int res = MT_RM_STATUS_OK;
156
157 if (val == NULL) {
158 return MT_RM_STATUS_BAD;
159 }
160
161 if (type == PLAT_RC_UPDATE_CONDITION) {
162 tlb = (const struct mt_spm_cond_tables *)val;
163 tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
164
165 status.cond_block =
166 mt_spm_cond_check(state_id, tlb, tlb_check,
167 ((status.valid &
168 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
169 &cond_bus26m_res : NULL);
170 } else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
171 refer2remain_irq = (struct mt_irqremain *)val;
172 } else {
173 res = MT_RM_STATUS_BAD;
174 }
175
176 return res;
177 }
178
spm_allow_rc_bus26m(int state_id)179 unsigned int spm_allow_rc_bus26m(int state_id)
180 {
181 (void)state_id;
182
183 return CONSTRAINT_BUS26M_ALLOW;
184 }
185
spm_run_rc_bus26m(unsigned int cpu,int state_id)186 int spm_run_rc_bus26m(unsigned int cpu, int state_id)
187 {
188 (void)cpu;
189
190 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
191 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
192 (IS_PLAT_SUSPEND_ID(state_id) ?
193 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
194 #endif
195 if (IS_PLAT_SUSPEND_ID(state_id)) {
196 mt_spm_suspend_enter(state_id,
197 (MT_SPM_EX_OP_SET_WDT |
198 MT_SPM_EX_OP_HW_S1_DETECT |
199 bus26m_ext_opand),
200 CONSTRAINT_BUS26M_RESOURCE_REQ);
201 } else {
202 mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
203 spm_bus26m_conduct);
204 }
205
206 return 0;
207 }
208
spm_reset_rc_bus26m(unsigned int cpu,int state_id)209 int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
210 {
211 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
212
213 (void)cpu;
214
215 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
216 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
217 #endif
218 if (IS_PLAT_SUSPEND_ID(state_id)) {
219 ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
220 mt_spm_suspend_resume(state_id, ext_op, NULL);
221 bus26m_ext_opand = 0U;
222 } else {
223 mt_spm_idle_generic_resume(state_id, ext_op, NULL);
224 status.enter_cnt++;
225 }
226
227 do_irqs_delivery();
228
229 return 0;
230 }
231
