1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9
10 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
11 #include <mt_gic_v3.h>
12 #endif
13
14 #include <mt_lp_rm.h>
15 #include <mt_spm.h>
16 #include <mt_spm_cond.h>
17 #include <mt_spm_conservation.h>
18 #include <mt_spm_constraint.h>
19 #include <mt_spm_idle.h>
20 #include <mt_spm_internal.h>
21 #include <mt_spm_notifier.h>
22 #include <mt_spm_pmic_wrap.h>
23 #include <mt_spm_rc_internal.h>
24 #include <mt_spm_reg.h>
25 #include <mt_spm_resource_req.h>
26 #include <mt_spm_suspend.h>
27
28 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
29 #include <mt_cirq.h>
30 #endif
31
32 #include <plat_mtk_lpm.h>
33 #include <plat_pm.h>
34
35 #define CONSTRAINT_BUS26M_ALLOW \
36 (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
37 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
38 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
39 MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
40 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
41 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
42
43 #define CONSTRAINT_BUS26M_PCM_FLAG \
44 (SPM_FLAG_DISABLE_INFRA_PDN | \
45 SPM_FLAG_DISABLE_VCORE_DVS | \
46 SPM_FLAG_DISABLE_VCORE_DFS | \
47 SPM_FLAG_SRAM_SLEEP_CTRL | \
48 SPM_FLAG_ENABLE_TIA_WORKAROUND | \
49 SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
50 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
51
52 #define CONSTRAINT_BUS26M_PCM_FLAG1 (0U)
53 #define CONSTRAINT_BUS26M_RESOURCE_REQ (0U)
54
55 static unsigned int bus26m_ext_opand;
56 static struct mt_irqremain *refer2remain_irq;
57 static struct mt_spm_cond_tables cond_bus26m = {
58 .name = "bus26m",
59 .table_cg = {
60 0x0385E03C, /* MTCMOS1 */
61 0x003F0100, /* INFRA0 */
62 0x0A040802, /* INFRA1 */
63 0x06017E51, /* INFRA2 */
64 0x08000000, /* INFRA3 */
65 0x00000000, /* INFRA4 */
66 0x00000000, /* INFRA5 */
67 0x03720820, /* MMSYS0 */
68 0x00000000, /* MMSYS1 */
69 0x00000000, /* MMSYS2 */
70 0x00015151, /* MMSYS3 */
71 },
72 .table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
73 PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
74 PLL_BIT_MMPLL),
75 };
76
77 static struct mt_spm_cond_tables cond_bus26m_res = {
78 .table_cg = {0U},
79 .table_pll = 0U,
80 };
81
82 static struct constraint_status status = {
83 .id = MT_RM_CONSTRAINT_ID_BUS26M,
84 .valid = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_COND_LATCH),
85 .cond_block = 0U,
86 .enter_cnt = 0U,
87 .cond_res = &cond_bus26m_res,
88 };
89
90 /*
91 * Cirq will take the place of gic when gic is off.
92 * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
93 * Therefore, we need to set irq pending for specific wakeup source.
94 */
95 #ifdef ATF_PLAT_CIRQ_UNSUPPORT
96 #define do_irqs_delivery()
97 #else
mt_spm_irq_remain_dump(struct mt_irqremain * irqs,unsigned int irq_index,struct wake_status * wakeup)98 static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
99 unsigned int irq_index,
100 struct wake_status *wakeup)
101 {
102 INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
103 wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
104 wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
105 wakeup->tr.comm.b_sw_flag1);
106
107 INFO("irq:%u(0x%08x) set pending\n",
108 irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
109 }
110
do_irqs_delivery(void)111 static void do_irqs_delivery(void)
112 {
113 unsigned int idx;
114 int res = 0;
115 struct wake_status *wakeup = NULL;
116 struct mt_irqremain *irqs = refer2remain_irq;
117
118 res = spm_conservation_get_result(&wakeup);
119
120 if ((res != 0) && (irqs == NULL)) {
121 return;
122 }
123
124 for (idx = 0; idx < irqs->count; ++idx) {
125 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
126 ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
127 if ((irqs->wakeupsrc_cat[idx] & MT_IRQ_REMAIN_CAT_LOG) != 0U) {
128 mt_spm_irq_remain_dump(irqs, idx, wakeup);
129 }
130
131 mt_irq_set_pending(irqs->irqs[idx]);
132 }
133 }
134 }
135 #endif
136
spm_bus26m_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)137 static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp, unsigned int *resource_req)
138 {
139 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
140 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
141 *resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
142 }
143
spm_is_valid_rc_bus26m(unsigned int cpu,int state_id)144 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
145 {
146 (void)cpu;
147 (void)state_id;
148
149 return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
150 }
151
spm_update_rc_bus26m(int state_id,int type,const void * val)152 int spm_update_rc_bus26m(int state_id, int type, const void *val)
153 {
154 const struct mt_spm_cond_tables *tlb;
155 const struct mt_spm_cond_tables *tlb_check;
156 int res = MT_RM_STATUS_OK;
157
158 if (val == NULL) {
159 res = MT_RM_STATUS_BAD;
160 } else {
161 if (type == PLAT_RC_UPDATE_CONDITION) {
162 tlb = (const struct mt_spm_cond_tables *)val;
163 tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
164
165 status.cond_block =
166 mt_spm_cond_check(state_id, tlb, tlb_check,
167 ((status.valid &
168 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
169 (&cond_bus26m_res) : (NULL));
170 } else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
171 refer2remain_irq = (struct mt_irqremain *)val;
172 } else {
173 res = MT_RM_STATUS_BAD;
174 }
175 }
176
177 return res;
178 }
179
spm_allow_rc_bus26m(int state_id)180 unsigned int spm_allow_rc_bus26m(int state_id)
181 {
182 (void)state_id;
183
184 return CONSTRAINT_BUS26M_ALLOW;
185 }
186
spm_run_rc_bus26m(unsigned int cpu,int state_id)187 int spm_run_rc_bus26m(unsigned int cpu, int state_id)
188 {
189 (void)cpu;
190
191 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
192
193 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
194
195 #ifdef ATF_VOLTAGE_BIN_VCORE_SUPPORT
196 #define SUSPEND_VB_MAGIC (0x5642)
197 if (IS_PLAT_SUSPEND_ID(state_id)) {
198 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
199 ((SUSPEND_VB_MAGIC << 16) |
200 spm_get_suspend_vcore_voltage_idx()));
201 }
202 #endif
203 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
204 (IS_PLAT_SUSPEND_ID(state_id) ?
205 (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
206 #endif
207 if (IS_PLAT_SUSPEND_ID(state_id)) {
208 mt_spm_suspend_enter(state_id,
209 (MT_SPM_EX_OP_CLR_26M_RECORD |
210 MT_SPM_EX_OP_SET_WDT |
211 MT_SPM_EX_OP_HW_S1_DETECT |
212 bus26m_ext_opand),
213 CONSTRAINT_BUS26M_RESOURCE_REQ);
214 } else {
215 mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
216 }
217
218 return 0;
219 }
220
spm_reset_rc_bus26m(unsigned int cpu,int state_id)221 int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
222 {
223 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
224
225 (void)cpu;
226
227 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
228 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
229 #endif
230 if (IS_PLAT_SUSPEND_ID(state_id)) {
231 ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
232 mt_spm_suspend_resume(state_id, ext_op, NULL);
233 bus26m_ext_opand = 0U;
234 } else {
235 mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
236 status.enter_cnt++;
237 }
238
239 do_irqs_delivery();
240 return 0;
241 }
242
