1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /**************************************************************** 8 * Auto generated by DE, please DO NOT modify this file directly. 9 ****************************************************************/ 10 11 #ifndef MT_SPM_REG_H 12 #define MT_SPM_REG_H 13 14 #include "pcm_def.h" 15 #include "sleep_def.h" 16 #include <spm_reg.h> 17 18 /* Define and Declare */ 19 20 /* POWERON_CONFIG_EN (0x10006000+0x000) */ 21 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 22 #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 23 /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ 24 #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ 25 /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ 26 #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ 27 /* SPM_CLK_CON (0x10006000+0x00C) */ 28 #define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ 29 #define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ 30 #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ 31 #define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 32 #define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ 33 #define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ 34 #define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ 35 #define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ 36 #define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 37 #define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ 38 #define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ 39 #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ 40 #define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ 41 #define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ 42 /* SPM_CLK_SETTLE (0x10006000+0x010) */ 43 #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ 44 /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ 45 #define REG_WFI_OP_LSB (1U << 0) /* 1b */ 46 #define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ 47 #define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ 48 #define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ 49 #define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ 50 #define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ 51 #define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ 52 #define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ 53 /* PCM_CON0 (0x10006000+0x018) */ 54 #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 55 #define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 56 #define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ 57 #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 58 #define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ 59 /* PCM_CON1 (0x10006000+0x01C) */ 60 #define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ 61 #define RG_IM_SLEEP_LSB (1U << 1) /* 1b */ 62 #define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ 63 #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ 64 #define RG_IM_PDN_LSB (1U << 4) /* 1b */ 65 #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 66 #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ 67 #define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 68 #define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ 69 #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ 70 #define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ 71 #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ 72 #define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ 73 #define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 74 #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 75 #define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ 76 #define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ 77 /* SPM_POWER_ON_VAL2 (0x10006000+0x020) */ 78 #define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ 79 /* SPM_POWER_ON_VAL3 (0x10006000+0x024) */ 80 #define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ 81 /* PCM_REG_DATA_INI (0x10006000+0x028) */ 82 #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ 83 /* PCM_PWR_IO_EN (0x10006000+0x02C) */ 84 #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ 85 #define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ 86 /* PCM_TIMER_VAL (0x10006000+0x030) */ 87 #define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ 88 /* PCM_WDT_VAL (0x10006000+0x034) */ 89 #define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ 90 /* SPM_SW_RST_CON (0x10006000+0x040) */ 91 #define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ 92 #define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ 93 /* SPM_SW_RST_CON_SET (0x10006000+0x044) */ 94 #define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ 95 #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ 96 /* SPM_SW_RST_CON_CLR (0x10006000+0x048) */ 97 #define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ 98 #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ 99 /* VS1_PSR_MASK_B (0x10006000+0x04C) */ 100 #define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ 101 #define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ 102 /* VS2_PSR_MASK_B (0x10006000+0x050) */ 103 #define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ 104 #define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ 105 #define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */ 106 /* MD32_CLK_CON (0x10006000+0x084) */ 107 #define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ 108 #define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ 109 /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ 110 #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ 111 /* SPM_SWINT (0x10006000+0x08C) */ 112 #define SPM_SWINT_LSB (1U << 0) /* 32b */ 113 /* SPM_SWINT_SET (0x10006000+0x090) */ 114 #define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ 115 /* SPM_SWINT_CLR (0x10006000+0x094) */ 116 #define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ 117 /* SPM_SCP_MAILBOX (0x10006000+0x098) */ 118 #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ 119 /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ 120 #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ 121 /* SPM_TWAM_CON (0x10006000+0x0A0) */ 122 #define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ 123 #define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ 124 #define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ 125 #define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ 126 #define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ 127 #define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ 128 #define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ 129 #define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ 130 /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ 131 #define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ 132 /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ 133 #define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ 134 #define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ 135 #define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ 136 #define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ 137 /* SPM_SCP_IRQ (0x10006000+0x0AC) */ 138 #define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ 139 #define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 140 /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ 141 #define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ 142 /* SPM_IRQ_MASK (0x10006000+0x0B4) */ 143 #define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ 144 /* DDR_EN_DBC (0x10006000+0x0B4) */ 145 #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 16) /* 1b */ 146 /* SPM_SRC_REQ (0x10006000+0x0B8) */ 147 #define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ 148 #define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ 149 #define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ 150 #define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ 151 #define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */ 152 #define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ 153 #define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ 154 #define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ 155 #define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ 156 #define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ 157 /* SPM_SRC_MASK (0x10006000+0x0BC) */ 158 #define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */ 159 #define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */ 160 #define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */ 161 #define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */ 162 #define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */ 163 #define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */ 164 #define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */ 165 #define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */ 166 #define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */ 167 #define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */ 168 #define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */ 169 #define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */ 170 #define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ 171 #define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */ 172 #define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */ 173 #define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 174 #define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */ 175 #define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */ 176 #define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */ 177 #define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */ 178 #define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */ 179 #define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */ 180 #define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ 181 #define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 182 #define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 183 #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 184 #define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ 185 #define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 186 #define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 187 #define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 188 #define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 189 #define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 190 /* SPM_SRC2_MASK (0x10006000+0x0C0) */ 191 #define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 192 #define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 193 #define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 194 #define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 195 #define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ 196 #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ 197 #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ 198 #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ 199 #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ 200 #define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */ 201 #define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ 202 #define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ 203 #define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ 204 #define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ 205 #define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */ 206 #define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 207 #define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ 208 #define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ 209 #define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */ 210 #define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ 211 #define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ 212 #define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 213 #define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ 214 #define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 215 #define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 216 #define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 217 #define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ 218 #define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ 219 #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ 220 #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 221 #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 222 #define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 223 /* SPM_SRC3_MASK (0x10006000+0x0C4) */ 224 #define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ 225 #define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */ 226 #define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */ 227 #define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */ 228 #define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */ 229 #define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ 230 #define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ 231 #define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ 232 #define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */ 233 #define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */ 234 #define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */ 235 #define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */ 236 #define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */ 237 #define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */ 238 #define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ 239 #define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ 240 #define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ 241 #define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ 242 #define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */ 243 #define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ 244 #define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 245 #define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ 246 #define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ 247 #define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ 248 #define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 249 #define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 250 #define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 251 #define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 252 #define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 253 /* SPM_SRC4_MASK (0x10006000+0x0C8) */ 254 #define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */ 255 #define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ 256 #define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ 257 #define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ 258 #define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ 259 #define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */ 260 #define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */ 261 #define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */ 262 #define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 263 #define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */ 264 #define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ 265 #define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */ 266 #define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */ 267 /* SPM_SRC5_MASK (0x10006000+0x0CC) */ 268 #define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ 269 #define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */ 270 /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ 271 #define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 272 /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */ 273 #define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 274 /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */ 275 #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ 276 /* SCP_CLK_CON (0x10006000+0x0DC) */ 277 #define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ 278 #define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ 279 #define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */ 280 #define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ 281 #define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ 282 /* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */ 283 #define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */ 284 #define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */ 285 #define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */ 286 #define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */ 287 #define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */ 288 #define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */ 289 #define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */ 290 #define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */ 291 #define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */ 292 #define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */ 293 #define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 294 #define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 295 #define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 296 #define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 297 #define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ 298 #define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 299 #define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 300 #define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 301 #define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 302 #define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ 303 #define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 304 #define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 305 #define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 306 #define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 307 #define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ 308 #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ 309 #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ 310 #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ 311 #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ 312 #define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */ 313 #define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ 314 #define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ 315 /* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */ 316 #define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ 317 #define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ 318 #define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ 319 #define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ 320 #define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */ 321 #define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ 322 #define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ 323 #define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ 324 #define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ 325 #define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */ 326 #define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 327 #define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 328 #define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 329 #define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 330 #define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ 331 #define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 332 #define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 333 #define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 334 #define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 335 #define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ 336 #define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 337 #define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 338 #define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 339 #define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 340 #define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ 341 #define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ 342 #define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */ 343 #define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ 344 #define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ 345 #define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ 346 #define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ 347 /* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */ 348 #define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 349 #define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ 350 #define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ 351 #define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ 352 /* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */ 353 #define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 354 #define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ 355 #define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ 356 #define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ 357 #define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ 358 #define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */ 359 /* PCM_REG0_DATA (0x10006000+0x100) */ 360 #define PCM_REG0_RF_LSB (1U << 0) /* 32b */ 361 /* PCM_REG2_DATA (0x10006000+0x104) */ 362 #define PCM_REG2_RF_LSB (1U << 0) /* 32b */ 363 /* PCM_REG6_DATA (0x10006000+0x108) */ 364 #define PCM_REG6_RF_LSB (1U << 0) /* 32b */ 365 /* PCM_REG7_DATA (0x10006000+0x10C) */ 366 #define PCM_REG7_RF_LSB (1U << 0) /* 32b */ 367 /* PCM_REG13_DATA (0x10006000+0x110) */ 368 #define PCM_REG13_RF_LSB (1U << 0) /* 32b */ 369 /* SRC_REQ_STA_0 (0x10006000+0x114) */ 370 #define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */ 371 #define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */ 372 #define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */ 373 #define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */ 374 #define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */ 375 #define MD_DDR_EN_0_LSB (1U << 5) /* 1b */ 376 #define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */ 377 #define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */ 378 #define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */ 379 #define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */ 380 #define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */ 381 #define MD_DDR_EN_1_LSB (1U << 11) /* 1b */ 382 #define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ 383 #define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ 384 #define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ 385 #define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ 386 #define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ 387 #define CONN_DDR_EN_LSB (1U << 17) /* 1b */ 388 #define SRCCLKENI_LSB (1U << 18) /* 3b */ 389 #define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */ 390 #define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */ 391 #define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */ 392 #define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */ 393 #define MD32_DDR_EN_LSB (1U << 25) /* 1b */ 394 #define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ 395 #define DISP0_DDR_EN_LSB (1U << 27) /* 1b */ 396 #define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ 397 #define DISP1_DDR_EN_LSB (1U << 29) /* 1b */ 398 #define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ 399 /* SRC_REQ_STA_1 (0x10006000+0x118) */ 400 #define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ 401 #define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ 402 #define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ 403 #define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ 404 #define SCP_DDR_EN_LSB (1U << 4) /* 1b */ 405 #define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ 406 #define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ 407 #define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ 408 #define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ 409 #define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */ 410 #define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ 411 #define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ 412 #define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ 413 #define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ 414 #define UFS_DDR_EN_LSB (1U << 14) /* 1b */ 415 #define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ 416 #define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ 417 #define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ 418 #define GCE_DDR_EN_LSB (1U << 18) /* 1b */ 419 #define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ 420 #define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */ 421 #define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ 422 #define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ 423 #define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ 424 #define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ 425 #define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */ 426 #define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ 427 #define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ 428 #define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ 429 #define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ 430 #define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */ 431 /* SRC_REQ_STA_2 (0x10006000+0x11C) */ 432 #define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ 433 #define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ 434 #define SW2SPM_INT_LSB (1U << 11) /* 4b */ 435 #define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ 436 #define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ 437 #define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ 438 #define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */ 439 #define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */ 440 #define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */ 441 #define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */ 442 #define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */ 443 #define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ 444 #define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ 445 #define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ 446 #define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ 447 #define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */ 448 /* PCM_TIMER_OUT (0x10006000+0x120) */ 449 #define PCM_TIMER_LSB (1U << 0) /* 32b */ 450 /* PCM_WDT_OUT (0x10006000+0x124) */ 451 #define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ 452 /* SPM_IRQ_STA (0x10006000+0x128) */ 453 #define TWAM_IRQ_LSB (1U << 2) /* 1b */ 454 #define PCM_IRQ_LSB (1U << 3) /* 1b */ 455 /* SRC_REQ_STA_4 (0x10006000+0x12C) */ 456 #define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ 457 #define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ 458 #define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ 459 #define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ 460 #define APU_DDR_EN_LSB (1U << 4) /* 1b */ 461 #define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ 462 #define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ 463 #define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ 464 #define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ 465 #define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */ 466 /* MD32PCM_WAKEUP_STA (0x10006000+0x130) */ 467 #define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ 468 /* MD32PCM_EVENT_STA (0x10006000+0x134) */ 469 #define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ 470 /* SPM_WAKEUP_STA (0x10006000+0x138) */ 471 #define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */ 472 #define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */ 473 /* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */ 474 #define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ 475 /* SPM_WAKEUP_MISC (0x10006000+0x140) */ 476 #define GIC_WAKEUP_LSB (1U << 0) /* 10b */ 477 #define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ 478 #define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ 479 #define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ 480 #define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ 481 #define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ 482 #define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */ 483 #define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */ 484 #define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */ 485 #define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ 486 #define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ 487 #define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ 488 #define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ 489 #define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ 490 #define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ 491 #define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ 492 /* MM_DVFS_HALT (0x10006000+0x144) */ 493 #define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ 494 /* BUS_PROTECT_RDY (0x10006000+0x150) */ 495 #define PROTECT_READY_LSB (1U << 0) /* 32b */ 496 /* BUS_PROTECT1_RDY (0x10006000+0x154) */ 497 #define PROTECT1_READY_LSB (1U << 0) /* 32b */ 498 /* BUS_PROTECT2_RDY (0x10006000+0x158) */ 499 #define PROTECT2_READY_LSB (1U << 0) /* 32b */ 500 /* BUS_PROTECT3_RDY (0x10006000+0x15C) */ 501 #define PROTECT3_READY_LSB (1U << 0) /* 32b */ 502 /* SUBSYS_IDLE_STA (0x10006000+0x160) */ 503 #define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ 504 /* PCM_STA (0x10006000+0x164) */ 505 #define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ 506 #define EXT_SRC_STA_LSB (1U << 4) /* 3b */ 507 /* SRC_REQ_STA_3 (0x10006000+0x168) */ 508 #define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */ 509 #define F26M_STATE_LSB (1U << 16) /* 1b */ 510 #define INFRA_STATE_LSB (1U << 17) /* 1b */ 511 #define APSRC_STATE_LSB (1U << 18) /* 1b */ 512 #define VRF18_STATE_LSB (1U << 19) /* 1b */ 513 #define DDR_EN_STATE_LSB (1U << 20) /* 1b */ 514 #define DVFS_STATE_LSB (1U << 21) /* 1b */ 515 #define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ 516 #define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ 517 #define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ 518 #define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ 519 /* PWR_STATUS (0x10006000+0x16C) */ 520 #define PWR_STATUS_LSB (1U << 0) /* 32b */ 521 /* PWR_STATUS_2ND (0x10006000+0x170) */ 522 #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 523 /* CPU_PWR_STATUS (0x10006000+0x174) */ 524 #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ 525 #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ 526 #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ 527 #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ 528 #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ 529 #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ 530 #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ 531 #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ 532 #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ 533 #define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ 534 /* OTHER_PWR_STATUS (0x10006000+0x178) */ 535 #define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ 536 /* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */ 537 #define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 538 #define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */ 539 /* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */ 540 #define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 541 #define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ 542 /* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */ 543 #define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 544 #define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ 545 /* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */ 546 #define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 547 #define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ 548 /* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */ 549 #define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 550 #define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ 551 /* MD32PCM_STA (0x10006000+0x190) */ 552 #define MD32PCM_HALT_LSB (1U << 0) /* 1b */ 553 #define MD32PCM_GATED_LSB (1U << 1) /* 1b */ 554 /* MD32PCM_PC (0x10006000+0x194) */ 555 #define MON_PC_LSB (1U << 0) /* 32b */ 556 /* DVFSRC_EVENT_STA (0x10006000+0x1A4) */ 557 #define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ 558 /* BUS_PROTECT4_RDY (0x10006000+0x1A8) */ 559 #define PROTECT4_READY_LSB (1U << 0) /* 32b */ 560 /* BUS_PROTECT5_RDY (0x10006000+0x1AC) */ 561 #define PROTECT5_READY_LSB (1U << 0) /* 32b */ 562 /* BUS_PROTECT6_RDY (0x10006000+0x1B0) */ 563 #define PROTECT6_READY_LSB (1U << 0) /* 32b */ 564 /* BUS_PROTECT7_RDY (0x10006000+0x1B4) */ 565 #define PROTECT7_READY_LSB (1U << 0) /* 32b */ 566 /* BUS_PROTECT8_RDY (0x10006000+0x1B8) */ 567 #define PROTECT8_READY_LSB (1U << 0) /* 32b */ 568 /* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */ 569 #define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 570 /* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */ 571 #define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 572 /* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */ 573 #define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 574 /* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */ 575 #define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 576 /* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */ 577 #define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 578 /* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */ 579 #define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 580 /* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */ 581 #define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 582 /* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */ 583 #define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 584 /* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */ 585 #define TWAM_TIMER_LSB (1U << 0) /* 32b */ 586 /* SPM_CG_CHECK_STA (0x10006000+0x1F4) */ 587 #define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ 588 #define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ 589 #define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ 590 /* SPM_DVFS_STA (0x10006000+0x1F8) */ 591 #define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 592 /* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */ 593 #define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ 594 #define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ 595 #define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ 596 /* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */ 597 #define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ 598 #define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ 599 #define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 600 #define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ 601 #define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ 602 #define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 603 #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ 604 /* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */ 605 #define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ 606 #define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ 607 #define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ 608 #define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ 609 #define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ 610 #define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 611 #define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ 612 #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ 613 /* SPM_CPU0_PWR_CON (0x10006000+0x208) */ 614 #define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ 615 #define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ 616 #define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ 617 #define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ 618 #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ 619 /* SPM_CPU1_PWR_CON (0x10006000+0x20C) */ 620 #define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ 621 #define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ 622 #define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ 623 #define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ 624 #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ 625 /* SPM_CPU2_PWR_CON (0x10006000+0x210) */ 626 #define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ 627 #define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ 628 #define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ 629 #define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ 630 #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ 631 /* SPM_CPU3_PWR_CON (0x10006000+0x214) */ 632 #define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ 633 #define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ 634 #define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ 635 #define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ 636 #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ 637 /* SPM_CPU4_PWR_CON (0x10006000+0x218) */ 638 #define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ 639 #define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ 640 #define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ 641 #define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ 642 #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ 643 /* SPM_CPU5_PWR_CON (0x10006000+0x21C) */ 644 #define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ 645 #define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ 646 #define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ 647 #define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ 648 #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ 649 /* SPM_CPU6_PWR_CON (0x10006000+0x220) */ 650 #define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ 651 #define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ 652 #define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ 653 #define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ 654 #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ 655 /* SPM_CPU7_PWR_CON (0x10006000+0x224) */ 656 #define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ 657 #define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ 658 #define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ 659 #define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ 660 #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ 661 /* ARMPLL_CLK_CON (0x10006000+0x22C) */ 662 #define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ 663 #define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ 664 #define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ 665 #define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ 666 #define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ 667 #define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ 668 #define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ 669 #define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ 670 #define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ 671 #define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ 672 #define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ 673 #define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ 674 #define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ 675 #define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ 676 #define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ 677 #define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ 678 #define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ 679 #define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ 680 #define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ 681 #define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ 682 /* MCUSYS_IDLE_STA (0x10006000+0x230) */ 683 #define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ 684 #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ 685 #define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ 686 #define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ 687 #define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ 688 #define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ 689 #define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ 690 #define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ 691 #define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ 692 #define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ 693 #define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ 694 #define WFI_AF_SEL_LSB (1U << 24) /* 8b */ 695 /* GIC_WAKEUP_STA (0x10006000+0x234) */ 696 #define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ 697 /* CPU_SPARE_CON (0x10006000+0x238) */ 698 #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ 699 /* CPU_SPARE_CON_SET (0x10006000+0x23C) */ 700 #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 701 /* CPU_SPARE_CON_CLR (0x10006000+0x240) */ 702 #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 703 /* ARMPLL_CLK_SEL (0x10006000+0x244) */ 704 #define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ 705 /* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */ 706 #define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ 707 /* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */ 708 #define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ 709 /* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */ 710 #define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ 711 /* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */ 712 #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 713 #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ 714 /* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */ 715 #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 716 #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ 717 /* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */ 718 #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 719 #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ 720 /* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */ 721 #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 722 #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ 723 /* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */ 724 #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 725 #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ 726 /* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */ 727 #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 728 #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ 729 /* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */ 730 #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 731 #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ 732 /* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */ 733 #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 734 #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ 735 /* MP0_CPU0_WFI_EN (0x10006000+0x280) */ 736 #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 737 /* MP0_CPU1_WFI_EN (0x10006000+0x284) */ 738 #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 739 /* MP0_CPU2_WFI_EN (0x10006000+0x288) */ 740 #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 741 /* MP0_CPU3_WFI_EN (0x10006000+0x28C) */ 742 #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 743 /* MP0_CPU4_WFI_EN (0x10006000+0x290) */ 744 #define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */ 745 /* MP0_CPU5_WFI_EN (0x10006000+0x294) */ 746 #define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */ 747 /* MP0_CPU6_WFI_EN (0x10006000+0x298) */ 748 #define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */ 749 /* MP0_CPU7_WFI_EN (0x10006000+0x29C) */ 750 #define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */ 751 /* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */ 752 #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ 753 /* ROOT_CORE_ADDR (0x10006000+0x2A4) */ 754 #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ 755 /* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */ 756 #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ 757 /* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */ 758 #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ 759 /* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */ 760 #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ 761 /* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */ 762 #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ 763 /* SW2SPM_INT (0x10006000+0x2E0) */ 764 #define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */ 765 /* SW2SPM_INT_SET (0x10006000+0x2E4) */ 766 #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ 767 /* SW2SPM_INT_CLR (0x10006000+0x2E8) */ 768 #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 769 /* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */ 770 #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 771 /* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */ 772 #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 773 /* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */ 774 #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 775 /* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */ 776 #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 777 /* SW2SPM_CFG (0x10006000+0x2FC) */ 778 #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 779 /* MD1_PWR_CON (0x10006000+0x300) */ 780 #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ 781 #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ 782 #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ 783 #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 784 #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 785 #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ 786 #define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 787 /* CONN_PWR_CON (0x10006000+0x304) */ 788 #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ 789 #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ 790 #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ 791 #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 792 #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 793 /* MFG0_PWR_CON (0x10006000+0x308) */ 794 #define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ 795 #define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ 796 #define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ 797 #define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 798 #define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 799 #define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ 800 #define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 801 /* MFG1_PWR_CON (0x10006000+0x30C) */ 802 #define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ 803 #define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ 804 #define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ 805 #define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 806 #define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 807 #define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ 808 #define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 809 /* MFG2_PWR_CON (0x10006000+0x310) */ 810 #define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ 811 #define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ 812 #define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ 813 #define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 814 #define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 815 #define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ 816 #define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 817 /* MFG3_PWR_CON (0x10006000+0x314) */ 818 #define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ 819 #define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ 820 #define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ 821 #define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 822 #define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 823 #define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ 824 #define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 825 /* MFG4_PWR_CON (0x10006000+0x318) */ 826 #define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ 827 #define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ 828 #define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ 829 #define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 830 #define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 831 #define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ 832 #define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 833 /* MFG5_PWR_CON (0x10006000+0x31C) */ 834 #define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ 835 #define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ 836 #define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ 837 #define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 838 #define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 839 #define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ 840 #define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 841 /* MFG6_PWR_CON (0x10006000+0x320) */ 842 #define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ 843 #define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ 844 #define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ 845 #define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 846 #define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 847 #define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ 848 #define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 849 /* IFR_PWR_CON (0x10006000+0x324) */ 850 #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ 851 #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ 852 #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ 853 #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 854 #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 855 #define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ 856 #define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 857 /* IFR_SUB_PWR_CON (0x10006000+0x328) */ 858 #define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ 859 #define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ 860 #define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ 861 #define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 862 #define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 863 #define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ 864 #define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 865 /* DPY_PWR_CON (0x10006000+0x32C) */ 866 #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ 867 #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ 868 #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ 869 #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 870 #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 871 #define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */ 872 #define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 873 /* ISP_PWR_CON (0x10006000+0x330) */ 874 #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ 875 #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ 876 #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ 877 #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 878 #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 879 #define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ 880 #define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 881 /* ISP2_PWR_CON (0x10006000+0x334) */ 882 #define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ 883 #define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ 884 #define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ 885 #define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 886 #define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 887 #define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ 888 #define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 889 /* IPE_PWR_CON (0x10006000+0x338) */ 890 #define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ 891 #define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ 892 #define IPE_PWR_ON_LSB (1U << 2) /* 1b */ 893 #define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 894 #define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 895 #define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ 896 #define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 897 /* VDE_PWR_CON (0x10006000+0x33C) */ 898 #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ 899 #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ 900 #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ 901 #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 902 #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 903 #define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ 904 #define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 905 /* VDE2_PWR_CON (0x10006000+0x340) */ 906 #define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ 907 #define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ 908 #define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ 909 #define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 910 #define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 911 #define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ 912 #define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 913 /* VEN_PWR_CON (0x10006000+0x344) */ 914 #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ 915 #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ 916 #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ 917 #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 918 #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 919 #define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ 920 #define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 921 /* VEN_CORE1_PWR_CON (0x10006000+0x348) */ 922 #define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 923 #define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 924 #define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 925 #define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 926 #define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 927 #define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ 928 #define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 929 /* MDP_PWR_CON (0x10006000+0x34C) */ 930 #define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ 931 #define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ 932 #define MDP_PWR_ON_LSB (1U << 2) /* 1b */ 933 #define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 934 #define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 935 #define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ 936 #define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 937 /* DIS_PWR_CON (0x10006000+0x350) */ 938 #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ 939 #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ 940 #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ 941 #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 942 #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 943 #define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ 944 #define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 945 /* AUDIO_PWR_CON (0x10006000+0x354) */ 946 #define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ 947 #define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ 948 #define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ 949 #define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 950 #define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 951 #define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ 952 #define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 953 /* ADSP_PWR_CON (0x10006000+0x358) */ 954 #define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ 955 #define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ 956 #define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ 957 #define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 958 #define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 959 #define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 960 #define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 961 #define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ 962 #define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 963 #define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 964 #define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 965 /* CAM_PWR_CON (0x10006000+0x35C) */ 966 #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ 967 #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ 968 #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ 969 #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 970 #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 971 #define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ 972 #define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 973 /* CAM_RAWA_PWR_CON (0x10006000+0x360) */ 974 #define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ 975 #define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ 976 #define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ 977 #define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 978 #define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 979 #define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ 980 #define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 981 /* CAM_RAWB_PWR_CON (0x10006000+0x364) */ 982 #define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ 983 #define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ 984 #define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ 985 #define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 986 #define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 987 #define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ 988 #define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 989 /* CAM_RAWC_PWR_CON (0x10006000+0x368) */ 990 #define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ 991 #define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ 992 #define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ 993 #define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 994 #define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 995 #define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ 996 #define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 997 /* SYSRAM_CON (0x10006000+0x36C) */ 998 #define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 999 #define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1000 #define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ 1001 #define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ 1002 /* SYSROM_CON (0x10006000+0x370) */ 1003 #define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */ 1004 /* SSPM_SRAM_CON (0x10006000+0x374) */ 1005 #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1006 #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1007 #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1008 #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ 1009 /* SCP_SRAM_CON (0x10006000+0x378) */ 1010 #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1011 #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1012 #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1013 #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ 1014 /* DPY_SHU_SRAM_CON (0x10006000+0x37C) */ 1015 #define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1016 #define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1017 #define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1018 #define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ 1019 /* UFS_SRAM_CON (0x10006000+0x380) */ 1020 #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1021 #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1022 #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1023 #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ 1024 /* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */ 1025 #define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1026 #define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1027 #define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1028 #define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1029 /* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */ 1030 #define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1031 #define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1032 #define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1033 #define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1034 /* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */ 1035 #define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1036 #define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1037 #define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1038 #define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */ 1039 /* USB_SRAM_CON (0x10006000+0x390) */ 1040 #define USB_SRAM_PDN_LSB (1U << 0) /* 7b */ 1041 /* DUMMY_SRAM_CON (0x10006000+0x394) */ 1042 #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1043 #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1044 #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1045 #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ 1046 /* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */ 1047 #define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1048 #define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1049 /* EXT_BUCK_ISO (0x10006000+0x39C) */ 1050 #define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1051 #define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1052 #define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ 1053 /* DXCC_SRAM_CON (0x10006000+0x3A0) */ 1054 #define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1055 #define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1056 #define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1057 #define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */ 1058 /* MSDC_SRAM_CON (0x10006000+0x3A4) */ 1059 #define MSDC_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1060 #define MSDC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1061 #define MSDC_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1062 #define MSDC_SRAM_PDN_LSB (1U << 16) /* 5b */ 1063 /* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */ 1064 #define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ 1065 /* DP_TX_PWR_CON (0x10006000+0x3AC) */ 1066 #define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ 1067 #define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ 1068 #define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ 1069 #define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1070 #define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1071 #define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ 1072 #define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1073 /* DPMAIF_SRAM_CON (0x10006000+0x3B0) */ 1074 #define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1075 #define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1076 #define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1077 #define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ 1078 /* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */ 1079 #define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1080 #define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1081 #define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1082 #define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */ 1083 /* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */ 1084 #define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1085 #define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1086 #define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1087 #define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */ 1088 /* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */ 1089 #define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1090 #define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1091 #define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1092 #define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */ 1093 /* MCUPM_SRAM_CON (0x10006000+0x3C0) */ 1094 #define MCUPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1095 #define MCUPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1096 #define MCUPM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1097 #define MCUPM_SRAM_PDN_LSB (1U << 16) /* 8b */ 1098 /* DPY2_PWR_CON (0x10006000+0x3C4) */ 1099 #define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1100 #define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ 1101 #define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ 1102 #define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1103 #define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1104 #define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1105 #define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1106 /* SPM_MEM_CK_SEL (0x10006000+0x400) */ 1107 #define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ 1108 #define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ 1109 /* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */ 1110 #define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ 1111 /* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */ 1112 #define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ 1113 /* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */ 1114 #define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ 1115 /* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */ 1116 #define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ 1117 /* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */ 1118 #define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ 1119 /* SPM_EMI_BW_MODE (0x10006000+0x418) */ 1120 #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ 1121 #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ 1122 #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ 1123 #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ 1124 /* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */ 1125 #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ 1126 /* ULPOSC_CON (0x10006000+0x420) */ 1127 #define ULPOSC_EN_LSB (1U << 0) /* 1b */ 1128 #define ULPOSC_RST_LSB (1U << 1) /* 1b */ 1129 #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ 1130 #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ 1131 /* SPM2MM_CON (0x10006000+0x424) */ 1132 #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ 1133 #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ 1134 #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ 1135 #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ 1136 #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ 1137 #define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ 1138 #define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ 1139 #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ 1140 #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ 1141 #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ 1142 /* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */ 1143 #define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ 1144 /* SPM2MCUPM_CON (0x10006000+0x42C) */ 1145 #define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ 1146 #define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ 1147 /* AP_MDSRC_REQ (0x10006000+0x430) */ 1148 #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ 1149 #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ 1150 #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ 1151 #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ 1152 #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ 1153 #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ 1154 /* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */ 1155 #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ 1156 /* SPM2MD_DVFS_CON (0x10006000+0x438) */ 1157 #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ 1158 /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ 1159 #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1160 /* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */ 1161 #define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ 1162 /* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */ 1163 #define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ 1164 /* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */ 1165 #define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ 1166 /* SPM_PLL_CON (0x10006000+0x44C) */ 1167 #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ 1168 #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ 1169 #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ 1170 #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ 1171 #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ 1172 #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ 1173 #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ 1174 #define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ 1175 #define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ 1176 #define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ 1177 /* CPU_DVFS_REQ (0x10006000+0x450) */ 1178 #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ 1179 /* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */ 1180 #define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ 1181 #define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ 1182 /* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */ 1183 #define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ 1184 /* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */ 1185 #define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ 1186 /* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */ 1187 #define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ 1188 /* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */ 1189 #define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ 1190 /* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */ 1191 #define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ 1192 #define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ 1193 /* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */ 1194 #define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ 1195 /* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */ 1196 #define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ 1197 /* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */ 1198 #define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ 1199 #define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ 1200 #define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ 1201 #define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ 1202 #define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ 1203 #define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ 1204 /* RELAY_DVFS_LEVEL (0x10006000+0x478) */ 1205 #define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1206 /* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */ 1207 #define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ 1208 #define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ 1209 #define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ 1210 #define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ 1211 #define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ 1212 #define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ 1213 #define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ 1214 #define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ 1215 #define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ 1216 #define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ 1217 #define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ 1218 #define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ 1219 #define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ 1220 #define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ 1221 #define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ 1222 /* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */ 1223 #define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ 1224 #define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ 1225 #define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ 1226 #define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ 1227 #define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ 1228 #define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ 1229 #define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ 1230 #define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ 1231 #define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ 1232 #define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ 1233 #define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ 1234 #define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ 1235 #define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ 1236 #define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ 1237 /* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */ 1238 #define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ 1239 #define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ 1240 #define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ 1241 #define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ 1242 #define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ 1243 #define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ 1244 #define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ 1245 #define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ 1246 #define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ 1247 #define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ 1248 #define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ 1249 /* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */ 1250 #define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ 1251 #define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ 1252 #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ 1253 #define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ 1254 #define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ 1255 #define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ 1256 #define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ 1257 #define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ 1258 /* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */ 1259 #define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ 1260 #define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ 1261 #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ 1262 #define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ 1263 #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ 1264 #define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ 1265 #define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ 1266 #define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ 1267 #define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ 1268 #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ 1269 #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ 1270 #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ 1271 #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ 1272 #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ 1273 #define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ 1274 /* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */ 1275 #define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ 1276 #define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ 1277 #define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ 1278 #define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ 1279 #define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ 1280 #define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ 1281 #define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ 1282 #define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ 1283 #define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ 1284 #define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ 1285 #define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ 1286 #define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ 1287 #define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ 1288 /* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */ 1289 #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ 1290 #define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ 1291 #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ 1292 #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ 1293 #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ 1294 #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ 1295 #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ 1296 #define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ 1297 #define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ 1298 #define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ 1299 #define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ 1300 /* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */ 1301 #define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ 1302 #define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ 1303 #define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ 1304 #define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ 1305 #define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ 1306 #define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ 1307 #define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ 1308 #define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ 1309 /* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */ 1310 #define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ 1311 #define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ 1312 #define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ 1313 #define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ 1314 #define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ 1315 #define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ 1316 #define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ 1317 #define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ 1318 #define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ 1319 #define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ 1320 #define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ 1321 #define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ 1322 #define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ 1323 #define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ 1324 #define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ 1325 #define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ 1326 #define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ 1327 #define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ 1328 #define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ 1329 #define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ 1330 #define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ 1331 #define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ 1332 /* SPM_DVFS_LEVEL (0x10006000+0x4A4) */ 1333 #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1334 /* SPM_CIRQ_CON (0x10006000+0x4A8) */ 1335 #define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ 1336 /* SPM_DVFS_MISC (0x10006000+0x4AC) */ 1337 #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ 1338 #define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ 1339 #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ 1340 #define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ 1341 #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ 1342 #define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ 1343 #define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ 1344 #define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ 1345 #define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ 1346 #define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ 1347 /* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */ 1348 #define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */ 1349 #define VS1_INIT_LSB (1U << 2) /* 1b */ 1350 #define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */ 1351 #define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */ 1352 #define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */ 1353 #define VS1_TRIGGER_LSB (1U << 9) /* 1b */ 1354 #define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */ 1355 #define VS2_INIT_LSB (1U << 13) /* 1b */ 1356 #define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */ 1357 #define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */ 1358 #define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */ 1359 #define VS2_TRIGGER_LSB (1U << 23) /* 1b */ 1360 #define VS1_FORCE_LSB (1U << 24) /* 1b */ 1361 #define VS2_FORCE_LSB (1U << 25) /* 1b */ 1362 #define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */ 1363 #define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */ 1364 /* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */ 1365 #define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1366 /* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */ 1367 #define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1368 /* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */ 1369 #define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1370 /* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */ 1371 #define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1372 /* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */ 1373 #define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1374 /* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */ 1375 #define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1376 /* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */ 1377 #define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1378 /* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */ 1379 #define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1380 /* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */ 1381 #define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1382 /* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */ 1383 #define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1384 /* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */ 1385 #define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1386 /* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */ 1387 #define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1388 /* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */ 1389 #define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1390 /* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */ 1391 #define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1392 /* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */ 1393 #define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1394 /* SPM_CG_CHECK_CON (0x10006000+0x4F0) */ 1395 #define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ 1396 #define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ 1397 #define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ 1398 #define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ 1399 #define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ 1400 #define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ 1401 #define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ 1402 #define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ 1403 #define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ 1404 /* SPM_SRC_RDY_STA (0x10006000+0x4F4) */ 1405 #define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ 1406 #define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ 1407 /* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */ 1408 #define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ 1409 #define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ 1410 /* SPM_FORCE_DVFS (0x10006000+0x4FC) */ 1411 #define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1412 /* SRCLKEN_RC_CFG (0x10006000+0x500) */ 1413 #define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */ 1414 /* RC_CENTRAL_CFG1 (0x10006000+0x504) */ 1415 #define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */ 1416 /* RC_CENTRAL_CFG2 (0x10006000+0x508) */ 1417 #define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */ 1418 /* RC_CMD_ARB_CFG (0x10006000+0x50C) */ 1419 #define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */ 1420 /* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */ 1421 #define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */ 1422 #define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */ 1423 /* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */ 1424 #define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */ 1425 #define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */ 1426 /* RC_DCXO_FPM_CFG (0x10006000+0x518) */ 1427 #define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */ 1428 /* RC_CENTRAL_CFG3 (0x10006000+0x51C) */ 1429 #define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */ 1430 /* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */ 1431 #define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1432 /* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */ 1433 #define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1434 /* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */ 1435 #define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1436 /* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */ 1437 #define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1438 /* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */ 1439 #define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1440 /* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */ 1441 #define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1442 /* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */ 1443 #define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1444 /* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */ 1445 #define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1446 /* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */ 1447 #define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1448 /* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */ 1449 #define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1450 /* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */ 1451 #define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1452 /* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */ 1453 #define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1454 /* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */ 1455 #define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 1456 /* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */ 1457 #define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */ 1458 /* RC_CENTRAL_CFG4 (0x10006000+0x558) */ 1459 #define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */ 1460 /* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */ 1461 #define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */ 1462 /* RC_DEBUG_CFG (0x10006000+0x564) */ 1463 #define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */ 1464 /* RC_MISC_0 (0x10006000+0x5B4) */ 1465 #define SRCCLKENO_LSB (1U << 0) /* 2b */ 1466 #define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */ 1467 #define RC_VREQ_LSB (1U << 5) /* 1b */ 1468 #define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */ 1469 /* RC_SPM_CTRL (0x10006000+0x448) */ 1470 #define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ 1471 #define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */ 1472 #define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ 1473 /* SUBSYS_INTF_CFG (0x10006000+0x5BC) */ 1474 #define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */ 1475 #define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */ 1476 /* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */ 1477 #define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */ 1478 /* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */ 1479 #define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */ 1480 /* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */ 1481 #define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */ 1482 /* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */ 1483 #define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */ 1484 /* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */ 1485 #define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */ 1486 /* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */ 1487 #define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */ 1488 /* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */ 1489 #define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */ 1490 /* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */ 1491 #define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */ 1492 /* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */ 1493 #define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */ 1494 /* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */ 1495 #define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */ 1496 /* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */ 1497 #define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */ 1498 /* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */ 1499 #define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */ 1500 /* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */ 1501 #define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */ 1502 /* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */ 1503 #define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */ 1504 /* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */ 1505 #define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */ 1506 /* SPM_SW_FLAG_0 (0x10006000+0x600) */ 1507 #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ 1508 /* SPM_SW_DEBUG_0 (0x10006000+0x604) */ 1509 #define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ 1510 /* SPM_SW_FLAG_1 (0x10006000+0x608) */ 1511 #define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ 1512 /* SPM_SW_DEBUG_1 (0x10006000+0x60C) */ 1513 #define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ 1514 /* SPM_SW_RSV_0 (0x10006000+0x610) */ 1515 #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ 1516 /* SPM_SW_RSV_1 (0x10006000+0x614) */ 1517 #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ 1518 /* SPM_SW_RSV_2 (0x10006000+0x618) */ 1519 #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ 1520 /* SPM_SW_RSV_3 (0x10006000+0x61C) */ 1521 #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ 1522 /* SPM_SW_RSV_4 (0x10006000+0x620) */ 1523 #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ 1524 /* SPM_SW_RSV_5 (0x10006000+0x624) */ 1525 #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ 1526 /* SPM_SW_RSV_6 (0x10006000+0x628) */ 1527 #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ 1528 /* SPM_SW_RSV_7 (0x10006000+0x62C) */ 1529 #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ 1530 /* SPM_SW_RSV_8 (0x10006000+0x630) */ 1531 #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ 1532 /* SPM_BK_WAKE_EVENT (0x10006000+0x634) */ 1533 #define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ 1534 /* SPM_BK_VTCXO_DUR (0x10006000+0x638) */ 1535 #define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ 1536 /* SPM_BK_WAKE_MISC (0x10006000+0x63C) */ 1537 #define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ 1538 /* SPM_BK_PCM_TIMER (0x10006000+0x640) */ 1539 #define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ 1540 /* SPM_RSV_CON_0 (0x10006000+0x650) */ 1541 #define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ 1542 /* SPM_RSV_CON_1 (0x10006000+0x654) */ 1543 #define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ 1544 /* SPM_RSV_STA_0 (0x10006000+0x658) */ 1545 #define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ 1546 /* SPM_RSV_STA_1 (0x10006000+0x65C) */ 1547 #define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ 1548 /* SPM_SPARE_CON (0x10006000+0x660) */ 1549 #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ 1550 /* SPM_SPARE_CON_SET (0x10006000+0x664) */ 1551 #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1552 /* SPM_SPARE_CON_CLR (0x10006000+0x668) */ 1553 #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1554 /* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */ 1555 #define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */ 1556 #define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */ 1557 /* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */ 1558 #define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */ 1559 #define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */ 1560 /* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */ 1561 #define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */ 1562 #define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */ 1563 /* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */ 1564 #define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */ 1565 #define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */ 1566 /* SCP_VCORE_LEVEL (0x10006000+0x67C) */ 1567 #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ 1568 /* SC_MM_CK_SEL_CON (0x10006000+0x680) */ 1569 #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ 1570 #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ 1571 /* SPARE_ACK_MASK (0x10006000+0x684) */ 1572 #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ 1573 /* SPM_DV_CON_0 (0x10006000+0x68C) */ 1574 #define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ 1575 /* SPM_DV_CON_1 (0x10006000+0x690) */ 1576 #define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ 1577 /* SPM_DV_STA (0x10006000+0x694) */ 1578 #define SPM_DV_STA_LSB (1U << 0) /* 32b */ 1579 /* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */ 1580 #define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ 1581 /* SPM_SEMA_M0 (0x10006000+0x69C) */ 1582 #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ 1583 /* SPM_SEMA_M1 (0x10006000+0x6A0) */ 1584 #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ 1585 /* SPM_SEMA_M2 (0x10006000+0x6A4) */ 1586 #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ 1587 /* SPM_SEMA_M3 (0x10006000+0x6A8) */ 1588 #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ 1589 /* SPM_SEMA_M4 (0x10006000+0x6AC) */ 1590 #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ 1591 /* SPM_SEMA_M5 (0x10006000+0x6B0) */ 1592 #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ 1593 /* SPM_SEMA_M6 (0x10006000+0x6B4) */ 1594 #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ 1595 /* SPM_SEMA_M7 (0x10006000+0x6B8) */ 1596 #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ 1597 /* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */ 1598 #define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ 1599 /* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */ 1600 #define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ 1601 /* SPM_ADSP_IRQ (0x10006000+0x6C4) */ 1602 #define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ 1603 #define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 1604 /* SPM_MD32_IRQ (0x10006000+0x6C8) */ 1605 #define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ 1606 #define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ 1607 /* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */ 1608 #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ 1609 /* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */ 1610 #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ 1611 /* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */ 1612 #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ 1613 /* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */ 1614 #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ 1615 /* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */ 1616 #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1617 /* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */ 1618 #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1619 /* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */ 1620 #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1621 /* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */ 1622 #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1623 /* UFS_PSRI_SW (0x10006000+0x6EC) */ 1624 #define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ 1625 /* UFS_PSRI_SW_SET (0x10006000+0x6F0) */ 1626 #define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ 1627 /* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */ 1628 #define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ 1629 /* SPM_AP_SEMA (0x10006000+0x6F8) */ 1630 #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ 1631 /* SPM_SPM_SEMA (0x10006000+0x6FC) */ 1632 #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ 1633 /* SPM_DVFS_CON (0x10006000+0x700) */ 1634 #define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1635 /* SPM_DVFS_CON_STA (0x10006000+0x704) */ 1636 #define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ 1637 /* SPM_PMIC_SPMI_CON (0x10006000+0x708) */ 1638 #define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ 1639 #define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ 1640 #define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ 1641 #define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ 1642 /* SPM_DVFS_CMD0 (0x10006000+0x710) */ 1643 #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ 1644 /* SPM_DVFS_CMD1 (0x10006000+0x714) */ 1645 #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ 1646 /* SPM_DVFS_CMD2 (0x10006000+0x718) */ 1647 #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ 1648 /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ 1649 #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ 1650 /* SPM_DVFS_CMD4 (0x10006000+0x720) */ 1651 #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ 1652 /* SPM_DVFS_CMD5 (0x10006000+0x724) */ 1653 #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ 1654 /* SPM_DVFS_CMD6 (0x10006000+0x728) */ 1655 #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ 1656 /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ 1657 #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ 1658 /* SPM_DVFS_CMD8 (0x10006000+0x730) */ 1659 #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ 1660 /* SPM_DVFS_CMD9 (0x10006000+0x734) */ 1661 #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ 1662 /* SPM_DVFS_CMD10 (0x10006000+0x738) */ 1663 #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ 1664 /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ 1665 #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ 1666 /* SPM_DVFS_CMD12 (0x10006000+0x740) */ 1667 #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ 1668 /* SPM_DVFS_CMD13 (0x10006000+0x744) */ 1669 #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ 1670 /* SPM_DVFS_CMD14 (0x10006000+0x748) */ 1671 #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ 1672 /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ 1673 #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ 1674 /* SPM_DVFS_CMD16 (0x10006000+0x750) */ 1675 #define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ 1676 /* SPM_DVFS_CMD17 (0x10006000+0x754) */ 1677 #define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ 1678 /* SPM_DVFS_CMD18 (0x10006000+0x758) */ 1679 #define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ 1680 /* SPM_DVFS_CMD19 (0x10006000+0x75C) */ 1681 #define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ 1682 /* SPM_DVFS_CMD20 (0x10006000+0x760) */ 1683 #define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ 1684 /* SPM_DVFS_CMD21 (0x10006000+0x764) */ 1685 #define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ 1686 /* SPM_DVFS_CMD22 (0x10006000+0x768) */ 1687 #define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ 1688 /* SPM_DVFS_CMD23 (0x10006000+0x76C) */ 1689 #define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ 1690 /* SYS_TIMER_VALUE_L (0x10006000+0x770) */ 1691 #define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ 1692 /* SYS_TIMER_VALUE_H (0x10006000+0x774) */ 1693 #define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ 1694 /* SYS_TIMER_START_L (0x10006000+0x778) */ 1695 #define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ 1696 /* SYS_TIMER_START_H (0x10006000+0x77C) */ 1697 #define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ 1698 /* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */ 1699 #define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 1700 /* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */ 1701 #define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 1702 /* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */ 1703 #define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 1704 /* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */ 1705 #define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 1706 /* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */ 1707 #define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 1708 /* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */ 1709 #define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 1710 /* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */ 1711 #define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 1712 /* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */ 1713 #define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 1714 /* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */ 1715 #define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 1716 /* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */ 1717 #define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 1718 /* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */ 1719 #define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 1720 /* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */ 1721 #define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 1722 /* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */ 1723 #define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 1724 /* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */ 1725 #define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 1726 /* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */ 1727 #define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 1728 /* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */ 1729 #define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 1730 /* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */ 1731 #define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ 1732 /* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */ 1733 #define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ 1734 /* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */ 1735 #define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ 1736 /* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */ 1737 #define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ 1738 /* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */ 1739 #define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ 1740 /* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */ 1741 #define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ 1742 /* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */ 1743 #define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ 1744 /* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */ 1745 #define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ 1746 /* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */ 1747 #define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ 1748 /* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */ 1749 #define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ 1750 /* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */ 1751 #define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ 1752 /* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */ 1753 #define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ 1754 /* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */ 1755 #define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ 1756 /* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */ 1757 #define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ 1758 /* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */ 1759 #define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ 1760 /* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */ 1761 #define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ 1762 /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ 1763 #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ 1764 /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ 1765 #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ 1766 /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ 1767 #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ 1768 /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ 1769 #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ 1770 /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ 1771 #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ 1772 /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ 1773 #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ 1774 /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ 1775 #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ 1776 /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ 1777 #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ 1778 /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ 1779 #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ 1780 /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ 1781 #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ 1782 /* PCM_WDT_LATCH_10 (0x10006000+0x828) */ 1783 #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ 1784 /* PCM_WDT_LATCH_11 (0x10006000+0x82C) */ 1785 #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ 1786 /* PCM_WDT_LATCH_12 (0x10006000+0x830) */ 1787 #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ 1788 /* PCM_WDT_LATCH_13 (0x10006000+0x834) */ 1789 #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ 1790 /* PCM_WDT_LATCH_14 (0x10006000+0x838) */ 1791 #define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ 1792 /* PCM_WDT_LATCH_15 (0x10006000+0x83C) */ 1793 #define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ 1794 /* PCM_WDT_LATCH_16 (0x10006000+0x840) */ 1795 #define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ 1796 /* PCM_WDT_LATCH_17 (0x10006000+0x844) */ 1797 #define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ 1798 /* PCM_WDT_LATCH_18 (0x10006000+0x848) */ 1799 #define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ 1800 /* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */ 1801 #define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 1802 /* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */ 1803 #define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ 1804 /* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */ 1805 #define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ 1806 /* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */ 1807 #define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ 1808 /* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */ 1809 #define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ 1810 /* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */ 1811 #define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ 1812 /* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */ 1813 #define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ 1814 /* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */ 1815 #define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ 1816 /* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */ 1817 #define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ 1818 /* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */ 1819 #define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ 1820 /* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */ 1821 #define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ 1822 /* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */ 1823 #define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ 1824 /* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */ 1825 #define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ 1826 /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */ 1827 #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 1828 /* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */ 1829 #define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ 1830 #define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ 1831 #define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ 1832 #define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ 1833 #define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ 1834 #define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ 1835 #define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ 1836 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ 1837 #define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ 1838 #define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ 1839 #define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ 1840 /* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */ 1841 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ 1842 #define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ 1843 /* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */ 1844 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ 1845 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ 1846 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ 1847 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ 1848 /* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */ 1849 #define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ 1850 #define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ 1851 /* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */ 1852 #define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ 1853 /* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */ 1854 #define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ 1855 /* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */ 1856 #define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ 1857 #define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ 1858 #define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ 1859 #define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ 1860 #define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ 1861 #define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ 1862 #define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ 1863 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ 1864 #define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ 1865 #define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ 1866 #define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ 1867 /* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */ 1868 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ 1869 #define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ 1870 /* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */ 1871 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ 1872 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ 1873 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ 1874 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ 1875 /* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */ 1876 #define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ 1877 #define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ 1878 /* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */ 1879 #define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ 1880 /* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */ 1881 #define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ 1882 /* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */ 1883 #define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ 1884 #define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ 1885 #define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ 1886 #define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ 1887 #define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ 1888 #define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ 1889 #define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ 1890 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ 1891 #define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ 1892 #define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ 1893 #define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ 1894 /* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */ 1895 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ 1896 #define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ 1897 /* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */ 1898 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ 1899 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ 1900 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ 1901 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ 1902 /* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */ 1903 #define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ 1904 #define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ 1905 /* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */ 1906 #define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ 1907 /* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */ 1908 #define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ 1909 /* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */ 1910 #define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ 1911 #define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ 1912 #define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ 1913 #define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ 1914 #define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ 1915 #define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ 1916 #define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ 1917 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ 1918 #define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ 1919 #define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ 1920 #define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ 1921 /* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */ 1922 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ 1923 #define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ 1924 /* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */ 1925 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ 1926 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ 1927 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ 1928 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ 1929 /* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */ 1930 #define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ 1931 #define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ 1932 /* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */ 1933 #define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ 1934 /* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */ 1935 #define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ 1936 /* SPM_COUNTER_0 (0x10006000+0x978) */ 1937 #define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ 1938 #define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ 1939 #define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ 1940 #define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ 1941 #define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ 1942 #define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ 1943 /* SPM_COUNTER_1 (0x10006000+0x97C) */ 1944 #define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ 1945 #define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ 1946 #define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ 1947 #define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ 1948 #define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ 1949 #define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ 1950 /* SPM_COUNTER_2 (0x10006000+0x980) */ 1951 #define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ 1952 #define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ 1953 #define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ 1954 #define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ 1955 #define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ 1956 #define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ 1957 /* SYS_TIMER_CON (0x10006000+0x98C) */ 1958 #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ 1959 #define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ 1960 #define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ 1961 #define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ 1962 /* RC_FSM_STA_0 (0x10006000+0xE00) */ 1963 #define RC_FSM_STA_0_LSB (1U << 0) /* 32b */ 1964 /* RC_CMD_STA_0 (0x10006000+0xE04) */ 1965 #define RC_CMD_STA_0_LSB (1U << 0) /* 32b */ 1966 /* RC_CMD_STA_1 (0x10006000+0xE08) */ 1967 #define RC_CMD_STA_1_LSB (1U << 0) /* 32b */ 1968 /* RC_SPI_STA_0 (0x10006000+0xE0C) */ 1969 #define RC_SPI_STA_0_LSB (1U << 0) /* 32b */ 1970 /* RC_PI_PO_STA_0 (0x10006000+0xE10) */ 1971 #define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */ 1972 /* RC_M00_REQ_STA_0 (0x10006000+0xE14) */ 1973 #define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */ 1974 /* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */ 1975 #define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */ 1976 /* RC_M02_REQ_STA_0 (0x10006000+0xE20) */ 1977 #define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */ 1978 /* RC_M03_REQ_STA_0 (0x10006000+0xE24) */ 1979 #define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */ 1980 /* RC_M04_REQ_STA_0 (0x10006000+0xE28) */ 1981 #define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */ 1982 /* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */ 1983 #define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */ 1984 /* RC_M06_REQ_STA_0 (0x10006000+0xE30) */ 1985 #define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */ 1986 /* RC_M07_REQ_STA_0 (0x10006000+0xE34) */ 1987 #define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */ 1988 /* RC_M08_REQ_STA_0 (0x10006000+0xE38) */ 1989 #define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */ 1990 /* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */ 1991 #define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */ 1992 /* RC_M10_REQ_STA_0 (0x10006000+0xE40) */ 1993 #define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */ 1994 /* RC_M11_REQ_STA_0 (0x10006000+0xE44) */ 1995 #define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */ 1996 /* RC_M12_REQ_STA_0 (0x10006000+0xE48) */ 1997 #define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */ 1998 /* RC_DEBUG_STA_0 (0x10006000+0xE4C) */ 1999 #define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */ 2000 /* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */ 2001 #define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */ 2002 /* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */ 2003 #define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */ 2004 /* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */ 2005 #define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */ 2006 /* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */ 2007 #define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */ 2008 /* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */ 2009 #define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */ 2010 /* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */ 2011 #define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */ 2012 /* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */ 2013 #define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */ 2014 /* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */ 2015 #define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */ 2016 /* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */ 2017 #define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */ 2018 /* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */ 2019 #define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */ 2020 /* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */ 2021 #define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */ 2022 /* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */ 2023 #define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */ 2024 /* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */ 2025 #define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */ 2026 /* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */ 2027 #define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */ 2028 /* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */ 2029 #define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */ 2030 /* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */ 2031 #define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */ 2032 /* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */ 2033 #define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 2034 /* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */ 2035 #define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 2036 /* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */ 2037 #define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 2038 /* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */ 2039 #define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 2040 /* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */ 2041 #define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 2042 /* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */ 2043 #define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 2044 /* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */ 2045 #define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 2046 /* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */ 2047 #define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 2048 /* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */ 2049 #define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 2050 /* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */ 2051 #define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 2052 /* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */ 2053 #define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 2054 /* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */ 2055 #define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 2056 /* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */ 2057 #define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 2058 /* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */ 2059 #define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 2060 /* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */ 2061 #define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 2062 /* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */ 2063 #define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 2064 /* PCM_WDT_LATCH_19 (0x10006000+0xED8) */ 2065 #define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */ 2066 /* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */ 2067 #define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */ 2068 /* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */ 2069 #define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */ 2070 /* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */ 2071 #define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */ 2072 /* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */ 2073 #define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */ 2074 /* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */ 2075 #define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */ 2076 /* PMSR_LAST_DAT (0x10006000+0xF00) */ 2077 #define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */ 2078 /* PMSR_LAST_CNT (0x10006000+0xF04) */ 2079 #define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */ 2080 #define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */ 2081 /* PMSR_LAST_ACK (0x10006000+0xF08) */ 2082 #define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */ 2083 /* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */ 2084 #define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */ 2085 #define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */ 2086 #define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */ 2087 #define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */ 2088 /* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */ 2089 #define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */ 2090 #define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */ 2091 #define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */ 2092 #define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */ 2093 /* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */ 2094 #define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */ 2095 #define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */ 2096 #define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */ 2097 #define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */ 2098 /* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */ 2099 #define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */ 2100 #define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */ 2101 #define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */ 2102 #define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */ 2103 /* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */ 2104 #define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */ 2105 #define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */ 2106 #define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */ 2107 #define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */ 2108 /* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */ 2109 #define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */ 2110 #define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */ 2111 #define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */ 2112 #define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */ 2113 /* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */ 2114 #define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */ 2115 #define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */ 2116 #define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */ 2117 #define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */ 2118 /* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */ 2119 #define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */ 2120 #define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */ 2121 #define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */ 2122 #define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */ 2123 /* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */ 2124 #define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */ 2125 #define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */ 2126 #define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */ 2127 #define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */ 2128 /* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */ 2129 #define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */ 2130 #define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */ 2131 #define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */ 2132 #define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */ 2133 /* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */ 2134 #define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */ 2135 #define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */ 2136 #define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */ 2137 #define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */ 2138 /* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */ 2139 #define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */ 2140 #define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */ 2141 #define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */ 2142 #define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */ 2143 /* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */ 2144 #define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */ 2145 /* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */ 2146 #define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */ 2147 /* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */ 2148 #define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */ 2149 /* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */ 2150 #define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */ 2151 #define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */ 2152 #define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */ 2153 #define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */ 2154 #define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */ 2155 #define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */ 2156 #define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */ 2157 #define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */ 2158 #define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */ 2159 #define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */ 2160 #define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */ 2161 #define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */ 2162 #define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */ 2163 #define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */ 2164 #define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */ 2165 #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */ 2166 #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */ 2167 #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */ 2168 #define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */ 2169 #define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */ 2170 #define PMSR_MODE_LSB (1U << 20) /* 2b */ 2171 #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */ 2172 #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */ 2173 #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */ 2174 /* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */ 2175 #define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */ 2176 /* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */ 2177 #define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */ 2178 /* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */ 2179 #define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */ 2180 /* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */ 2181 #define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */ 2182 /* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */ 2183 #define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */ 2184 /* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */ 2185 #define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */ 2186 #define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */ 2187 #define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */ 2188 /* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */ 2189 #define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */ 2190 #define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */ 2191 #define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */ 2192 #define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */ 2193 #define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */ 2194 #define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */ 2195 #define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */ 2196 #define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */ 2197 #define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */ 2198 #define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */ 2199 #define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */ 2200 #define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */ 2201 #define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */ 2202 #define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */ 2203 #define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */ 2204 #define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */ 2205 /* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */ 2206 #define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */ 2207 #define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */ 2208 #define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */ 2209 #define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */ 2210 #define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */ 2211 #define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */ 2212 #define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */ 2213 #define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */ 2214 #define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */ 2215 #define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */ 2216 #define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */ 2217 #define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */ 2218 #define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */ 2219 #define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */ 2220 #define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */ 2221 #define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */ 2222 /* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */ 2223 #define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */ 2224 #define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */ 2225 #define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */ 2226 #define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */ 2227 #define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */ 2228 #define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */ 2229 #define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */ 2230 #define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */ 2231 #define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */ 2232 #define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */ 2233 #define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */ 2234 #define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */ 2235 #define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */ 2236 #define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */ 2237 #define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */ 2238 #define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */ 2239 /* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */ 2240 #define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */ 2241 /* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */ 2242 #define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */ 2243 /* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */ 2244 #define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */ 2245 2246 #define SPM_PROJECT_CODE (0xb16) 2247 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2248 2249 #endif /* MT_SPM_REG_H */ 2250
