1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <arch_helpers.h>
9 #include <common/debug.h>
10 #include <drivers/mentor/mi2cv.h>
11 #include <lib/mmio.h>
12
13 #include <mv_ddr_if.h>
14 #include <mvebu_def.h>
15 #include <plat_marvell.h>
16
17 #define MVEBU_CP_MPP_CTRL37_OFFS 20
18 #define MVEBU_CP_MPP_CTRL38_OFFS 24
19 #define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
20 #define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
21
22 #define MVEBU_MPP_CTRL_MASK 0xf
23
24 /*
25 * This struct provides the DRAM training code with
26 * the appropriate board DRAM configuration
27 */
28 static struct mv_ddr_topology_map board_topology_map = {
29 /* Board with 1CS 8Gb x4 devices of Micron 2400T */
30 DEBUG_LEVEL_ERROR,
31 0x1, /* active interfaces */
32 /* cs_mask, mirror, dqs_swap, ck_swap X subphys */
33 { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */
34 {0x1, 0x0, 0, 0},
35 {0x1, 0x0, 0, 0},
36 {0x1, 0x0, 0, 0},
37 {0x1, 0x0, 0, 0},
38 {0x1, 0x0, 0, 0},
39 {0x1, 0x0, 0, 0},
40 {0x1, 0x0, 0, 0},
41 {0x1, 0x0, 0, 0} },
42 /* TODO: double check if the speed bin is 2400T */
43 SPEED_BIN_DDR_2400T, /* speed_bin */
44 MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
45 MV_DDR_DIE_CAP_8GBIT, /* die capacity */
46 MV_DDR_FREQ_SAR, /* frequency */
47 0, 0, /* cas_l, cas_wl */
48 MV_DDR_TEMP_LOW} }, /* temperature */
49 MV_DDR_64BIT_BUS_MASK, /* subphys mask */
50 MV_DDR_CFG_SPD, /* ddr configuration data source */
51 NOT_COMBINED, /* ddr twin-die combined*/
52 { {0} }, /* raw spd data */
53 {0}, /* timing parameters */
54 { /* electrical configuration */
55 { /* memory electrical configuration */
56 MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
57 {
58 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
59 MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
60 },
61 {
62 MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
63 MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
64 },
65 MV_DDR_DIC_RZQ_DIV7 /* dic */
66 },
67 { /* phy electrical configuration */
68 MV_DDR_OHM_30, /* data_drv_p */
69 MV_DDR_OHM_30, /* data_drv_n */
70 MV_DDR_OHM_30, /* ctrl_drv_p */
71 MV_DDR_OHM_30, /* ctrl_drv_n */
72 {
73 MV_DDR_OHM_60, /* odt_p 1cs */
74 MV_DDR_OHM_120 /* odt_p 2cs */
75 },
76 {
77 MV_DDR_OHM_60, /* odt_n 1cs */
78 MV_DDR_OHM_120 /* odt_n 2cs */
79 },
80 },
81 { /* mac electrical configuration */
82 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
83 MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
84 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
85 },
86 }
87 };
88
mv_ddr_topology_map_get(void)89 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
90 {
91 /* Return the board topology as defined in the board code */
92 return &board_topology_map;
93 }
94
mpp_config(void)95 static void mpp_config(void)
96 {
97 uint32_t val;
98 uintptr_t reg = MVEBU_CP_MPP_REGS(0, 4);
99
100 /* configure CP0 MPP 37 and 38 to i2c */
101 val = mmio_read_32(reg);
102 val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
103 (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
104 val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << MVEBU_CP_MPP_CTRL37_OFFS) |
105 (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << MVEBU_CP_MPP_CTRL38_OFFS);
106 mmio_write_32(reg, val);
107 }
108
109 /*
110 * This function may modify the default DRAM parameters
111 * based on information received from SPD or bootloader
112 * configuration located on non volatile storage
113 */
plat_marvell_dram_update_topology(void)114 void plat_marvell_dram_update_topology(void)
115 {
116 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
117
118 INFO("Gathering DRAM information\n");
119
120 if (tm->cfg_src == MV_DDR_CFG_SPD) {
121 /* configure MPPs to enable i2c */
122 mpp_config();
123 /* initialize the i2c */
124 i2c_init((void *)MVEBU_CP0_I2C_BASE);
125 /* select SPD memory page 0 to access DRAM configuration */
126 i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
127 /* read data from spd */
128 i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
129 sizeof(tm->spd_data.all_bytes));
130 }
131 }
132
