1 /*
2  * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <arch_helpers.h>
9 #include <drivers/delay_timer.h>
10 #include <lib/mmio.h>
11 #include "socfpga_plat_def.h"
12 
13 
14 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
15 #include "agilex_clock_manager.h"
16 #elif PLATFORM_MODEL == PLAT_SOCFPGA_N5X
17 #include "n5x_clock_manager.h"
18 #elif PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
19 #include "s10_clock_manager.h"
20 #endif
21 
22 #define SOCFPGA_GLOBAL_TIMER		0xffd01000
23 #define SOCFPGA_GLOBAL_TIMER_EN		0x3
24 
25 static timer_ops_t plat_timer_ops;
26 /********************************************************************
27  * The timer delay function
28  ********************************************************************/
socfpga_get_timer_value(void)29 static uint32_t socfpga_get_timer_value(void)
30 {
31 	/*
32 	 * Generic delay timer implementation expects the timer to be a down
33 	 * counter. We apply bitwise NOT operator to the tick values returned
34 	 * by read_cntpct_el0() to simulate the down counter. The value is
35 	 * clipped from 64 to 32 bits.
36 	 */
37 	return (uint32_t)(~read_cntpct_el0());
38 }
39 
socfpga_delay_timer_init_args(void)40 void socfpga_delay_timer_init_args(void)
41 {
42 	plat_timer_ops.get_timer_value	= socfpga_get_timer_value;
43 	plat_timer_ops.clk_mult		= 1;
44 	plat_timer_ops.clk_div		= PLAT_SYS_COUNTER_FREQ_IN_MHZ;
45 
46 	timer_init(&plat_timer_ops);
47 
48 }
49 
socfpga_delay_timer_init(void)50 void socfpga_delay_timer_init(void)
51 {
52 	socfpga_delay_timer_init_args();
53 	mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
54 
55 	NOTICE("BL31 CLK freq = %d MHz\n", PLAT_SYS_COUNTER_FREQ_IN_MHZ);
56 
57 	asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
58 	asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
59 
60 }
61