1 /*
2 * Copyright 2019-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <context.h>
14 #include <drivers/arm/tzc380.h>
15 #include <drivers/console.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21
22 #include <dram.h>
23 #include <gpc.h>
24 #include <imx_aipstz.h>
25 #include <imx_uart.h>
26 #include <imx_rdc.h>
27 #include <imx8m_caam.h>
28 #include <imx8m_ccm.h>
29 #include <imx8m_csu.h>
30 #include <imx8m_snvs.h>
31 #include <platform_def.h>
32 #include <plat_imx8.h>
33
34 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
35
36 static const mmap_region_t imx_mmap[] = {
37 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP,
38 CAAM_RAM_MAP, NS_OCRAM_MAP, ROM_MAP, DRAM_MAP,
39 {0},
40 };
41
42 static const struct aipstz_cfg aipstz[] = {
43 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
44 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
45 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
46 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
47 {0},
48 };
49
50 static const struct imx_rdc_cfg rdc[] = {
51 /* Master domain assignment */
52 RDC_MDAn(RDC_MDA_M7, DID1),
53
54 /* peripherals domain permission */
55 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
56 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
57
58 /* memory region */
59 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff),
60 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff),
61 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff),
62
63 /* Sentinel */
64 {0},
65 };
66
67 static const struct imx_csu_cfg csu_cfg[] = {
68 /* peripherals csl setting */
69 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED),
70 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED),
71
72 /* master HP0~1 */
73
74 /* SA setting */
75
76 /* HP control setting */
77
78 /* Sentinel */
79 {0}
80 };
81
82
83 static entry_point_info_t bl32_image_ep_info;
84 static entry_point_info_t bl33_image_ep_info;
85
86 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)87 static uint32_t get_spsr_for_bl33_entry(void)
88 {
89 unsigned long el_status;
90 unsigned long mode;
91 uint32_t spsr;
92
93 /* figure out what mode we enter the non-secure world */
94 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
95 el_status &= ID_AA64PFR0_ELX_MASK;
96
97 mode = (el_status) ? MODE_EL2 : MODE_EL1;
98
99 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
100 return spsr;
101 }
102
bl31_tzc380_setup(void)103 static void bl31_tzc380_setup(void)
104 {
105 unsigned int val;
106
107 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
108 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
109 return;
110
111 tzc380_init(IMX_TZASC_BASE);
112
113 /*
114 * Need to substact offset 0x40000000 from CPU address when
115 * programming tzasc region for i.mx8mn.
116 */
117
118 /* Enable 1G-5G S/NS RW */
119 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
120 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
121 }
122
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)123 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
124 u_register_t arg2, u_register_t arg3)
125 {
126 unsigned int console_base = IMX_BOOT_UART_BASE;
127 static console_t console;
128 unsigned int val;
129 int i;
130
131 /* Enable CSU NS access permission */
132 for (i = 0; i < 64; i++) {
133 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
134 }
135
136 imx_aipstz_init(aipstz);
137
138 imx_rdc_init(rdc);
139
140 imx_csu_init(csu_cfg);
141
142 /*
143 * Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes
144 * partial write issue. The AXI2AHB bridge is used for masters that access the TCM
145 * through system bus. Please refer to errata ERR050362 for more information.
146 */
147 mmio_setbits_32((GPV5_BASE_ADDR + FORCE_INCR_OFFSET), FORCE_INCR_BIT_MASK);
148
149 /* config the ocram memory range for secure access */
150 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1);
151 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
152 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
153
154 if (console_base == 0U) {
155 console_base = imx8m_uart_get_base();
156 }
157
158 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
159 IMX_CONSOLE_BAUDRATE, &console);
160 /* This console is only used for boot stage */
161 console_set_scope(&console, CONSOLE_FLAG_BOOT);
162
163 imx8m_caam_init();
164
165 /*
166 * tell BL3-1 where the non-secure software image is located
167 * and the entry state information.
168 */
169 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
170 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
171 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
172
173 #if defined(SPD_opteed) || defined(SPD_trusty)
174 /* Populate entry point information for BL32 */
175 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
176 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
177 bl32_image_ep_info.pc = BL32_BASE;
178 bl32_image_ep_info.spsr = 0;
179
180 /* Pass TEE base and size to bl33 */
181 bl33_image_ep_info.args.arg1 = BL32_BASE;
182 bl33_image_ep_info.args.arg2 = BL32_SIZE;
183
184 #ifdef SPD_trusty
185 bl32_image_ep_info.args.arg0 = BL32_SIZE;
186 bl32_image_ep_info.args.arg1 = BL32_BASE;
187 #else
188 /* Make sure memory is clean */
189 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
190 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
191 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
192 #endif
193 #endif
194
195 #if !defined(SPD_opteed) && !defined(SPD_trusty)
196 enable_snvs_privileged_access();
197 #endif
198
199 bl31_tzc380_setup();
200 }
201
202 #define MAP_BL31_TOTAL \
203 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
204 #define MAP_BL31_RO \
205 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
206 #define MAP_COHERENT_MEM \
207 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
208 MT_DEVICE | MT_RW | MT_SECURE)
209 #define MAP_BL32_TOTAL \
210 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW)
211
bl31_plat_arch_setup(void)212 void bl31_plat_arch_setup(void)
213 {
214 const mmap_region_t bl_regions[] = {
215 MAP_BL31_TOTAL,
216 MAP_BL31_RO,
217 #if USE_COHERENT_MEM
218 MAP_COHERENT_MEM,
219 #endif
220 #if defined(SPD_opteed) || defined(SPD_trusty)
221 /* Map TEE memory */
222 MAP_BL32_TOTAL,
223 #endif
224 {0}
225 };
226
227 setup_page_tables(bl_regions, imx_mmap);
228 enable_mmu_el3(0);
229 }
230
bl31_platform_setup(void)231 void bl31_platform_setup(void)
232 {
233 generic_delay_timer_init();
234
235 /* select the CKIL source to 32K OSC */
236 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
237
238 /* Init the dram info */
239 dram_info_init(SAVED_DRAM_TIMING_BASE);
240
241 plat_gic_driver_init();
242 plat_gic_init();
243
244 imx_gpc_init();
245 }
246
bl31_plat_get_next_image_ep_info(unsigned int type)247 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
248 {
249 if (type == NON_SECURE)
250 return &bl33_image_ep_info;
251 if (type == SECURE)
252 return &bl32_image_ep_info;
253
254 return NULL;
255 }
256
plat_get_syscnt_freq2(void)257 unsigned int plat_get_syscnt_freq2(void)
258 {
259 return COUNTER_FREQUENCY;
260 }
261
262 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)263 void plat_trusty_set_boot_args(aapcs64_params_t *args)
264 {
265 args->arg0 = BL32_SIZE;
266 args->arg1 = BL32_BASE;
267 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
268 }
269 #endif
270
