1 /*
2 * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <drivers/generic_delay_timer.h>
10 #include <drivers/partition/partition.h>
11 #include <plat/arm/common/plat_arm.h>
12 #include <plat/common/platform.h>
13 #include <platform_def.h>
14
15 #pragma weak bl2_el3_early_platform_setup
16 #pragma weak bl2_el3_plat_arch_setup
17 #pragma weak bl2_el3_plat_prepare_exit
18
19 #define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \
20 bl2_el3_tzram_layout.total_base, \
21 bl2_el3_tzram_layout.total_size, \
22 MT_MEMORY | MT_RW | MT_SECURE)
23
24 static meminfo_t bl2_el3_tzram_layout;
25
26 /*
27 * Perform arm specific early platform setup. At this moment we only initialize
28 * the console and the memory layout.
29 */
arm_bl2_el3_early_platform_setup(void)30 void arm_bl2_el3_early_platform_setup(void)
31 {
32 /* Initialize the console to provide early debug support */
33 arm_console_boot_init();
34
35 /*
36 * Allow BL2 to see the whole Trusted RAM. This is determined
37 * statically since we cannot rely on BL1 passing this information
38 * in the RESET_TO_BL2 case.
39 */
40 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
41 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
42
43 /* Initialise the IO layer and register platform IO devices */
44 plat_arm_io_setup();
45 }
46
bl2_el3_early_platform_setup(u_register_t arg0 __unused,u_register_t arg1 __unused,u_register_t arg2 __unused,u_register_t arg3 __unused)47 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
48 u_register_t arg1 __unused,
49 u_register_t arg2 __unused,
50 u_register_t arg3 __unused)
51 {
52 arm_bl2_el3_early_platform_setup();
53
54 /*
55 * Initialize Interconnect for this cluster during cold boot.
56 * No need for locks as no other CPU is active.
57 */
58 plat_arm_interconnect_init();
59 /*
60 * Enable Interconnect coherency for the primary CPU's cluster.
61 */
62 plat_arm_interconnect_enter_coherency();
63
64 generic_delay_timer_init();
65 }
66
67 /*******************************************************************************
68 * Perform the very early platform specific architectural setup here. At the
69 * moment this is only initializes the mmu in a quick and dirty way.
70 ******************************************************************************/
arm_bl2_el3_plat_arch_setup(void)71 void arm_bl2_el3_plat_arch_setup(void)
72 {
73
74 #if USE_COHERENT_MEM
75 /* Ensure ARM platforms dont use coherent memory
76 * in RESET_TO_BL2
77 */
78 assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U);
79 #endif
80
81 const mmap_region_t bl_regions[] = {
82 MAP_BL2_EL3_TOTAL,
83 ARM_MAP_BL_RO,
84 {0}
85 };
86
87 setup_page_tables(bl_regions, plat_arm_get_mmap());
88
89 #ifdef __aarch64__
90 enable_mmu_el3(0);
91 #else
92 enable_mmu_svc_mon(0);
93 #endif
94 }
95
bl2_el3_plat_arch_setup(void)96 void bl2_el3_plat_arch_setup(void)
97 {
98 int __maybe_unused ret;
99 arm_bl2_el3_plat_arch_setup();
100 #if ARM_GPT_SUPPORT
101 ret = gpt_partition_init();
102 if (ret != 0) {
103 ERROR("GPT partition initialisation failed!\n");
104 panic();
105 }
106 #endif /* ARM_GPT_SUPPORT */
107 }
108
bl2_el3_plat_prepare_exit(void)109 void bl2_el3_plat_prepare_exit(void)
110 {
111 }
112
