1 /*
2 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <plat/arm/common/plat_arm.h>
9 #include <platform_def.h>
10
11 #define RDN2_TZC_CPER_REGION \
12 {CSS_SGI_SP_CPER_BUF_BASE, (CSS_SGI_SP_CPER_BUF_BASE + \
13 CSS_SGI_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
14 PLAT_ARM_TZC_NS_DEV_ACCESS}
15
16 static const arm_tzc_regions_info_t tzc_regions[] = {
17 ARM_TZC_REGIONS_DEF,
18 #if ENABLE_FEAT_RAS && FFH_SUPPORT
19 RDN2_TZC_CPER_REGION,
20 #endif
21 {}
22 };
23
24 #if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
25 static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
26 {
27 /* TZC memory regions for second chip */
28 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
29 {}
30 },
31 #if CSS_SGI_CHIP_COUNT > 2
32 {
33 /* TZC memory regions for third chip */
34 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
35 {}
36 },
37 #endif
38 #if CSS_SGI_CHIP_COUNT > 3
39 {
40 /* TZC memory regions for fourth chip */
41 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
42 {}
43 },
44 #endif
45 };
46 #endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */
47
48 /* Initialize the secure environment */
plat_arm_security_setup(void)49 void plat_arm_security_setup(void)
50 {
51 unsigned int i;
52
53 INFO("Configuring TrustZone Controller for Chip 0\n");
54
55 for (i = 0; i < TZC400_COUNT; i++) {
56 arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
57 }
58
59 #if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
60 unsigned int j;
61
62 for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
63 INFO("Configuring TrustZone Controller for Chip %u\n", i);
64
65 for (j = 0; j < TZC400_COUNT; j++) {
66 arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
67 + TZC400_BASE(j), tzc_regions_mc[i-1]);
68 }
69 }
70 #endif
71 }
72
