1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 35# progbits limit. We need a way to build all useful configurations while waiting 36# on the fvp to increase its SRAM size. The problem is twofild: 37# 1. the cleanup that introduced these enables cleaned up tf-a a little too 38# well and things that previously (incorrectly) were enabled, no longer are. 39# A bunch of CI configs build subtly incorrectly and this combo makes it 40# necessary to forcefully and unconditionally enable them here. 41# 2. the progbits limit is exceeded only when the tsp is involved. However, 42# there are tsp CI configs that run on very high architecture revisions so 43# disabling everything isn't an option. 44# The fix is to enable everything, as before. When the tsp is included, though, 45# we need to slim the size down. In that case, disable all optional features, 46# that will not be present in CI when the tsp is. 47# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 48# for it. 49# TODO: make all of this unconditional (or only base the condition on 50# ARM_ARCH_* when the makefile supports it). 51ifneq (${DRTM_SUPPORT}, 1) 52ifneq (${SPD}, tspd) 53 ENABLE_FEAT_AMU := 2 54 ENABLE_FEAT_AMUv1p1 := 2 55 ENABLE_FEAT_HCX := 2 56 ENABLE_FEAT_RNG := 2 57 ENABLE_FEAT_TWED := 2 58 ENABLE_FEAT_GCS := 2 59ifeq (${ARCH}, aarch64) 60ifneq (${SPD}, spmd) 61ifeq (${SPM_MM}, 0) 62ifeq (${CTX_INCLUDE_FPREGS}, 0) 63 ENABLE_SME_FOR_NS := 2 64 ENABLE_SME2_FOR_NS := 2 65endif 66endif 67endif 68endif 69endif 70 71# enable unconditionally for all builds 72ifeq (${ARCH}, aarch64) 73 ENABLE_BRBE_FOR_NS := 2 74 ENABLE_TRBE_FOR_NS := 2 75endif 76ENABLE_SYS_REG_TRACE_FOR_NS := 2 77ENABLE_FEAT_CSV2_2 := 2 78ENABLE_FEAT_DIT := 2 79ENABLE_FEAT_PAN := 2 80ENABLE_FEAT_MTE_PERM := 2 81ENABLE_FEAT_VHE := 2 82CTX_INCLUDE_NEVE_REGS := 2 83ENABLE_FEAT_SEL2 := 2 84ENABLE_TRF_FOR_NS := 2 85ENABLE_FEAT_ECV := 2 86ENABLE_FEAT_FGT := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92endif 93 94# The FVP platform depends on this macro to build with correct GIC driver. 95$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 96 97# Pass FVP_CLUSTER_COUNT to the build system. 98$(eval $(call add_define,FVP_CLUSTER_COUNT)) 99 100# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 101$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 102 103# Pass FVP_MAX_PE_PER_CPU to the build system. 104$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 105 106# Pass FVP_GICR_REGION_PROTECTION to the build system. 107$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 108 109# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 110$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 111 112# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 113# choose the CCI driver , else the CCN driver 114ifeq ($(FVP_CLUSTER_COUNT), 0) 115$(error "Incorrect cluster count specified for FVP port") 116else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 117FVP_INTERCONNECT_DRIVER := FVP_CCI 118else 119FVP_INTERCONNECT_DRIVER := FVP_CCN 120endif 121 122$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 123 124# Choose the GIC sources depending upon the how the FVP will be invoked 125ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 126 127# The GIC model (GIC-600 or GIC-500) will be detected at runtime 128GICV3_SUPPORT_GIC600 := 1 129GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 130 131# Include GICv3 driver files 132include drivers/arm/gic/v3/gicv3.mk 133 134FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 135 plat/common/plat_gicv3.c \ 136 plat/arm/common/arm_gicv3.c 137 138 ifeq ($(filter 1,${RESET_TO_BL2} \ 139 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 140 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 141 endif 142 143else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 144 145# No GICv4 extension 146GIC_ENABLE_V4_EXTN := 0 147$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 148 149# Include GICv2 driver files 150include drivers/arm/gic/v2/gicv2.mk 151 152FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 153 plat/common/plat_gicv2.c \ 154 plat/arm/common/arm_gicv2.c 155 156FVP_DT_PREFIX := fvp-base-gicv2-psci 157else 158$(error "Incorrect GIC driver chosen on FVP port") 159endif 160 161ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 162FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 163else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 164FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 165 plat/arm/common/arm_ccn.c 166else 167$(error "Incorrect CCN driver chosen on FVP port") 168endif 169 170FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 171 plat/arm/board/fvp/fvp_security.c \ 172 plat/arm/common/arm_tzc400.c 173 174 175PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 176 -Iinclude/lib/psa 177 178 179PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 180 181FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 182 183ifeq (${ARCH}, aarch64) 184 185# select a different set of CPU files, depending on whether we compile for 186# hardware assisted coherency cores or not 187ifeq (${HW_ASSISTED_COHERENCY}, 0) 188# Cores used without DSU 189 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 190 lib/cpus/aarch64/cortex_a53.S \ 191 lib/cpus/aarch64/cortex_a57.S \ 192 lib/cpus/aarch64/cortex_a72.S \ 193 lib/cpus/aarch64/cortex_a73.S 194else 195# Cores used with DSU only 196 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 197 # AArch64-only cores 198 # TODO: add all cores to the appropriate lists 199 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 200 lib/cpus/aarch64/cortex_a65ae.S \ 201 lib/cpus/aarch64/cortex_a76.S \ 202 lib/cpus/aarch64/cortex_a76ae.S \ 203 lib/cpus/aarch64/cortex_a77.S \ 204 lib/cpus/aarch64/cortex_a78.S \ 205 lib/cpus/aarch64/cortex_a78_ae.S \ 206 lib/cpus/aarch64/cortex_a78c.S \ 207 lib/cpus/aarch64/cortex_a710.S \ 208 lib/cpus/aarch64/cortex_a715.S \ 209 lib/cpus/aarch64/cortex_a720.S \ 210 lib/cpus/aarch64/neoverse_n_common.S \ 211 lib/cpus/aarch64/neoverse_n1.S \ 212 lib/cpus/aarch64/neoverse_n2.S \ 213 lib/cpus/aarch64/neoverse_v1.S \ 214 lib/cpus/aarch64/neoverse_e1.S \ 215 lib/cpus/aarch64/cortex_x2.S \ 216 lib/cpus/aarch64/cortex_x4.S \ 217 lib/cpus/aarch64/cortex_gelas.S \ 218 lib/cpus/aarch64/nevis.S \ 219 lib/cpus/aarch64/travis.S 220 endif 221 # AArch64/AArch32 cores 222 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 223 lib/cpus/aarch64/cortex_a75.S 224endif 225 226else 227FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 228 lib/cpus/aarch32/cortex_a57.S \ 229 lib/cpus/aarch32/cortex_a53.S 230endif 231 232BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 233 drivers/arm/sp805/sp805.c \ 234 drivers/delay_timer/delay_timer.c \ 235 drivers/io/io_semihosting.c \ 236 lib/semihosting/semihosting.c \ 237 lib/semihosting/${ARCH}/semihosting_call.S \ 238 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 239 plat/arm/board/fvp/fvp_bl1_setup.c \ 240 plat/arm/board/fvp/fvp_err.c \ 241 plat/arm/board/fvp/fvp_io_storage.c \ 242 ${FVP_CPU_LIBS} \ 243 ${FVP_INTERCONNECT_SOURCES} 244 245ifeq (${USE_SP804_TIMER},1) 246BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 247else 248BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 249endif 250 251 252BL2_SOURCES += drivers/arm/sp805/sp805.c \ 253 drivers/io/io_semihosting.c \ 254 lib/utils/mem_region.c \ 255 lib/semihosting/semihosting.c \ 256 lib/semihosting/${ARCH}/semihosting_call.S \ 257 plat/arm/board/fvp/fvp_bl2_setup.c \ 258 plat/arm/board/fvp/fvp_err.c \ 259 plat/arm/board/fvp/fvp_io_storage.c \ 260 plat/arm/common/arm_nor_psci_mem_protect.c \ 261 ${FVP_SECURITY_SOURCES} 262 263 264ifeq (${COT_DESC_IN_DTB},1) 265BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 266endif 267 268ifeq (${ENABLE_RME},1) 269BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 270 271BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 272 plat/arm/board/fvp/fvp_realm_attest_key.c 273endif 274 275ifeq (${ENABLE_FEAT_RNG_TRAP},1) 276BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 277endif 278 279ifeq (${RESET_TO_BL2},1) 280BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 281 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 282 ${FVP_CPU_LIBS} \ 283 ${FVP_INTERCONNECT_SOURCES} 284endif 285 286ifeq (${USE_SP804_TIMER},1) 287BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 288endif 289 290BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 291 ${FVP_SECURITY_SOURCES} 292 293ifeq (${USE_SP804_TIMER},1) 294BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 295endif 296 297BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 298 drivers/arm/smmu/smmu_v3.c \ 299 drivers/delay_timer/delay_timer.c \ 300 drivers/cfi/v2m/v2m_flash.c \ 301 lib/utils/mem_region.c \ 302 plat/arm/board/fvp/fvp_bl31_setup.c \ 303 plat/arm/board/fvp/fvp_console.c \ 304 plat/arm/board/fvp/fvp_pm.c \ 305 plat/arm/board/fvp/fvp_topology.c \ 306 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 307 plat/arm/common/arm_nor_psci_mem_protect.c \ 308 ${FVP_CPU_LIBS} \ 309 ${FVP_GIC_SOURCES} \ 310 ${FVP_INTERCONNECT_SOURCES} \ 311 ${FVP_SECURITY_SOURCES} 312 313# Support for fconf in BL31 314# Added separately from the above list for better readability 315ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 316BL31_SOURCES += lib/fconf/fconf.c \ 317 lib/fconf/fconf_dyn_cfg_getter.c \ 318 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 319 320BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 321 322ifeq (${SEC_INT_DESC_IN_FCONF},1) 323BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 324endif 325 326endif 327 328ifeq (${USE_SP804_TIMER},1) 329BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 330else 331BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 332endif 333 334# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 335ifdef UNIX_MK 336FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 337FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 338 ${PLAT}_fw_config.dts \ 339 ${PLAT}_tb_fw_config.dts \ 340 ${PLAT}_soc_fw_config.dts \ 341 ${PLAT}_nt_fw_config.dts \ 342 ) 343 344FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 345FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 346FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 347FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 348 349ifeq (${SPD},tspd) 350FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 351FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 352 353# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 354$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 355endif 356 357ifeq (${TRANSFER_LIST}, 1) 358include lib/transfer_list/transfer_list.mk 359endif 360 361ifeq (${SPD},spmd) 362 363ifeq ($(ARM_SPMC_MANIFEST_DTS),) 364ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 365endif 366 367FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 368FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 369 370# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 372endif 373 374# Add the FW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 376# Add the TB_FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 378# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 380# Add the NT_FW_CONFIG to FIP and specify the same to certtool 381$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 382 383FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 384$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 385 386# Add the HW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 388endif 389 390# Enable dynamic mitigation support by default 391DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 392 393ifneq (${ENABLE_FEAT_AMU},0) 394BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 395 lib/cpus/aarch64/cpuamu_helpers.S 396 397ifeq (${HW_ASSISTED_COHERENCY}, 1) 398BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 399 lib/cpus/aarch64/neoverse_n1_pubsub.c 400endif 401endif 402 403ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 404ifeq (${ENABLE_FEAT_RAS},1) 405BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 406else 407BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 408endif 409endif 410 411ifneq (${ENABLE_STACK_PROTECTOR},0) 412PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 413endif 414 415# Enable the dynamic translation tables library. 416ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 417 ifeq (${ARCH},aarch32) 418 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 419 else # AArch64 420 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 421 endif 422endif 423 424ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 425 ifeq (${ARCH},aarch32) 426 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 427 else # AArch64 428 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 429 ifeq (${SPD},tspd) 430 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 431 endif 432 endif 433endif 434 435ifeq (${USE_DEBUGFS},1) 436 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 437endif 438 439# Add support for platform supplied linker script for BL31 build 440$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 441 442ifneq (${RESET_TO_BL2}, 0) 443 override BL1_SOURCES = 444endif 445 446# RSS is not supported on FVP right now. Thus, we use the mocked version 447# of the provided PSA APIs. They return with success and hard-coded token/key. 448PLAT_RSS_NOT_SUPPORTED := 1 449 450# Include Measured Boot makefile before any Crypto library makefile. 451# Crypto library makefile may need default definitions of Measured Boot build 452# flags present in Measured Boot makefile. 453ifeq (${MEASURED_BOOT},1) 454 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 455 $(info Including ${RSS_MEASURED_BOOT_MK}) 456 include ${RSS_MEASURED_BOOT_MK} 457 458 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 459 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 460 endif 461 462 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 463 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 464endif 465 466include plat/arm/board/common/board_common.mk 467include plat/arm/common/arm_common.mk 468 469ifeq (${MEASURED_BOOT},1) 470BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 471 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 472 lib/psa/measured_boot.c 473 474BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 475 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 476 lib/psa/measured_boot.c 477 478# Even though RSS is not supported on FVP (see above), we support overriding 479# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 480# the code to detect any build regressions. The resulting firmware will not be 481# functional. 482ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 483 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 484 include drivers/arm/rss/rss_comms.mk 485 BL1_SOURCES += ${RSS_COMMS_SOURCES} 486 BL2_SOURCES += ${RSS_COMMS_SOURCES} 487 BL31_SOURCES += ${RSS_COMMS_SOURCES} 488 489 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 490 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 491 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 492endif 493 494endif 495 496ifeq (${DRTM_SUPPORT}, 1) 497BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 498 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 499 plat/arm/board/fvp/fvp_drtm_err.c \ 500 plat/arm/board/fvp/fvp_drtm_measurement.c \ 501 plat/arm/board/fvp/fvp_drtm_stub.c \ 502 plat/arm/common/arm_dyn_cfg.c \ 503 plat/arm/board/fvp/fvp_err.c 504endif 505 506ifeq (${TRUSTED_BOARD_BOOT}, 1) 507BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 508BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 509 510# FVP being a development platform, enable capability to disable Authentication 511# dynamically if TRUSTED_BOARD_BOOT is set. 512DYN_DISABLE_AUTH := 1 513endif 514 515ifeq (${SPMC_AT_EL3}, 1) 516PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 517endif 518 519PSCI_OS_INIT_MODE := 1 520 521ifeq (${SPD},spmd) 522BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 523endif 524 525# Test specific macros, keep them at bottom of this file 526$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 527ifeq (${PLATFORM_TEST_EA_FFH}, 1) 528 ifeq (${FFH_SUPPORT}, 0) 529 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 530 endif 531 532endif 533 534$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 535ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 536 ifeq (${ENABLE_FEAT_RAS}, 0) 537 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 538 endif 539 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 540 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 541 endif 542endif 543 544ifeq (${ERRATA_ABI_SUPPORT}, 1) 545include plat/arm/board/fvp/fvp_cpu_errata.mk 546endif 547 548# Build macro necessary for running SPM tests on FVP platform 549$(eval $(call add_define,PLAT_TEST_SPM)) 550
