1/*
2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/tbbr/tbbr_img_def.h>
8
9/dts-v1/;
10
11/ {
12	dtb-registry {
13		compatible = "fconf,dyn_cfg-dtb_registry";
14
15		tb_fw-config {
16			load-address = <0x0 0x4001300>;
17			max-size = <0x1800>;
18			id = <TB_FW_CONFIG_ID>;
19		};
20
21		hw-config {
22			load-address = <0x0 0x07f00000>;
23			max-size = <0x00100000>;
24			id = <HW_CONFIG_ID>;
25			secondary-load-address = <0x0 0x82000000>;
26		};
27
28		/*
29		 * Load SoC and TOS firmware configs at the base of
30		 * non shared SRAM. The runtime checks ensure we don't
31		 * overlap BL2, BL31 or BL32. The NT firmware config
32		 * is loaded at base of DRAM.
33		 */
34		soc_fw-config {
35			load-address = <0x0 0x04001300>;
36			max-size = <0x200>;
37			id = <SOC_FW_CONFIG_ID>;
38		};
39
40/* If required, SPD should enable loading of trusted OS fw config */
41#if defined(SPD_tspd) || defined(SPD_spmd)
42		tos_fw-config {
43
44			load-address = <0x0 0x04001500>;
45#if ENABLE_RME
46			secondary-load-address = <0x0 0x7e00000>;
47#endif /* ENABLE_RME */
48			max-size = <0xB00>;
49			id = <TOS_FW_CONFIG_ID>;
50		};
51#endif
52
53		nt_fw-config {
54			load-address = <0x0 0x80000000>;
55			max-size = <0x200>;
56			id = <NT_FW_CONFIG_ID>;
57		};
58	};
59};
60