1/*
2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a710.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
30	ldr x0,=0x6
31	msr S3_6_c15_c8_0,x0
32	ldr x0,=0xF3A08002
33	msr S3_6_c15_c8_2,x0
34	ldr x0,=0xFFF0F7FE
35	msr S3_6_c15_c8_3,x0
36	ldr x0,=0x40000001003ff
37	msr S3_6_c15_c8_1,x0
38	ldr x0,=0x7
39	msr S3_6_c15_c8_0,x0
40	ldr x0,=0xBF200000
41	msr S3_6_c15_c8_2,x0
42	ldr x0,=0xFFEF0000
43	msr S3_6_c15_c8_3,x0
44	ldr x0,=0x40000001003f3
45	msr S3_6_c15_c8_1,x0
46workaround_reset_end cortex_a710, ERRATUM(1987031)
47
48check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0)
49
50workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
51	/* Stash ERRSELR_EL1 in x2 */
52	mrs	x2, ERRSELR_EL1
53
54	/* Select error record 0 and clear ED bit */
55	msr	ERRSELR_EL1, xzr
56	mrs	x1, ERXCTLR_EL1
57	bfi	x1, xzr, #ERXCTLR_ED_SHIFT, #1
58	msr	ERXCTLR_EL1, x1
59
60	/* Select error record 1 and clear ED bit */
61	mov	x0, #1
62	msr	ERRSELR_EL1, x0
63	mrs	x1, ERXCTLR_EL1
64	bfi	x1, xzr, #ERXCTLR_ED_SHIFT, #1
65	msr	ERXCTLR_EL1, x1
66
67	/* Restore ERRSELR_EL1 from x2 */
68	msr	ERRSELR_EL1, x2
69workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB
70
71check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0)
72
73workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096
74	sysreg_bit_set	CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
75workaround_reset_end cortex_a710, ERRATUM(2017096)
76
77check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0)
78
79workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002
80	sysreg_bit_set	CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46
81workaround_reset_end cortex_a710, ERRATUM(2055002)
82
83check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0)
84
85workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
86	sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
87		CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
88workaround_reset_end cortex_a710, ERRATUM(2058056)
89
90check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1)
91
92workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
93	ldr	x0,=0x3
94	msr	S3_6_c15_c8_0,x0
95	ldr	x0,=0xF3A08002
96	msr	S3_6_c15_c8_2,x0
97	ldr	x0,=0xFFF0F7FE
98	msr	S3_6_c15_c8_3,x0
99	ldr	x0,=0x10002001003FF
100	msr	S3_6_c15_c8_1,x0
101	ldr	x0,=0x4
102	msr	S3_6_c15_c8_0,x0
103	ldr	x0,=0xBF200000
104	msr	S3_6_c15_c8_2,x0
105	ldr	x0,=0xFFEF0000
106	msr	S3_6_c15_c8_3,x0
107	ldr	x0,=0x10002001003F3
108	msr	S3_6_c15_c8_1,x0
109workaround_reset_end cortex_a710, ERRATUM(2081180)
110
111check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0)
112
113workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908
114	sysreg_bit_set	CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
115workaround_reset_end cortex_a710, ERRATUM(2083908)
116
117check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
118
119workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059
120	sysreg_bit_set	CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
121workaround_reset_end cortex_a710, ERRATUM(2136059)
122
123check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0)
124
125workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715
126	sysreg_bit_set	CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
127workaround_reset_end cortex_a710, ERRATUM(2147715)
128
129check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
130
131workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384
132	sysreg_bit_set	CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
133
134	ldr	x0,=0x5
135	msr	CORTEX_A710_CPUPSELR_EL3, x0
136	ldr	x0,=0x10F600E000
137	msr	CORTEX_A710_CPUPOR_EL3, x0
138	ldr	x0,=0x10FF80E000
139	msr	CORTEX_A710_CPUPMR_EL3, x0
140	ldr	x0,=0x80000000003FF
141	msr	CORTEX_A710_CPUPCR_EL3, x0
142workaround_reset_end cortex_a710, ERRATUM(2216384)
143
144check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0)
145
146workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065
147	sysreg_bit_set	CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
148workaround_reset_end cortex_a710, ERRATUM(2267065)
149
150check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0)
151
152workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622
153	sysreg_bit_set	CORTEX_A710_CPUACTLR2_EL1, BIT(0)
154workaround_reset_end cortex_a710, ERRATUM(2282622)
155
156check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1)
157
158workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
159	/* Set bit 36 in ACTLR2_EL1 */
160	sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36
161workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB
162
163check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0)
164
165/*
166 * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as
167 * well. Create a symbollic link to existing errata workaround to get them
168 * registered under the Errata Framework.
169 */
170.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941
171.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa
172add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
173
174workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105
175	/* Set bit 40 in CPUACTLR2_EL1 */
176	sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40
177workaround_reset_end cortex_a710, ERRATUM(2371105)
178
179check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0)
180
181workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423
182	/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
183	sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55)
184	sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56)
185workaround_reset_end cortex_a710, ERRATUM(2742423)
186
187check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1)
188
189workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515
190	/* dsb before isb of power down sequence */
191	dsb	sy
192workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB
193
194check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1)
195
196workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471
197	sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47)
198workaround_reset_end cortex_a710, ERRATUM(2778471)
199
200check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
201
202workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
203#if IMAGE_BL31
204	/*
205	 * The Cortex-A710 generic vectors are overridden to apply errata
206	 * mitigation on exception entry from lower ELs.
207	 */
208	override_vector_table wa_cve_vbar_cortex_a710
209#endif /* IMAGE_BL31 */
210workaround_reset_end cortex_a710, CVE(2022, 23960)
211
212check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
213
214	/* ----------------------------------------------------
215	 * HW will do the cache maintenance while powering down
216	 * ----------------------------------------------------
217	 */
218func cortex_a710_core_pwr_dwn
219	apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
220	apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
221
222	/* ---------------------------------------------------
223	 * Enable CPU power down bit in power control register
224	 * ---------------------------------------------------
225	 */
226	sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
227	apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV
228	isb
229	ret
230endfunc cortex_a710_core_pwr_dwn
231
232errata_report_shim cortex_a710
233
234cpu_reset_func_start cortex_a710
235	/* Disable speculative loads */
236	msr	SSBS, xzr
237cpu_reset_func_end cortex_a710
238
239	/* ---------------------------------------------
240	 * This function provides Cortex-A710 specific
241	 * register information for crash reporting.
242	 * It needs to return with x6 pointing to
243	 * a list of register names in ascii and
244	 * x8 - x15 having values of registers to be
245	 * reported.
246	 * ---------------------------------------------
247	 */
248.section .rodata.cortex_a710_regs, "aS"
249cortex_a710_regs:  /* The ascii list of register names to be reported */
250	.asciz	"cpuectlr_el1", ""
251
252func cortex_a710_cpu_reg_dump
253	adr	x6, cortex_a710_regs
254	mrs	x8, CORTEX_A710_CPUECTLR_EL1
255	ret
256endfunc cortex_a710_cpu_reg_dump
257
258declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
259	cortex_a710_reset_func, \
260	cortex_a710_core_pwr_dwn
261