1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A78C_H 8 #define CORTEX_A78C_H 9 10 11 #define CORTEX_A78C_MIDR U(0x410FD4B1) 12 13 /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 14 #define CORTEX_A78C_BHB_LOOP_COUNT U(32) 15 16 /******************************************************************************* 17 * CPU Auxiliary Control register 2 specific definitions. 18 * ****************************************************************************/ 19 #define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 20 #define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 21 #define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 22 23 /******************************************************************************* 24 * CPU Extended Control register specific definitions. 25 ******************************************************************************/ 26 #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 27 #define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) 28 #define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) 29 #define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) 30 31 /******************************************************************************* 32 * CPU Power Control register specific definitions 33 ******************************************************************************/ 34 #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 35 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 36 37 /******************************************************************************* 38 * CPU Auxiliary Control register 3 specific definitions. 39 ******************************************************************************/ 40 #define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 41 42 /******************************************************************************* 43 * CPU Implementation Specific Selected Instruction registers 44 ******************************************************************************/ 45 #define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 46 #define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 47 #define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 48 #define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 49 50 /******************************************************************************* 51 * CPU Auxiliary Control register 5 specific definitions. 52 ******************************************************************************/ 53 #define CORTEX_A78C_ACTLR5_EL1 S3_0_C15_C9_0 54 55 #endif /* CORTEX_A78C_H */ 56
