1 /*
2 * Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <common/debug.h>
14 #include <drivers/clk.h>
15 #include <drivers/delay_timer.h>
16 #include <drivers/mmc.h>
17 #include <drivers/st/stm32_gpio.h>
18 #include <drivers/st/stm32_sdmmc2.h>
19 #include <drivers/st/stm32mp_reset.h>
20 #include <lib/mmio.h>
21 #include <lib/utils.h>
22 #include <libfdt.h>
23 #include <plat/common/platform.h>
24
25 #include <platform_def.h>
26
27 /* Registers offsets */
28 #define SDMMC_POWER 0x00U
29 #define SDMMC_CLKCR 0x04U
30 #define SDMMC_ARGR 0x08U
31 #define SDMMC_CMDR 0x0CU
32 #define SDMMC_RESPCMDR 0x10U
33 #define SDMMC_RESP1R 0x14U
34 #define SDMMC_RESP2R 0x18U
35 #define SDMMC_RESP3R 0x1CU
36 #define SDMMC_RESP4R 0x20U
37 #define SDMMC_DTIMER 0x24U
38 #define SDMMC_DLENR 0x28U
39 #define SDMMC_DCTRLR 0x2CU
40 #define SDMMC_DCNTR 0x30U
41 #define SDMMC_STAR 0x34U
42 #define SDMMC_ICR 0x38U
43 #define SDMMC_MASKR 0x3CU
44 #define SDMMC_ACKTIMER 0x40U
45 #define SDMMC_IDMACTRLR 0x50U
46 #define SDMMC_IDMABSIZER 0x54U
47 #define SDMMC_IDMABASE0R 0x58U
48 #define SDMMC_IDMABASE1R 0x5CU
49 #define SDMMC_FIFOR 0x80U
50
51 /* SDMMC power control register */
52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1)
54 #define SDMMC_POWER_DIRPOL BIT(4)
55
56 /* SDMMC clock control register */
57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
59 #define SDMMC_CLKCR_NEGEDGE BIT(16)
60 #define SDMMC_CLKCR_HWFC_EN BIT(17)
61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20)
62
63 /* SDMMC command register */
64 #define SDMMC_CMDR_CMDTRANS BIT(6)
65 #define SDMMC_CMDR_CMDSTOP BIT(7)
66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8)
67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8)
68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9)
69 #define SDMMC_CMDR_CPSMEN BIT(12)
70
71 /* SDMMC data control register */
72 #define SDMMC_DCTRLR_DTEN BIT(0)
73 #define SDMMC_DCTRLR_DTDIR BIT(1)
74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2)
75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4)
76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4
77 #define SDMMC_DCTRLR_FIFORST BIT(13)
78
79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \
80 SDMMC_DCTRLR_DTDIR | \
81 SDMMC_DCTRLR_DTMODE | \
82 SDMMC_DCTRLR_DBLOCKSIZE)
83
84 /* SDMMC status register */
85 #define SDMMC_STAR_CCRCFAIL BIT(0)
86 #define SDMMC_STAR_DCRCFAIL BIT(1)
87 #define SDMMC_STAR_CTIMEOUT BIT(2)
88 #define SDMMC_STAR_DTIMEOUT BIT(3)
89 #define SDMMC_STAR_TXUNDERR BIT(4)
90 #define SDMMC_STAR_RXOVERR BIT(5)
91 #define SDMMC_STAR_CMDREND BIT(6)
92 #define SDMMC_STAR_CMDSENT BIT(7)
93 #define SDMMC_STAR_DATAEND BIT(8)
94 #define SDMMC_STAR_DBCKEND BIT(10)
95 #define SDMMC_STAR_DPSMACT BIT(12)
96 #define SDMMC_STAR_RXFIFOHF BIT(15)
97 #define SDMMC_STAR_RXFIFOE BIT(19)
98 #define SDMMC_STAR_IDMATE BIT(27)
99 #define SDMMC_STAR_IDMABTC BIT(28)
100
101 /* SDMMC DMA control register */
102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0)
103
104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \
105 SDMMC_STAR_DCRCFAIL | \
106 SDMMC_STAR_CTIMEOUT | \
107 SDMMC_STAR_DTIMEOUT | \
108 SDMMC_STAR_TXUNDERR | \
109 SDMMC_STAR_RXOVERR | \
110 SDMMC_STAR_CMDREND | \
111 SDMMC_STAR_CMDSENT | \
112 SDMMC_STAR_DATAEND | \
113 SDMMC_STAR_DBCKEND | \
114 SDMMC_STAR_IDMATE | \
115 SDMMC_STAR_IDMABTC)
116
117 #define TIMEOUT_US_1_MS 1000U
118 #define TIMEOUT_US_10_MS 10000U
119 #define TIMEOUT_US_1_S 1000000U
120
121 /* Power cycle delays in ms */
122 #define VCC_POWER_OFF_DELAY 2
123 #define VCC_POWER_ON_DELAY 2
124 #define POWER_CYCLE_DELAY 2
125 #define POWER_OFF_DELAY 2
126 #define POWER_ON_DELAY 1
127
128 #ifndef DT_SDMMC2_COMPAT
129 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
130 #endif
131
132 #define SDMMC_FIFO_SIZE 64U
133
134 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
135 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
136 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
137 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
138 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
139
140 static void stm32_sdmmc2_init(void);
141 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
142 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
143 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width);
144 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size);
145 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size);
146 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size);
147
148 static const struct mmc_ops stm32_sdmmc2_ops = {
149 .init = stm32_sdmmc2_init,
150 .send_cmd = stm32_sdmmc2_send_cmd,
151 .set_ios = stm32_sdmmc2_set_ios,
152 .prepare = stm32_sdmmc2_prepare,
153 .read = stm32_sdmmc2_read,
154 .write = stm32_sdmmc2_write,
155 };
156
157 static struct stm32_sdmmc2_params sdmmc2_params;
158
159 static bool next_cmd_is_acmd;
160
161 #pragma weak plat_sdmmc2_use_dma
plat_sdmmc2_use_dma(unsigned int instance,unsigned int memory)162 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory)
163 {
164 return false;
165 }
166
stm32_sdmmc2_init(void)167 static void stm32_sdmmc2_init(void)
168 {
169 uint32_t clock_div;
170 uint32_t freq = STM32MP_MMC_INIT_FREQ;
171 uintptr_t base = sdmmc2_params.reg_base;
172 int ret;
173
174 if (sdmmc2_params.max_freq != 0U) {
175 freq = MIN(sdmmc2_params.max_freq, freq);
176 }
177
178 if (sdmmc2_params.vmmc_regu != NULL) {
179 ret = regulator_disable(sdmmc2_params.vmmc_regu);
180 if (ret < 0) {
181 panic();
182 }
183 }
184
185 mdelay(VCC_POWER_OFF_DELAY);
186
187 mmio_write_32(base + SDMMC_POWER,
188 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol);
189 mdelay(POWER_CYCLE_DELAY);
190
191 if (sdmmc2_params.vmmc_regu != NULL) {
192 ret = regulator_enable(sdmmc2_params.vmmc_regu);
193 if (ret < 0) {
194 panic();
195 }
196 }
197
198 mdelay(VCC_POWER_ON_DELAY);
199
200 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol);
201 mdelay(POWER_OFF_DELAY);
202
203 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U);
204
205 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
206 sdmmc2_params.negedge |
207 sdmmc2_params.pin_ckin);
208
209 mmio_write_32(base + SDMMC_POWER,
210 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol);
211
212 mdelay(POWER_ON_DELAY);
213 }
214
stm32_sdmmc2_stop_transfer(void)215 static int stm32_sdmmc2_stop_transfer(void)
216 {
217 struct mmc_cmd cmd_stop;
218
219 zeromem(&cmd_stop, sizeof(struct mmc_cmd));
220
221 cmd_stop.cmd_idx = MMC_CMD(12);
222 cmd_stop.resp_type = MMC_RESPONSE_R1B;
223
224 return stm32_sdmmc2_send_cmd(&cmd_stop);
225 }
226
stm32_sdmmc2_send_cmd_req(struct mmc_cmd * cmd)227 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
228 {
229 uint64_t timeout;
230 uint32_t flags_cmd, status;
231 uint32_t flags_data = 0;
232 int err = 0;
233 uintptr_t base = sdmmc2_params.reg_base;
234 unsigned int cmd_reg, arg_reg;
235
236 if (cmd == NULL) {
237 return -EINVAL;
238 }
239
240 flags_cmd = SDMMC_STAR_CTIMEOUT;
241 arg_reg = cmd->cmd_arg;
242
243 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) {
244 mmio_write_32(base + SDMMC_CMDR, 0);
245 }
246
247 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN;
248
249 if (cmd->resp_type == 0U) {
250 flags_cmd |= SDMMC_STAR_CMDSENT;
251 }
252
253 if ((cmd->resp_type & MMC_RSP_48) != 0U) {
254 if ((cmd->resp_type & MMC_RSP_136) != 0U) {
255 flags_cmd |= SDMMC_STAR_CMDREND;
256 cmd_reg |= SDMMC_CMDR_WAITRESP;
257 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) {
258 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL;
259 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT;
260 } else {
261 flags_cmd |= SDMMC_STAR_CMDREND;
262 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC;
263 }
264 }
265
266 switch (cmd->cmd_idx) {
267 case MMC_CMD(1):
268 arg_reg |= OCR_POWERUP;
269 break;
270 case MMC_CMD(6):
271 if ((sdmmc2_params.device_info->mmc_dev_type == MMC_IS_SD_HC) &&
272 (!next_cmd_is_acmd)) {
273 cmd_reg |= SDMMC_CMDR_CMDTRANS;
274 if (sdmmc2_params.use_dma) {
275 flags_data |= SDMMC_STAR_DCRCFAIL |
276 SDMMC_STAR_DTIMEOUT |
277 SDMMC_STAR_DATAEND |
278 SDMMC_STAR_RXOVERR |
279 SDMMC_STAR_IDMATE |
280 SDMMC_STAR_DBCKEND;
281 }
282 }
283 break;
284 case MMC_CMD(8):
285 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
286 cmd_reg |= SDMMC_CMDR_CMDTRANS;
287 }
288 break;
289 case MMC_CMD(12):
290 cmd_reg |= SDMMC_CMDR_CMDSTOP;
291 break;
292 case MMC_CMD(17):
293 case MMC_CMD(18):
294 cmd_reg |= SDMMC_CMDR_CMDTRANS;
295 if (sdmmc2_params.use_dma) {
296 flags_data |= SDMMC_STAR_DCRCFAIL |
297 SDMMC_STAR_DTIMEOUT |
298 SDMMC_STAR_DATAEND |
299 SDMMC_STAR_RXOVERR |
300 SDMMC_STAR_IDMATE;
301 }
302 break;
303 case MMC_ACMD(41):
304 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4;
305 break;
306 case MMC_ACMD(51):
307 cmd_reg |= SDMMC_CMDR_CMDTRANS;
308 if (sdmmc2_params.use_dma) {
309 flags_data |= SDMMC_STAR_DCRCFAIL |
310 SDMMC_STAR_DTIMEOUT |
311 SDMMC_STAR_DATAEND |
312 SDMMC_STAR_RXOVERR |
313 SDMMC_STAR_IDMATE |
314 SDMMC_STAR_DBCKEND;
315 }
316 break;
317 default:
318 break;
319 }
320
321 next_cmd_is_acmd = (cmd->cmd_idx == MMC_CMD(55));
322
323 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
324
325 /*
326 * Clear the SDMMC_DCTRLR if the command does not await data.
327 * Skip CMD55 as the next command could be data related, and
328 * the register could have been set in prepare function.
329 */
330 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && !next_cmd_is_acmd) {
331 mmio_write_32(base + SDMMC_DCTRLR, 0U);
332 }
333
334 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) {
335 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
336 }
337
338 mmio_write_32(base + SDMMC_ARGR, arg_reg);
339
340 mmio_write_32(base + SDMMC_CMDR, cmd_reg);
341
342 status = mmio_read_32(base + SDMMC_STAR);
343
344 timeout = timeout_init_us(TIMEOUT_US_10_MS);
345
346 while ((status & flags_cmd) == 0U) {
347 if (timeout_elapsed(timeout)) {
348 err = -ETIMEDOUT;
349 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n",
350 __func__, cmd->cmd_idx, status);
351 goto err_exit;
352 }
353
354 status = mmio_read_32(base + SDMMC_STAR);
355 }
356
357 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) {
358 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) {
359 err = -ETIMEDOUT;
360 /*
361 * Those timeouts can occur, and framework will handle
362 * the retries. CMD8 is expected to return this timeout
363 * for eMMC
364 */
365 if (!((cmd->cmd_idx == MMC_CMD(1)) ||
366 (cmd->cmd_idx == MMC_CMD(13)) ||
367 ((cmd->cmd_idx == MMC_CMD(8)) &&
368 (cmd->resp_type == MMC_RESPONSE_R7)))) {
369 ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n",
370 __func__, cmd->cmd_idx, status);
371 }
372 } else {
373 err = -EIO;
374 ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n",
375 __func__, cmd->cmd_idx, status);
376 }
377
378 goto err_exit;
379 }
380
381 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) {
382 if ((cmd->cmd_idx == MMC_CMD(9)) &&
383 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) {
384 /* Need to invert response to match CSD structure */
385 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R);
386 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R);
387 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R);
388 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R);
389 } else {
390 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R);
391 if ((cmd_reg & SDMMC_CMDR_WAITRESP) ==
392 SDMMC_CMDR_WAITRESP) {
393 cmd->resp_data[1] = mmio_read_32(base +
394 SDMMC_RESP2R);
395 cmd->resp_data[2] = mmio_read_32(base +
396 SDMMC_RESP3R);
397 cmd->resp_data[3] = mmio_read_32(base +
398 SDMMC_RESP4R);
399 }
400 }
401 }
402
403 if (flags_data == 0U) {
404 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
405
406 return 0;
407 }
408
409 status = mmio_read_32(base + SDMMC_STAR);
410
411 timeout = timeout_init_us(TIMEOUT_US_10_MS);
412
413 while ((status & flags_data) == 0U) {
414 if (timeout_elapsed(timeout)) {
415 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n",
416 __func__, cmd->cmd_idx, status);
417 err = -ETIMEDOUT;
418 goto err_exit;
419 }
420
421 status = mmio_read_32(base + SDMMC_STAR);
422 };
423
424 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL |
425 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR |
426 SDMMC_STAR_IDMATE)) != 0U) {
427 ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__,
428 cmd->cmd_idx, status);
429 err = -EIO;
430 }
431
432 err_exit:
433 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
434 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
435
436 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) {
437 int ret_stop = stm32_sdmmc2_stop_transfer();
438
439 if (ret_stop != 0) {
440 return ret_stop;
441 }
442 }
443
444 return err;
445 }
446
stm32_sdmmc2_send_cmd(struct mmc_cmd * cmd)447 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd)
448 {
449 uint8_t retry;
450 int err;
451
452 assert(cmd != NULL);
453
454 for (retry = 0U; retry < 3U; retry++) {
455 err = stm32_sdmmc2_send_cmd_req(cmd);
456 if (err == 0) {
457 return 0;
458 }
459
460 if ((cmd->cmd_idx == MMC_CMD(1)) ||
461 (cmd->cmd_idx == MMC_CMD(13))) {
462 return 0; /* Retry managed by framework */
463 }
464
465 /* Command 8 is expected to fail for eMMC */
466 if (cmd->cmd_idx != MMC_CMD(8)) {
467 WARN(" CMD%u, Retry: %u, Error: %d\n",
468 cmd->cmd_idx, retry + 1U, err);
469 }
470
471 udelay(10U);
472 }
473
474 return err;
475 }
476
stm32_sdmmc2_set_ios(unsigned int clk,unsigned int width)477 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
478 {
479 uintptr_t base = sdmmc2_params.reg_base;
480 uint32_t bus_cfg = 0;
481 uint32_t clock_div, max_freq, freq;
482 uint32_t clk_rate = sdmmc2_params.clk_rate;
483 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq;
484
485 switch (width) {
486 case MMC_BUS_WIDTH_1:
487 break;
488 case MMC_BUS_WIDTH_4:
489 bus_cfg |= SDMMC_CLKCR_WIDBUS_4;
490 break;
491 case MMC_BUS_WIDTH_8:
492 bus_cfg |= SDMMC_CLKCR_WIDBUS_8;
493 break;
494 default:
495 panic();
496 break;
497 }
498
499 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
500 if (max_bus_freq >= 52000000U) {
501 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
502 } else {
503 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
504 }
505 } else {
506 if (max_bus_freq >= 50000000U) {
507 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
508 } else {
509 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
510 }
511 }
512
513 if (sdmmc2_params.max_freq != 0U) {
514 freq = MIN(sdmmc2_params.max_freq, max_freq);
515 } else {
516 freq = max_freq;
517 }
518
519 clock_div = div_round_up(clk_rate, freq * 2U);
520
521 mmio_write_32(base + SDMMC_CLKCR,
522 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg |
523 sdmmc2_params.negedge |
524 sdmmc2_params.pin_ckin);
525
526 return 0;
527 }
528
stm32_sdmmc2_prepare(int lba,uintptr_t buf,size_t size)529 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
530 {
531 struct mmc_cmd cmd;
532 int ret;
533 uintptr_t base = sdmmc2_params.reg_base;
534 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
535 uint32_t arg_size;
536
537 assert((size != 0U) && (size <= UINT32_MAX));
538
539 if (size > MMC_BLOCK_SIZE) {
540 arg_size = MMC_BLOCK_SIZE;
541 } else {
542 arg_size = (uint32_t)size;
543 }
544
545 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
546
547 if (sdmmc2_params.use_dma) {
548 inv_dcache_range(buf, size);
549 }
550
551 /* Prepare CMD 16*/
552 mmio_write_32(base + SDMMC_DTIMER, 0);
553
554 mmio_write_32(base + SDMMC_DLENR, 0);
555
556 mmio_write_32(base + SDMMC_DCTRLR, 0);
557
558 zeromem(&cmd, sizeof(struct mmc_cmd));
559
560 cmd.cmd_idx = MMC_CMD(16);
561 cmd.cmd_arg = arg_size;
562 cmd.resp_type = MMC_RESPONSE_R1;
563
564 ret = stm32_sdmmc2_send_cmd(&cmd);
565 if (ret != 0) {
566 ERROR("CMD16 failed\n");
567 return ret;
568 }
569
570 /* Prepare data command */
571 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
572
573 mmio_write_32(base + SDMMC_DLENR, size);
574
575 if (sdmmc2_params.use_dma) {
576 mmio_write_32(base + SDMMC_IDMACTRLR,
577 SDMMC_IDMACTRLR_IDMAEN);
578 mmio_write_32(base + SDMMC_IDMABASE0R, buf);
579
580 flush_dcache_range(buf, size);
581 }
582
583 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT;
584
585 mmio_clrsetbits_32(base + SDMMC_DCTRLR,
586 SDMMC_DCTRLR_CLEAR_MASK,
587 data_ctrl);
588
589 return 0;
590 }
591
stm32_sdmmc2_read(int lba,uintptr_t buf,size_t size)592 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
593 {
594 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL |
595 SDMMC_STAR_DTIMEOUT;
596 uint32_t flags = error_flags | SDMMC_STAR_DATAEND;
597 uint32_t status;
598 uint32_t *buffer;
599 uintptr_t base = sdmmc2_params.reg_base;
600 uintptr_t fifo_reg = base + SDMMC_FIFOR;
601 uint64_t timeout;
602 int ret;
603
604 /* Assert buf is 4 bytes aligned */
605 assert((buf & GENMASK(1, 0)) == 0U);
606
607 buffer = (uint32_t *)buf;
608
609 if (sdmmc2_params.use_dma) {
610 inv_dcache_range(buf, size);
611
612 return 0;
613 }
614
615 if (size <= MMC_BLOCK_SIZE) {
616 flags |= SDMMC_STAR_DBCKEND;
617 }
618
619 timeout = timeout_init_us(TIMEOUT_US_1_S);
620
621 do {
622 status = mmio_read_32(base + SDMMC_STAR);
623
624 if ((status & error_flags) != 0U) {
625 ERROR("%s: Read error (status = %x)\n", __func__,
626 status);
627 mmio_write_32(base + SDMMC_DCTRLR,
628 SDMMC_DCTRLR_FIFORST);
629
630 mmio_write_32(base + SDMMC_ICR,
631 SDMMC_STATIC_FLAGS);
632
633 ret = stm32_sdmmc2_stop_transfer();
634 if (ret != 0) {
635 return ret;
636 }
637
638 return -EIO;
639 }
640
641 if (timeout_elapsed(timeout)) {
642 ERROR("%s: timeout 1s (status = %x)\n",
643 __func__, status);
644 mmio_write_32(base + SDMMC_ICR,
645 SDMMC_STATIC_FLAGS);
646
647 ret = stm32_sdmmc2_stop_transfer();
648 if (ret != 0) {
649 return ret;
650 }
651
652 return -ETIMEDOUT;
653 }
654
655 if (size < (SDMMC_FIFO_SIZE / 2U)) {
656 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) &&
657 ((status & SDMMC_STAR_RXFIFOE) == 0U)) {
658 *buffer = mmio_read_32(fifo_reg);
659 buffer++;
660 }
661 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) {
662 uint32_t count;
663
664 /* Read data from SDMMC Rx FIFO */
665 for (count = 0; count < (SDMMC_FIFO_SIZE / 2U);
666 count += sizeof(uint32_t)) {
667 *buffer = mmio_read_32(fifo_reg);
668 buffer++;
669 }
670 }
671 } while ((status & flags) == 0U);
672
673 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
674
675 if ((status & SDMMC_STAR_DPSMACT) != 0U) {
676 WARN("%s: DPSMACT=1, send stop\n", __func__);
677 return stm32_sdmmc2_stop_transfer();
678 }
679
680 return 0;
681 }
682
stm32_sdmmc2_write(int lba,uintptr_t buf,size_t size)683 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size)
684 {
685 return 0;
686 }
687
stm32_sdmmc2_dt_get_config(void)688 static int stm32_sdmmc2_dt_get_config(void)
689 {
690 int sdmmc_node;
691 void *fdt = NULL;
692 const fdt32_t *cuint;
693 struct dt_node_info dt_info;
694
695 if (fdt_get_address(&fdt) == 0) {
696 return -FDT_ERR_NOTFOUND;
697 }
698
699 if (fdt == NULL) {
700 return -FDT_ERR_NOTFOUND;
701 }
702
703 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT,
704 sdmmc2_params.reg_base);
705 if (sdmmc_node == -FDT_ERR_NOTFOUND) {
706 return -FDT_ERR_NOTFOUND;
707 }
708
709 dt_fill_device_info(&dt_info, sdmmc_node);
710 if (dt_info.status == DT_DISABLED) {
711 return -FDT_ERR_NOTFOUND;
712 }
713
714 if (dt_set_pinctrl_config(sdmmc_node) != 0) {
715 return -FDT_ERR_BADVALUE;
716 }
717
718 sdmmc2_params.clock_id = dt_info.clock;
719 sdmmc2_params.reset_id = dt_info.reset;
720
721 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) {
722 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0;
723 }
724
725 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) {
726 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL;
727 }
728
729 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) {
730 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE;
731 }
732
733 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL);
734 if (cuint != NULL) {
735 switch (fdt32_to_cpu(*cuint)) {
736 case 4:
737 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4;
738 break;
739
740 case 8:
741 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8;
742 break;
743
744 default:
745 break;
746 }
747 }
748
749 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL);
750 if (cuint != NULL) {
751 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint);
752 }
753
754 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc");
755
756 return 0;
757 }
758
stm32_sdmmc2_mmc_get_device_size(void)759 unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
760 {
761 return sdmmc2_params.device_info->device_size;
762 }
763
stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params * params)764 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
765 {
766 assert((params != NULL) &&
767 ((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
768 ((params->bus_width == MMC_BUS_WIDTH_1) ||
769 (params->bus_width == MMC_BUS_WIDTH_4) ||
770 (params->bus_width == MMC_BUS_WIDTH_8)));
771
772 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params));
773
774 sdmmc2_params.vmmc_regu = NULL;
775
776 if (stm32_sdmmc2_dt_get_config() != 0) {
777 ERROR("%s: DT error\n", __func__);
778 return -ENOMEM;
779 }
780
781 clk_enable(sdmmc2_params.clock_id);
782
783 if ((int)sdmmc2_params.reset_id >= 0) {
784 int rc;
785
786 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
787 if (rc != 0) {
788 panic();
789 }
790 udelay(2);
791 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
792 if (rc != 0) {
793 panic();
794 }
795 mdelay(1);
796 }
797
798 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id);
799 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
800
801 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
802 sdmmc2_params.bus_width, sdmmc2_params.flags,
803 sdmmc2_params.device_info);
804 }
805
