1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.22 Build 14, unless otherwise stated. 16 17- ``Foundation_Platform`` 18- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21) 19- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21) 20- ``FVP_Base_AEMvA`` 21- ``FVP_Base_AEMvA-AEMvA`` 22- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38) 23- ``FVP_Base_Cortex-A35x4`` 24- ``FVP_Base_Cortex-A53x4`` 25- ``FVP_Base_Cortex-A55`` 26- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 27- ``FVP_Base_Cortex-A55x4+Cortex-A76x2`` 28- ``FVP_Base_Cortex-A57x1-A53x1`` 29- ``FVP_Base_Cortex-A57x2-A53x4`` 30- ``FVP_Base_Cortex-A57x4`` 31- ``FVP_Base_Cortex-A57x4-A53x4`` 32- ``FVP_Base_Cortex-A65`` 33- ``FVP_Base_Cortex-A65AE`` 34- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21) 35- ``FVP_Base_Cortex-A72x4`` 36- ``FVP_Base_Cortex-A72x4-A53x4`` 37- ``FVP_Base_Cortex-A73x4`` 38- ``FVP_Base_Cortex-A73x4-A53x4`` 39- ``FVP_Base_Cortex-A75`` 40- ``FVP_Base_Cortex-A76`` 41- ``FVP_Base_Cortex-A76AE`` 42- ``FVP_Base_Cortex-A77`` 43- ``FVP_Base_Cortex-A78`` 44- ``FVP_Base_Cortex-A78AE`` 45- ``FVP_Base_Cortex-A78C`` 46- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21) 47- ``FVP_Base_Neoverse-E1`` 48- ``FVP_Base_Neoverse-N1`` 49- ``FVP_Base_Neoverse-V1`` 50- ``FVP_Base_RevC-2xAEMvA`` 51- ``FVP_BaseR_AEMv8R`` 52- ``FVP_Morello`` (Version 0.11/33) 53- ``FVP_RD_V1`` 54- ``FVP_TC1`` 55- ``FVP_TC2`` (Version 11.20/24) 56 57The latest version of the AArch32 build of TF-A has been tested on the 58following Arm FVPs without shifted affinities, and that do not support threaded 59CPU cores (64-bit host machine only). 60 61- ``FVP_Base_AEMvA`` 62- ``FVP_Base_AEMvA-AEMvA`` 63- ``FVP_Base_Cortex-A32x4`` 64 65.. note:: 66 The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which 67 is not compatible with legacy GIC configurations. Therefore this FVP does not 68 support these legacy GIC configurations. 69 70The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 71FVP website`_. The Cortex-A models listed above are also available to download 72from `Arm's website`_. 73 74.. note:: 75 The build numbers quoted above are those reported by launching the FVP 76 with the ``--version`` parameter. 77 78.. note:: 79 Linaro provides a ramdisk image in prebuilt FVP configurations and full 80 file systems that can be downloaded separately. To run an FVP with a virtio 81 file system image an additional FVP configuration option 82 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 83 used. 84 85.. note:: 86 The software will not work on Version 1.0 of the Foundation FVP. 87 The commands below would report an ``unhandled argument`` error in this case. 88 89.. note:: 90 FVPs can be launched with ``--cadi-server`` option such that a 91 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 92 its execution. 93 94.. warning:: 95 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 96 the internal synchronisation timings changed compared to older versions of 97 the models. The models can be launched with ``-Q 100`` option if they are 98 required to match the run time characteristics of the older versions. 99 100All the above platforms have been tested with `Linaro Release 20.01`_. 101 102.. _build_options_arm_fvp_platform: 103 104Arm FVP Platform Specific Build Options 105--------------------------------------- 106 107- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 108 build the topology tree within TF-A. By default TF-A is configured for dual 109 cluster topology and this option can be used to override the default value. 110 111- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 112 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 113 explained in the options below: 114 115 - ``FVP_CCI`` : The CCI driver is selected. This is the default 116 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 117 - ``FVP_CCN`` : The CCN driver is selected. This is the default 118 if ``FVP_CLUSTER_COUNT`` > 2. 119 120- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 121 a single cluster. This option defaults to 4. 122 123- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 124 in the system. This option defaults to 1. Note that the build option 125 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 126 127- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 128 129 - ``FVP_GICV2`` : The GICv2 only driver is selected 130 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 131 132- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 133 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 134 details on HW_CONFIG. By default, this is initialized to a sensible DTS 135 file in ``fdts/`` folder depending on other build options. But some cases, 136 like shifted affinity format for MPIDR, cannot be detected at build time 137 and this option is needed to specify the appropriate DTS file. 138 139- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 140 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 141 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 142 HW_CONFIG blob instead of the DTS file. This option is useful to override 143 the default HW_CONFIG selected by the build system. 144 145- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of 146 inactive/fused CPU cores as read-only. The default value of this option 147 is ``0``, which means the redistributor pages of all CPU cores are marked 148 as read and write. 149 150Booting Firmware Update images 151------------------------------ 152 153When Firmware Update (FWU) is enabled there are at least 2 new images 154that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 155FWU FIP. 156 157The additional fip images must be loaded with: 158 159:: 160 161 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 162 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 163 164The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 165In the same way, the address ns_bl2u_base_address is the value of 166NS_BL2U_BASE. 167 168Booting an EL3 payload 169---------------------- 170 171The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 172the secondary CPUs holding pen to work properly. Unfortunately, its reset value 173is undefined on the FVP platform and the FVP platform code doesn't clear it. 174Therefore, one must modify the way the model is normally invoked in order to 175clear the mailbox at start-up. 176 177One way to do that is to create an 8-byte file containing all zero bytes using 178the following command: 179 180.. code:: shell 181 182 dd if=/dev/zero of=mailbox.dat bs=1 count=8 183 184and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 185using the following model parameters: 186 187:: 188 189 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 190 --data=mailbox.dat@0x04000000 [Foundation FVP] 191 192To provide the model with the EL3 payload image, the following methods may be 193used: 194 195#. If the EL3 payload is able to execute in place, it may be programmed into 196 flash memory. On Base Cortex and AEM FVPs, the following model parameter 197 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 198 used for the FIP): 199 200 :: 201 202 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 203 204 On Foundation FVP, there is no flash loader component and the EL3 payload 205 may be programmed anywhere in flash using method 3 below. 206 207#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 208 command may be used to load the EL3 payload ELF image over JTAG: 209 210 :: 211 212 load <path-to>/el3-payload.elf 213 214#. The EL3 payload may be pre-loaded in volatile memory using the following 215 model parameters: 216 217 :: 218 219 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 220 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 221 222 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 223 used when building TF-A. 224 225Booting a preloaded kernel image (Base FVP) 226------------------------------------------- 227 228The following example uses a simplified boot flow by directly jumping from the 229TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 230useful if both the kernel and the device tree blob (DTB) are already present in 231memory (like in FVP). 232 233For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 234address ``0x82000000``, the firmware can be built like this: 235 236.. code:: shell 237 238 CROSS_COMPILE=aarch64-none-elf- \ 239 make PLAT=fvp DEBUG=1 \ 240 RESET_TO_BL31=1 \ 241 ARM_LINUX_KERNEL_AS_BL33=1 \ 242 PRELOADED_BL33_BASE=0x80080000 \ 243 ARM_PRELOADED_DTB_BASE=0x82000000 \ 244 all fip 245 246Now, it is needed to modify the DTB so that the kernel knows the address of the 247ramdisk. The following script generates a patched DTB from the provided one, 248assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 249script assumes that the user is using a ramdisk image prepared for U-Boot, like 250the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 251offset in ``INITRD_START`` has to be removed. 252 253.. code:: bash 254 255 #!/bin/bash 256 257 # Path to the input DTB 258 KERNEL_DTB=<path-to>/<fdt> 259 # Path to the output DTB 260 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 261 # Base address of the ramdisk 262 INITRD_BASE=0x84000000 263 # Path to the ramdisk 264 INITRD=<path-to>/<ramdisk.img> 265 266 # Skip uboot header (64 bytes) 267 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 268 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 269 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 270 271 CHOSEN_NODE=$(echo \ 272 "/ { \ 273 chosen { \ 274 linux,initrd-start = <${INITRD_START}>; \ 275 linux,initrd-end = <${INITRD_END}>; \ 276 }; \ 277 };") 278 279 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 280 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 281 282And the FVP binary can be run with the following command: 283 284.. code:: shell 285 286 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 287 -C pctl.startup=0.0.0.0 \ 288 -C bp.secure_memory=1 \ 289 -C cluster0.NUM_CORES=4 \ 290 -C cluster1.NUM_CORES=4 \ 291 -C cache_state_modelled=1 \ 292 -C cluster0.cpu0.RVBAR=0x04001000 \ 293 -C cluster0.cpu1.RVBAR=0x04001000 \ 294 -C cluster0.cpu2.RVBAR=0x04001000 \ 295 -C cluster0.cpu3.RVBAR=0x04001000 \ 296 -C cluster1.cpu0.RVBAR=0x04001000 \ 297 -C cluster1.cpu1.RVBAR=0x04001000 \ 298 -C cluster1.cpu2.RVBAR=0x04001000 \ 299 -C cluster1.cpu3.RVBAR=0x04001000 \ 300 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 301 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 302 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 303 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 304 305Obtaining the Flattened Device Trees 306^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 307 308Depending on the FVP configuration and Linux configuration used, different 309FDT files are required. FDT source files for the Foundation and Base FVPs can 310be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 311a subset of the Base FVP components. For example, the Foundation FVP lacks 312CLCD and MMC support, and has only one CPU cluster. 313 314.. note:: 315 It is not recommended to use the FDTs built along the kernel because not 316 all FDTs are available from there. 317 318The dynamic configuration capability is enabled in the firmware for FVPs. 319This means that the firmware can authenticate and load the FDT if present in 320FIP. A default FDT is packaged into FIP during the build based on 321the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 322or ``FVP_HW_CONFIG_DTS`` build options (refer to 323:ref:`build_options_arm_fvp_platform` for details on the options). 324 325- ``fvp-base-gicv2-psci.dts`` 326 327 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 328 without shifted affinities and with Base memory map configuration. 329 330- ``fvp-base-gicv3-psci.dts`` 331 332 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 333 without shifted affinities and with Base memory map configuration and 334 Linux GICv3 support. 335 336- ``fvp-base-gicv3-psci-1t.dts`` 337 338 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 339 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 340 341- ``fvp-base-gicv3-psci-dynamiq.dts`` 342 343 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 344 single cluster, single threaded CPUs, Base memory map configuration and Linux 345 GICv3 support. 346 347- ``fvp-foundation-gicv2-psci.dts`` 348 349 For use with Foundation FVP with Base memory map configuration. 350 351- ``fvp-foundation-gicv3-psci.dts`` 352 353 (Default) For use with Foundation FVP with Base memory map configuration 354 and Linux GICv3 support. 355 356 357Running on the Foundation FVP with reset to BL1 entrypoint 358^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 359 360The following ``Foundation_Platform`` parameters should be used to boot Linux with 3614 CPUs using the AArch64 build of TF-A. 362 363.. code:: shell 364 365 <path-to>/Foundation_Platform \ 366 --cores=4 \ 367 --arm-v8.0 \ 368 --secure-memory \ 369 --visualization \ 370 --gicv3 \ 371 --data="<path-to>/<bl1-binary>"@0x0 \ 372 --data="<path-to>/<FIP-binary>"@0x08000000 \ 373 --data="<path-to>/<kernel-binary>"@0x80080000 \ 374 --data="<path-to>/<ramdisk-binary>"@0x84000000 375 376Notes: 377 378- BL1 is loaded at the start of the Trusted ROM. 379- The Firmware Image Package is loaded at the start of NOR FLASH0. 380- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 381 is specified via the ``load-address`` property in the ``hw-config`` node of 382 `FW_CONFIG for FVP`_. 383- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 384 and enable the GICv3 device in the model. Note that without this option, 385 the Foundation FVP defaults to legacy (Versatile Express) memory map which 386 is not supported by TF-A. 387- In order for TF-A to run correctly on the Foundation FVP, the architecture 388 versions must match. The Foundation FVP defaults to the highest v8.x 389 version it supports but the default build for TF-A is for v8.0. To avoid 390 issues either start the Foundation FVP to use v8.0 architecture using the 391 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 392 ``ARM_ARCH_MINOR``. 393 394Running on the AEMv8 Base FVP with reset to BL1 entrypoint 395^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 396 397The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 398with 8 CPUs using the AArch64 build of TF-A. 399 400.. code:: shell 401 402 <path-to>/FVP_Base_RevC-2xAEMv8A \ 403 -C pctl.startup=0.0.0.0 \ 404 -C bp.secure_memory=1 \ 405 -C bp.tzc_400.diagnostics=1 \ 406 -C cluster0.NUM_CORES=4 \ 407 -C cluster1.NUM_CORES=4 \ 408 -C cache_state_modelled=1 \ 409 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 410 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 411 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 412 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 413 414.. note:: 415 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 416 a specific DTS for all the CPUs to be loaded. 417 418Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 419^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 420 421The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 422with 8 CPUs using the AArch32 build of TF-A. 423 424.. code:: shell 425 426 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 427 -C pctl.startup=0.0.0.0 \ 428 -C bp.secure_memory=1 \ 429 -C bp.tzc_400.diagnostics=1 \ 430 -C cluster0.NUM_CORES=4 \ 431 -C cluster1.NUM_CORES=4 \ 432 -C cache_state_modelled=1 \ 433 -C cluster0.cpu0.CONFIG64=0 \ 434 -C cluster0.cpu1.CONFIG64=0 \ 435 -C cluster0.cpu2.CONFIG64=0 \ 436 -C cluster0.cpu3.CONFIG64=0 \ 437 -C cluster1.cpu0.CONFIG64=0 \ 438 -C cluster1.cpu1.CONFIG64=0 \ 439 -C cluster1.cpu2.CONFIG64=0 \ 440 -C cluster1.cpu3.CONFIG64=0 \ 441 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 442 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 443 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 444 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 445 446Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 447^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 448 449The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 450boot Linux with 8 CPUs using the AArch64 build of TF-A. 451 452.. code:: shell 453 454 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 455 -C pctl.startup=0.0.0.0 \ 456 -C bp.secure_memory=1 \ 457 -C bp.tzc_400.diagnostics=1 \ 458 -C cache_state_modelled=1 \ 459 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 460 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 461 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 462 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 463 464Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 465^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 466 467The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 468boot Linux with 4 CPUs using the AArch32 build of TF-A. 469 470.. code:: shell 471 472 <path-to>/FVP_Base_Cortex-A32x4 \ 473 -C pctl.startup=0.0.0.0 \ 474 -C bp.secure_memory=1 \ 475 -C bp.tzc_400.diagnostics=1 \ 476 -C cache_state_modelled=1 \ 477 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 478 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 479 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 480 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 481 482 483Running on the AEMv8 Base FVP with reset to BL31 entrypoint 484^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 485 486The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 487with 8 CPUs using the AArch64 build of TF-A. 488 489.. code:: shell 490 491 <path-to>/FVP_Base_RevC-2xAEMv8A \ 492 -C pctl.startup=0.0.0.0 \ 493 -C bp.secure_memory=1 \ 494 -C bp.tzc_400.diagnostics=1 \ 495 -C cluster0.NUM_CORES=4 \ 496 -C cluster1.NUM_CORES=4 \ 497 -C cache_state_modelled=1 \ 498 -C cluster0.cpu0.RVBAR=0x04010000 \ 499 -C cluster0.cpu1.RVBAR=0x04010000 \ 500 -C cluster0.cpu2.RVBAR=0x04010000 \ 501 -C cluster0.cpu3.RVBAR=0x04010000 \ 502 -C cluster1.cpu0.RVBAR=0x04010000 \ 503 -C cluster1.cpu1.RVBAR=0x04010000 \ 504 -C cluster1.cpu2.RVBAR=0x04010000 \ 505 -C cluster1.cpu3.RVBAR=0x04010000 \ 506 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 507 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 508 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 509 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 510 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 511 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 512 513Notes: 514 515- Position Independent Executable (PIE) support is enabled in this 516 config allowing BL31 to be loaded at any valid address for execution. 517 518- Since a FIP is not loaded when using BL31 as reset entrypoint, the 519 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 520 parameter is needed to load the individual bootloader images in memory. 521 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 522 Payload. For the same reason, the FDT needs to be compiled from the DT source 523 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 524 parameter. 525 526- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 527 specific DTS for all the CPUs to be loaded. 528 529- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 530 X and Y are the cluster and CPU numbers respectively, is used to set the 531 reset vector for each core. 532 533- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 534 changing the value of 535 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 536 ``BL32_BASE``. 537 538 539Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 540^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 541 542The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 543with 8 CPUs using the AArch32 build of TF-A. 544 545.. code:: shell 546 547 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 548 -C pctl.startup=0.0.0.0 \ 549 -C bp.secure_memory=1 \ 550 -C bp.tzc_400.diagnostics=1 \ 551 -C cluster0.NUM_CORES=4 \ 552 -C cluster1.NUM_CORES=4 \ 553 -C cache_state_modelled=1 \ 554 -C cluster0.cpu0.CONFIG64=0 \ 555 -C cluster0.cpu1.CONFIG64=0 \ 556 -C cluster0.cpu2.CONFIG64=0 \ 557 -C cluster0.cpu3.CONFIG64=0 \ 558 -C cluster1.cpu0.CONFIG64=0 \ 559 -C cluster1.cpu1.CONFIG64=0 \ 560 -C cluster1.cpu2.CONFIG64=0 \ 561 -C cluster1.cpu3.CONFIG64=0 \ 562 -C cluster0.cpu0.RVBAR=0x04002000 \ 563 -C cluster0.cpu1.RVBAR=0x04002000 \ 564 -C cluster0.cpu2.RVBAR=0x04002000 \ 565 -C cluster0.cpu3.RVBAR=0x04002000 \ 566 -C cluster1.cpu0.RVBAR=0x04002000 \ 567 -C cluster1.cpu1.RVBAR=0x04002000 \ 568 -C cluster1.cpu2.RVBAR=0x04002000 \ 569 -C cluster1.cpu3.RVBAR=0x04002000 \ 570 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 571 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 572 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 573 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 574 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 575 576.. note:: 577 Position Independent Executable (PIE) support is enabled in this 578 config allowing SP_MIN to be loaded at any valid address for execution. 579 580Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 581^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 582 583The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 584boot Linux with 8 CPUs using the AArch64 build of TF-A. 585 586.. code:: shell 587 588 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 589 -C pctl.startup=0.0.0.0 \ 590 -C bp.secure_memory=1 \ 591 -C bp.tzc_400.diagnostics=1 \ 592 -C cache_state_modelled=1 \ 593 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 594 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 595 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 596 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 597 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 598 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 599 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 600 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 601 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 602 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 603 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 604 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 605 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 606 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 607 608Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 609^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 610 611The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 612boot Linux with 4 CPUs using the AArch32 build of TF-A. 613 614.. code:: shell 615 616 <path-to>/FVP_Base_Cortex-A32x4 \ 617 -C pctl.startup=0.0.0.0 \ 618 -C bp.secure_memory=1 \ 619 -C bp.tzc_400.diagnostics=1 \ 620 -C cache_state_modelled=1 \ 621 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 622 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 623 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 624 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 625 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 626 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 627 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 628 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 629 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 630 631-------------- 632 633*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 634 635.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts 636.. _Arm's website: `FVP models`_ 637.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 638.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01 639.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 640
