1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL2_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL2_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29
30#if ENABLE_RME
31        *bl2_rme_entrypoint.o(.text*)
32#else /* ENABLE_RME */
33        *bl2_entrypoint.o(.text*)
34#endif /* ENABLE_RME */
35
36        *(SORT_BY_ALIGNMENT(.text*))
37        *(.vectors)
38        __TEXT_END_UNALIGNED__ = .;
39
40        . = ALIGN(PAGE_SIZE);
41
42        __TEXT_END__ = .;
43    } >RAM
44
45    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
46    .ARM.extab . : {
47        *(.ARM.extab* .gnu.linkonce.armextab.*)
48    } >RAM
49
50    .ARM.exidx . : {
51        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
52    } >RAM
53
54    .rodata . : {
55        __RODATA_START__ = .;
56
57        *(SORT_BY_ALIGNMENT(.rodata*))
58
59        RODATA_COMMON
60
61        __RODATA_END_UNALIGNED__ = .;
62        . = ALIGN(PAGE_SIZE);
63
64        __RODATA_END__ = .;
65    } >RAM
66#else /* SEPARATE_CODE_AND_RODATA */
67    .ro . : {
68        __RO_START__ = .;
69
70        *bl2_entrypoint.o(.text*)
71        *(SORT_BY_ALIGNMENT(.text*))
72        *(SORT_BY_ALIGNMENT(.rodata*))
73
74        RODATA_COMMON
75
76        *(.vectors)
77
78        __RO_END_UNALIGNED__ = .;
79
80        /*
81         * Memory page(s) mapped to this section will be marked as read-only,
82         * executable. No RW data from the next section must creep in. Ensure
83         * that the rest of the current memory page is unused.
84         */
85        . = ALIGN(PAGE_SIZE);
86
87        __RO_END__ = .;
88    } >RAM
89#endif /* SEPARATE_CODE_AND_RODATA */
90
91    __RW_START__ = .;
92
93    DATA_SECTION >RAM
94    STACK_SECTION >RAM
95    BSS_SECTION >RAM
96    XLAT_TABLE_SECTION >RAM
97
98#if USE_COHERENT_MEM
99    /*
100     * The base address of the coherent memory section must be page-aligned to
101     * guarantee that the coherent data are stored on their own pages and are
102     * not mixed with normal data.  This is required to set up the correct
103     * memory attributes for the coherent data page tables.
104     */
105    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
106        __COHERENT_RAM_START__ = .;
107        *(.tzfw_coherent_mem)
108        __COHERENT_RAM_END_UNALIGNED__ = .;
109
110        /*
111         * Memory page(s) mapped to this section will be marked as device
112         * memory. No other unexpected data must creep in. Ensure the rest of
113         * the current memory page is unused.
114         */
115        . = ALIGN(PAGE_SIZE);
116
117        __COHERENT_RAM_END__ = .;
118    } >RAM
119#endif /* USE_COHERENT_MEM */
120
121    __RW_END__ = .;
122    __BL2_END__ = .;
123    RAM_REGION_END = .;
124
125    __BSS_SIZE__ = SIZEOF(.bss);
126
127#if USE_COHERENT_MEM
128    __COHERENT_RAM_UNALIGNED_SIZE__ =
129        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
130#endif /* USE_COHERENT_MEM */
131
132    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
133}
134