1 /*
2 * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /*
10 * Zynq UltraScale+ MPSoC IPI agent registers access management
11 */
12
13 #include <lib/utils_def.h>
14 #include <ipi.h>
15 #include <plat_ipi.h>
16
17 /* Zynqmp ipi configuration table */
18 static const struct ipi_config zynqmp_ipi_table[] = {
19 /* APU IPI */
20 {
21 .ipi_bit_mask = 0x1,
22 .ipi_reg_base = 0xFF300000U,
23 .secure_only = 0,
24 },
25 /* RPU0 IPI */
26 {
27 .ipi_bit_mask = 0x100,
28 .ipi_reg_base = 0xFF310000U,
29 .secure_only = 0,
30 },
31 /* RPU1 IPI */
32 {
33 .ipi_bit_mask = 0x200,
34 .ipi_reg_base = 0xFF320000U,
35 .secure_only = 0,
36 },
37 /* PMU0 IPI */
38 {
39 .ipi_bit_mask = 0x10000,
40 .ipi_reg_base = 0xFF330000U,
41 .secure_only = IPI_SECURE_MASK,
42 },
43 /* PMU1 IPI */
44 {
45 .ipi_bit_mask = 0x20000,
46 .ipi_reg_base = 0xFF331000U,
47 .secure_only = 0,
48 },
49 /* PMU2 IPI */
50 {
51 .ipi_bit_mask = 0x40000,
52 .ipi_reg_base = 0xFF332000U,
53 .secure_only = IPI_SECURE_MASK,
54 },
55 /* PMU3 IPI */
56 {
57 .ipi_bit_mask = 0x80000,
58 .ipi_reg_base = 0xFF333000U,
59 .secure_only = IPI_SECURE_MASK,
60 },
61 /* PL0 IPI */
62 {
63 .ipi_bit_mask = 0x1000000,
64 .ipi_reg_base = 0xFF340000U,
65 .secure_only = 0,
66 },
67 /* PL1 IPI */
68 {
69 .ipi_bit_mask = 0x2000000,
70 .ipi_reg_base = 0xFF350000U,
71 .secure_only = 0,
72 },
73 /* PL2 IPI */
74 {
75 .ipi_bit_mask = 0x4000000,
76 .ipi_reg_base = 0xFF360000U,
77 .secure_only = 0,
78 },
79 /* PL3 IPI */
80 {
81 .ipi_bit_mask = 0x8000000,
82 .ipi_reg_base = 0xFF370000U,
83 .secure_only = 0,
84 },
85 };
86
87 /**
88 * zynqmp_ipi_config_table_init() - Initialize ZynqMP IPI configuration data.
89 *
90 */
zynqmp_ipi_config_table_init(void)91 void zynqmp_ipi_config_table_init(void)
92 {
93 ipi_config_table_init(zynqmp_ipi_table, ARRAY_SIZE(zynqmp_ipi_table));
94 }
95
