1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
3# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4#
5# SPDX-License-Identifier: BSD-3-Clause
6
7PLAT_PATH := plat/xilinx/versal_net
8
9# A78 Erratum for SoC
10ERRATA_A78_AE_1941500 := 1
11ERRATA_A78_AE_1951502 := 1
12ERRATA_A78_AE_2376748 := 1
13ERRATA_A78_AE_2395408 := 1
14
15override PROGRAMMABLE_RESET_ADDRESS := 1
16PSCI_EXTENDED_STATE_ID := 1
17SEPARATE_CODE_AND_RODATA := 1
18override RESET_TO_BL31 := 1
19PL011_GENERIC_UART := 1
20IPI_CRC_CHECK := 0
21GIC_ENABLE_V4_EXTN :=  0
22GICV3_SUPPORT_GIC600 := 1
23TFA_NO_PM := 0
24
25override CTX_INCLUDE_AARCH32_REGS    := 0
26
27ifdef TFA_NO_PM
28   $(eval $(call add_define,TFA_NO_PM))
29endif
30
31ifdef VERSAL_NET_ATF_MEM_BASE
32    $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
33
34    ifndef VERSAL_NET_ATF_MEM_SIZE
35        $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
36    endif
37    $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
38
39    ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE
40        $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE))
41    endif
42endif
43
44ifdef VERSAL_NET_BL32_MEM_BASE
45    $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
46
47    ifndef VERSAL_NET_BL32_MEM_SIZE
48        $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
49    endif
50    $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
51endif
52
53ifdef IPI_CRC_CHECK
54    $(eval $(call add_define,IPI_CRC_CHECK))
55endif
56
57USE_COHERENT_MEM := 0
58HW_ASSISTED_COHERENCY := 1
59
60VERSAL_NET_CONSOLE	?=	pl011
61ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
62else
63  $(error Please define VERSAL_NET_CONSOLE)
64endif
65
66$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
67
68ifdef XILINX_OF_BOARD_DTB_ADDR
69$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
70endif
71
72# enable assert() for release/debug builds
73ENABLE_ASSERTIONS := 1
74
75PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
76				-Iplat/xilinx/common/include/			\
77				-Iplat/xilinx/common/ipi_mailbox_service/	\
78				-I${PLAT_PATH}/include/				\
79				-Iplat/xilinx/versal/pm_service/
80
81# Include GICv3 driver files
82include drivers/arm/gic/v3/gicv3.mk
83include lib/xlat_tables_v2/xlat_tables.mk
84include lib/libfdt/libfdt.mk
85
86PLAT_BL_COMMON_SOURCES	:=	\
87				drivers/arm/dcc/dcc_console.c			\
88				drivers/delay_timer/delay_timer.c		\
89				drivers/delay_timer/generic_delay_timer.c	\
90				${GICV3_SOURCES}				\
91				drivers/arm/pl011/aarch64/pl011_console.S	\
92				plat/common/aarch64/crash_console_helpers.S	\
93				plat/arm/common/arm_common.c			\
94				plat/common/plat_gicv3.c			\
95				${PLAT_PATH}/aarch64/versal_net_helpers.S	\
96				${PLAT_PATH}/aarch64/versal_net_common.c
97
98BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
99				lib/cpus/aarch64/cortex_a78_ae.S		\
100				lib/cpus/aarch64/cortex_a78.S			\
101				plat/common/plat_psci_common.c
102ifeq ($(TFA_NO_PM), 0)
103BL31_SOURCES		+=	plat/xilinx/common/pm_service/pm_api_sys.c	\
104				plat/xilinx/common/pm_service/pm_ipi.c		\
105				${PLAT_PATH}/plat_psci_pm.c			\
106				plat/xilinx/common/pm_service/pm_svc_main.c	\
107				${PLAT_PATH}/pm_service/pm_client.c		\
108				${PLAT_PATH}/versal_net_ipi.c
109else
110BL31_SOURCES		+=	${PLAT_PATH}/plat_psci.c
111endif
112BL31_SOURCES		+=	plat/xilinx/common/plat_fdt.c			\
113				plat/xilinx/common/plat_startup.c		\
114				plat/xilinx/common/plat_console.c		\
115				plat/xilinx/common/ipi.c			\
116				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
117				plat/xilinx/common/versal.c			\
118				${PLAT_PATH}/bl31_versal_net_setup.c		\
119				${PLAT_PATH}/plat_topology.c			\
120				common/fdt_fixup.c				\
121				common/fdt_wrappers.c				\
122				${LIBFDT_SRCS}					\
123				${PLAT_PATH}/sip_svc_setup.c			\
124				${PLAT_PATH}/versal_net_gicv3.c			\
125				${XLAT_TABLES_LIB_SRCS}
126