1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <rk3328_def.h> 14 15 /******************************************************************************* 16 * Platform binary types for linking 17 ******************************************************************************/ 18 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 19 #define PLATFORM_LINKER_ARCH aarch64 20 21 /******************************************************************************* 22 * Generic platform constants 23 ******************************************************************************/ 24 25 /* Size of cacheable stacks */ 26 #if defined(IMAGE_BL1) 27 #define PLATFORM_STACK_SIZE 0x440 28 #elif defined(IMAGE_BL2) 29 #define PLATFORM_STACK_SIZE 0x400 30 #elif defined(IMAGE_BL31) 31 #define PLATFORM_STACK_SIZE 0x800 32 #elif defined(IMAGE_BL32) 33 #define PLATFORM_STACK_SIZE 0x440 34 #endif 35 36 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 37 38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 39 #define PLATFORM_SYSTEM_COUNT 1 40 #define PLATFORM_CLUSTER_COUNT U(1) 41 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 42 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 43 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 44 PLATFORM_CLUSTER0_CORE_COUNT) 45 46 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 47 PLATFORM_CLUSTER_COUNT + \ 48 PLATFORM_CORE_COUNT) 49 50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 51 52 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 53 54 /* 55 * This macro defines the deepest retention state possible. A higher state 56 * id will represent an invalid or a power down state. 57 */ 58 #define PLAT_MAX_RET_STATE U(1) 59 60 /* 61 * This macro defines the deepest power down states possible. Any state ID 62 * higher than this is invalid. 63 */ 64 #define PLAT_MAX_OFF_STATE U(2) 65 66 /******************************************************************************* 67 * Platform memory map related constants 68 ******************************************************************************/ 69 /* TF text, ro, rw, Size: 1MB */ 70 #define TZRAM_BASE (0x0) 71 #define TZRAM_SIZE (0x100000) 72 73 /******************************************************************************* 74 * BL31 specific defines. 75 ******************************************************************************/ 76 /* 77 * Put BL3-1 at the top of the Trusted RAM 78 */ 79 #define BL31_BASE (TZRAM_BASE + 0x40000) 80 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 81 82 /******************************************************************************* 83 * Platform specific page table and MMU setup constants 84 ******************************************************************************/ 85 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 86 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 87 #define MAX_XLAT_TABLES 9 88 #define MAX_MMAP_REGIONS 33 89 90 /******************************************************************************* 91 * Declarations and constants to access the mailboxes safely. Each mailbox is 92 * aligned on the biggest cache line size in the platform. This is known only 93 * to the platform as it might have a combination of integrated and external 94 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 95 * line at any cache level. They could belong to different cpus/clusters & 96 * get written while being protected by different locks causing corruption of 97 * a valid mailbox address. 98 ******************************************************************************/ 99 #define CACHE_WRITEBACK_SHIFT 6 100 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 101 102 /* 103 * Define GICD and GICC and GICR base 104 */ 105 #define PLAT_RK_GICD_BASE RK3328_GICD_BASE 106 #define PLAT_RK_GICC_BASE RK3328_GICC_BASE 107 108 #define PLAT_RK_UART_BASE UART2_BASE 109 #define PLAT_RK_UART_CLOCK RK3328_UART_CLOCK 110 #define PLAT_RK_UART_BAUDRATE RK3328_BAUDRATE 111 112 #define PLAT_RK_PRIMARY_CPU 0x0 113 114 #define PSRAM_DO_DDR_RESUME 0 115 #define PSRAM_CHECK_WAKEUP_CPU 0 116 117 #endif /* PLATFORM_DEF_H */ 118
