1 /*
2  * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <common/debug.h>
8 #include <mtk_dcm.h>
9 #include <mtk_dcm_utils.h>
10 
dcm_armcore(bool mode)11 static void dcm_armcore(bool mode)
12 {
13 	dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
14 	dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
15 	dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
16 }
17 
dcm_mcusys(bool on)18 static void dcm_mcusys(bool on)
19 {
20 	dcm_mp_cpusys_top_adb_dcm(on);
21 	dcm_mp_cpusys_top_apb_dcm(on);
22 	dcm_mp_cpusys_top_cpubiu_dcm(on);
23 	dcm_mp_cpusys_top_cpubiu_dbg_cg(on);
24 	dcm_mp_cpusys_top_misc_dcm(on);
25 	dcm_mp_cpusys_top_mp0_qdcm(on);
26 	dcm_cpccfg_reg_emi_wfifo(on);
27 	dcm_mp_cpusys_top_last_cor_idle_dcm(on);
28 }
29 
dcm_stall(bool on)30 static void dcm_stall(bool on)
31 {
32 	dcm_mp_cpusys_top_core_stall_dcm(on);
33 	dcm_mp_cpusys_top_fcm_stall_dcm(on);
34 }
35 
check_dcm_state(void)36 static bool check_dcm_state(void)
37 {
38 	bool ret = true;
39 
40 	ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
41 	ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
42 	ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
43 
44 	ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
45 	ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
46 	ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
47 	ret &= dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on();
48 	ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
49 	ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
50 	ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
51 	ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
52 
53 	ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
54 	ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
55 
56 	return ret;
57 }
58 
dcm_set_default(void)59 void dcm_set_default(void)
60 {
61 	dcm_armcore(true);
62 	dcm_mcusys(true);
63 	dcm_stall(true);
64 
65 	INFO("%s: %d", __func__, check_dcm_state());
66 }
67