1 /*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <lib/bakery_lock.h>
7 #include <common/debug.h>
8 #include <drivers/delay_timer.h>
9 #include <lib/mmio.h>
10 #include <spm.h>
11 #include <spm_pmic_wrap.h>
12
13 DEFINE_BAKERY_LOCK(spm_lock);
14
15 /* SPM_DVS_LEVEL */
16 #define SPM_VMODEM_LEVEL_MASK (0xff << 16)
17 #define SPM_VMODEM_LEVEL (1U << 18)
18 #define SPM_VCORE_LEVEL_MASK (0xff)
19 #define SPM_VCORE_LEVEL (1U << 1)
20
21 /* CLK_SCP_CFG_0 */
22 #define SPM_CK_OFF_CONTROL (0x3FF)
23
24 /* CLK_SCP_CFG_1 */
25 #define SPM_AXI_26M_SEL (0x1)
26
27 /* AP_PLL_CON3 */
28 #define SPM_PLL_CONTROL (0x7FAAAAF)
29
30 /* AP_PLL_CON4 */
31 #define SPM_PLL_OUT_OFF_CONTROL (0xFA0A)
32
33 /* AP_PLL_CON6 */
34 #define PLL_DLY (0x20000)
35
36 const char *wakeup_src_str[32] = {
37 [0] = "R12_PCM_TIMER",
38 [1] = "R12_SSPM_WDT_EVENT_B",
39 [2] = "R12_KP_IRQ_B",
40 [3] = "R12_APWDT_EVENT_B",
41 [4] = "R12_APXGPT1_EVENT_B",
42 [5] = "R12_CONN2AP_SPM_WAKEUP_B",
43 [6] = "R12_EINT_EVENT_B",
44 [7] = "R12_CONN_WDT_IRQ_B",
45 [8] = "R12_CCIF0_EVENT_B",
46 [9] = "R12_LOWBATTERY_IRQ_B",
47 [10] = "R12_SSPM_SPM_IRQ_B",
48 [11] = "R12_SCP_SPM_IRQ_B",
49 [12] = "R12_SCP_WDT_EVENT_B",
50 [13] = "R12_PCM_WDT_WAKEUP_B",
51 [14] = "R12_USB_CDSC_B ",
52 [15] = "R12_USB_POWERDWN_B",
53 [16] = "R12_SYS_TIMER_EVENT_B",
54 [17] = "R12_EINT_EVENT_SECURE_B",
55 [18] = "R12_CCIF1_EVENT_B",
56 [19] = "R12_UART0_IRQ_B",
57 [20] = "R12_AFE_IRQ_MCU_B",
58 [21] = "R12_THERM_CTRL_EVENT_B",
59 [22] = "R12_SYS_CIRQ_IRQ_B",
60 [23] = "R12_MD2AP_PEER_EVENT_B",
61 [24] = "R12_CSYSPWREQ_B",
62 [25] = "R12_MD1_WDT_B ",
63 [26] = "R12_CLDMA_EVENT_B",
64 [27] = "R12_SEJ_WDT_GPT_B",
65 [28] = "R12_ALL_SSPM_WAKEUP_B",
66 [29] = "R12_CPU_IRQ_B",
67 [30] = "R12_CPU_WFI_AND_B"
68 };
69
spm_get_firmware_version(void)70 const char *spm_get_firmware_version(void)
71 {
72 return "DYNAMIC_SPM_FW_VERSION";
73 }
74
spm_lock_init(void)75 void spm_lock_init(void)
76 {
77 bakery_lock_init(&spm_lock);
78 }
79
spm_lock_get(void)80 void spm_lock_get(void)
81 {
82 bakery_lock_get(&spm_lock);
83 }
84
spm_lock_release(void)85 void spm_lock_release(void)
86 {
87 bakery_lock_release(&spm_lock);
88 }
89
spm_set_bootaddr(unsigned long bootaddr)90 void spm_set_bootaddr(unsigned long bootaddr)
91 {
92 /* initialize core4~7 boot entry address */
93 mmio_write_32(SW2SPM_MAILBOX_3, bootaddr);
94 }
95
spm_set_cpu_status(int cpu)96 void spm_set_cpu_status(int cpu)
97 {
98 if (cpu >= 0 && cpu < 4) {
99 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204);
100 mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4));
101 } else if (cpu >= 4 && cpu < 8) {
102 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218);
103 mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4));
104 } else {
105 ERROR("%s: error cpu number %d\n", __func__, cpu);
106 }
107 }
108
spm_set_power_control(const struct pwr_ctrl * pwrctrl)109 void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
110 {
111 mmio_write_32(SPM_AP_STANDBY_CON,
112 ((pwrctrl->wfi_op & 0x1) << 0) |
113 ((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) |
114 ((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) |
115 ((pwrctrl->mcusys_idle_mask & 0x1) << 4) |
116 ((pwrctrl->mm_mask_b & 0x3) << 16) |
117 ((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) |
118 ((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) |
119 ((pwrctrl->md_mask_b & 0x3) << 20) |
120 ((pwrctrl->sspm_mask_b & 0x1) << 22) |
121 ((pwrctrl->scp_mask_b & 0x1) << 23) |
122 ((pwrctrl->srcclkeni_mask_b & 0x1) << 24) |
123 ((pwrctrl->md_apsrc_1_sel & 0x1) << 25) |
124 ((pwrctrl->md_apsrc_0_sel & 0x1) << 26) |
125 ((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) |
126 ((pwrctrl->conn_mask_b & 0x1) << 28) |
127 ((pwrctrl->conn_apsrc_sel & 0x1) << 29));
128
129 mmio_write_32(SPM_SRC_REQ,
130 ((pwrctrl->spm_apsrc_req & 0x1) << 0) |
131 ((pwrctrl->spm_f26m_req & 0x1) << 1) |
132 ((pwrctrl->spm_infra_req & 0x1) << 3) |
133 ((pwrctrl->spm_vrf18_req & 0x1) << 4) |
134 ((pwrctrl->spm_ddren_req & 0x1) << 7) |
135 ((pwrctrl->spm_rsv_src_req & 0x7) << 8) |
136 ((pwrctrl->spm_ddren_2_req & 0x1) << 11) |
137 ((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16));
138
139 mmio_write_32(SPM_SRC_MASK,
140 ((pwrctrl->csyspwreq_mask & 0x1) << 0) |
141 ((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) |
142 ((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) |
143 ((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) |
144 ((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) |
145 ((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) |
146 ((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) |
147 ((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) |
148 ((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) |
149 ((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) |
150 ((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) |
151 ((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) |
152 ((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) |
153 ((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) |
154 ((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) |
155 ((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) |
156 ((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) |
157 ((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) |
158 ((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) |
159 ((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) |
160 ((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) |
161 ((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) |
162 ((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) |
163 ((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) |
164 ((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) |
165 ((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) |
166 ((pwrctrl->mfg_req_mask_b & 0x1) << 26) |
167 ((pwrctrl->vdec_req_mask_b & 0x1) << 27));
168
169 mmio_write_32(SPM_SRC2_MASK,
170 ((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) |
171 ((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) |
172 ((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) |
173 ((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) |
174 ((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) |
175 ((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) |
176 ((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) |
177 ((pwrctrl->gce_ddren_mask_b & 0x1) << 7) |
178 ((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1)
179 << 8) |
180 ((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1)
181 << 9));
182
183 mmio_write_32(SPM_WAKEUP_EVENT_MASK,
184 ((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0));
185
186 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
187 ((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff)
188 << 0));
189
190 mmio_write_32(SPM_SRC3_MASK,
191 ((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) |
192 ((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) |
193 ((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) |
194 ((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) |
195 ((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) |
196 ((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) |
197 ((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) |
198 ((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) |
199 ((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1)
200 << 8) |
201 ((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1)
202 << 9));
203
204 mmio_write_32(MP0_CPU0_WFI_EN,
205 ((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0));
206 mmio_write_32(MP0_CPU1_WFI_EN,
207 ((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0));
208 mmio_write_32(MP0_CPU2_WFI_EN,
209 ((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0));
210 mmio_write_32(MP0_CPU3_WFI_EN,
211 ((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0));
212
213 mmio_write_32(MP1_CPU0_WFI_EN,
214 ((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0));
215 mmio_write_32(MP1_CPU1_WFI_EN,
216 ((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0));
217 mmio_write_32(MP1_CPU2_WFI_EN,
218 ((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0));
219 mmio_write_32(MP1_CPU3_WFI_EN,
220 ((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0));
221 }
222
spm_disable_pcm_timer(void)223 void spm_disable_pcm_timer(void)
224 {
225 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
226 }
227
spm_set_wakeup_event(const struct pwr_ctrl * pwrctrl)228 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
229 {
230 uint32_t val, mask, isr;
231
232 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
233 mmio_write_32(PCM_TIMER_VAL, val);
234 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB);
235
236 mask = pwrctrl->wake_src;
237
238 if (pwrctrl->csyspwreq_mask)
239 mask &= ~WAKE_SRC_R12_CSYSPWREQ_B;
240
241 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
242
243 isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB;
244 mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX);
245 }
246
spm_set_pcm_flags(const struct pwr_ctrl * pwrctrl)247 void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
248 {
249 mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags);
250 mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1);
251 }
252
spm_set_pcm_wdt(int en)253 void spm_set_pcm_wdt(int en)
254 {
255 if (en) {
256 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB,
257 SPM_REGWR_CFG_KEY);
258
259 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX)
260 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
261 mmio_write_32(PCM_WDT_VAL,
262 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
263 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB);
264 } else {
265 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB,
266 SPM_REGWR_CFG_KEY);
267 }
268 }
269
spm_send_cpu_wakeup_event(void)270 void spm_send_cpu_wakeup_event(void)
271 {
272 mmio_write_32(PCM_REG_DATA_INI, 0);
273 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
274 }
275
spm_get_wakeup_status(struct wake_status * wakesta)276 void spm_get_wakeup_status(struct wake_status *wakesta)
277 {
278 wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI);
279 wakesta->r12 = mmio_read_32(SPM_SW_RSV_0);
280 wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA);
281 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
282 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
283 wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR);
284 wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR);
285 wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
286 wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
287 wakesta->req_sta = mmio_read_32(SRC_REQ_STA);
288 wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG);
289 wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2);
290 wakesta->r15 = mmio_read_32(PCM_REG15_DATA);
291 wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG);
292 wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX);
293 wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR);
294 wakesta->isr = mmio_read_32(SPM_IRQ_STA);
295 }
296
spm_clean_after_wakeup(void)297 void spm_clean_after_wakeup(void)
298 {
299 mmio_write_32(SPM_SW_RSV_0,
300 mmio_read_32(SPM_WAKEUP_STA) |
301 mmio_read_32(SPM_SW_RSV_0));
302 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
303 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0);
304 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
305 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
306 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
307 }
308
spm_output_wake_reason(struct wake_status * wakesta,const char * scenario)309 void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario)
310 {
311 uint32_t i;
312
313 if (wakesta->assert_pc != 0) {
314 INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n",
315 scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON));
316 goto spm_debug_flags;
317 }
318
319 for (i = 0; i <= 31; i++) {
320 if (wakesta->r12 & (1U << i)) {
321 INFO("%s: wake up by %s, timer_out = %u\n",
322 scenario, wakeup_src_str[i], wakesta->timer_out);
323 break;
324 }
325 }
326
327 spm_debug_flags:
328 INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
329 wakesta->r15, wakesta->r13, wakesta->debug_flag,
330 wakesta->debug_flag1);
331 INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n",
332 wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12,
333 wakesta->r12_ext);
334 INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n",
335 wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg);
336 INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n",
337 wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta);
338 INFO("wake_misc = 0x%x\n", wakesta->wake_misc);
339 }
340
spm_boot_init(void)341 void spm_boot_init(void)
342 {
343 NOTICE("%s() start\n", __func__);
344
345 spm_lock_init();
346 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
347
348 /* Set Vmodem / Vcore DVS init level */
349 mmio_clrsetbits_32(SPM_DVS_LEVEL,
350 SPM_VMODEM_LEVEL_MASK | SPM_VCORE_LEVEL_MASK,
351 SPM_VMODEM_LEVEL | SPM_VCORE_LEVEL);
352
353 /* switch ck_off/axi_26m control to SPM */
354 mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
355 mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
356
357 /* switch PLL/CLKSQ control to SPM */
358 mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
359 mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
360 mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
361
362 NOTICE("%s() end\n", __func__);
363 }
364
