1 /*
2  * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLAT_SOCFPGA_DEF_H
8 #define PLAT_SOCFPGA_DEF_H
9 
10 #include <platform_def.h>
11 #include "s10_system_manager.h"
12 
13 /* Platform Setting */
14 #define PLATFORM_MODEL						PLAT_SOCFPGA_STRATIX10
15 #define BOOT_SOURCE							BOOT_SOURCE_SDMMC
16 #define PLAT_PRIMARY_CPU					0
17 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT		MPIDR_AFF1_SHIFT
18 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT			MPIDR_AFF0_SHIFT
19 
20 /* FPGA config helpers */
21 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR		0x400000
22 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE		0x1000000
23 
24 /* QSPI Setting */
25 #define CAD_QSPIDATA_OFST			0xff900000
26 #define CAD_QSPI_OFFSET				0xff8d2000
27 
28 /* Register Mapping */
29 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
30 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)
31 
32 #define SOCFPGA_MMC_REG_BASE                    0xff808000
33 
34 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
35 #define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
36 
37 #define SOCFPGA_L4_PER_SCR_REG_BASE		0xffd21000
38 #define SOCFPGA_L4_SYS_SCR_REG_BASE		0xffd21100
39 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE		0xffd21200
40 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		0xffd21300
41 
42 /*******************************************************************************
43  * Platform memory map related constants
44  ******************************************************************************/
45 #define DRAM_BASE				(0x0)
46 #define DRAM_SIZE				(0x80000000)
47 
48 #define OCRAM_BASE				(0xFFE00000)
49 #define OCRAM_SIZE				(0x00040000)
50 
51 #define MEM64_BASE				(0x0100000000)
52 #define MEM64_SIZE				(0x1F00000000)
53 
54 #define DEVICE1_BASE				(0x80000000)
55 #define DEVICE1_SIZE				(0x60000000)
56 
57 #define DEVICE2_BASE				(0xF7000000)
58 #define DEVICE2_SIZE				(0x08E00000)
59 
60 #define DEVICE3_BASE				(0xFFFC0000)
61 #define DEVICE3_SIZE				(0x00008000)
62 
63 #define DEVICE4_BASE				(0x2000000000)
64 #define DEVICE4_SIZE				(0x0100000000)
65 
66 #define BL2_BASE		(0xffe00000)
67 #define BL2_LIMIT		(0xffe1b000)
68 
69 #define BL31_BASE		(0x1000)
70 #define BL31_LIMIT		(0x81000)
71 
72 /*******************************************************************************
73  * UART related constants
74  ******************************************************************************/
75 #define PLAT_UART0_BASE		(0xFFC02000)
76 #define PLAT_UART1_BASE		(0xFFC02100)
77 
78 /*******************************************************************************
79  * GIC related constants
80  ******************************************************************************/
81 #define PLAT_GIC_BASE			(0xFFFC0000)
82 #define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
83 #define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
84 #define PLAT_GICR_BASE			0
85 
86 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
87 #define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
88 
89 /*******************************************************************************
90  * SDMMC related pointer function
91  ******************************************************************************/
92 #define SDMMC_READ_BLOCKS	mmc_read_blocks
93 #define SDMMC_WRITE_BLOCKS	mmc_write_blocks
94 
95 /*******************************************************************************
96  * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
97  * is done and HPS should trigger warm reset via RMR_EL3.
98  ******************************************************************************/
99 #define L2_RESET_DONE_REG			0xFFD12218
100 
101 /* Platform specific system counter */
102 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ	get_cpu_clk()
103 
104 #endif /* PLATSOCFPGA_DEF_H */
105 
106