1 /*
2  * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef PLAT_SOCFPGA_DEF_H
9 #define PLAT_SOCFPGA_DEF_H
10 
11 #include "agilex_system_manager.h"
12 #include <platform_def.h>
13 
14 /* Platform Setting */
15 #define PLATFORM_MODEL						PLAT_SOCFPGA_AGILEX
16 #define BOOT_SOURCE							BOOT_SOURCE_SDMMC
17 #define PLAT_PRIMARY_CPU					0
18 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT		MPIDR_AFF1_SHIFT
19 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT			MPIDR_AFF0_SHIFT
20 
21 /* FPGA config helpers */
22 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR		0x400000
23 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE		0x2000000
24 
25 /* QSPI Setting */
26 #define CAD_QSPIDATA_OFST			0xff900000
27 #define CAD_QSPI_OFFSET				0xff8d2000
28 
29 /* Register Mapping */
30 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
31 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)
32 
33 #define SOCFPGA_MMC_REG_BASE			0xff808000
34 #define SOCFPGA_MEMCTRL_REG_BASE		0xf8011100
35 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
36 #define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
37 
38 #define SOCFPGA_L4_PER_SCR_REG_BASE             0xffd21000
39 #define SOCFPGA_L4_SYS_SCR_REG_BASE             0xffd21100
40 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE           0xffd21200
41 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE         0xffd21300
42 
43 /*******************************************************************************
44  * Platform memory map related constants
45  ******************************************************************************/
46 #define DRAM_BASE				(0x0)
47 #define DRAM_SIZE				(0x80000000)
48 
49 #define OCRAM_BASE				(0xFFE00000)
50 #define OCRAM_SIZE				(0x00040000)
51 
52 #define MEM64_BASE				(0x0100000000)
53 #define MEM64_SIZE				(0x1F00000000)
54 
55 #define DEVICE1_BASE				(0x80000000)
56 #define DEVICE1_SIZE				(0x60000000)
57 
58 #define DEVICE2_BASE				(0xF7000000)
59 #define DEVICE2_SIZE				(0x08E00000)
60 
61 #define DEVICE3_BASE				(0xFFFC0000)
62 #define DEVICE3_SIZE				(0x00008000)
63 
64 #define DEVICE4_BASE				(0x2000000000)
65 #define DEVICE4_SIZE				(0x0100000000)
66 
67 #define BL2_BASE		(0xffe00000)
68 #define BL2_LIMIT		(0xffe1b000)
69 
70 #define BL31_BASE		(0x1000)
71 #define BL31_LIMIT		(0x81000)
72 
73 /*******************************************************************************
74  * UART related constants
75  ******************************************************************************/
76 #define PLAT_UART0_BASE		(0xFFC02000)
77 #define PLAT_UART1_BASE		(0xFFC02100)
78 
79 /*******************************************************************************
80  * GIC related constants
81  ******************************************************************************/
82 #define PLAT_GIC_BASE			(0xFFFC0000)
83 #define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
84 #define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
85 #define PLAT_GICR_BASE			0
86 
87 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
88 #define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
89 
90 /*******************************************************************************
91  * SDMMC related pointer function
92  ******************************************************************************/
93 #define SDMMC_READ_BLOCKS	mmc_read_blocks
94 #define SDMMC_WRITE_BLOCKS	mmc_write_blocks
95 
96 /*******************************************************************************
97  * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
98  * is done and HPS should trigger warm reset via RMR_EL3.
99  ******************************************************************************/
100 #define L2_RESET_DONE_REG			0xFFD12218
101 
102 /* Platform specific system counter */
103 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ	get_cpu_clk()
104 
105 #endif /* PLAT_SOCFPGA_DEF_H */
106