1 /*
2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <inttypes.h>
9 #include <stdint.h>
10 #include <stdbool.h>
11
12 #include <platform_def.h>
13
14 #include <arch_helpers.h>
15 #include <context.h>
16 #include <common/bl_common.h>
17 #include <common/debug.h>
18 #include <drivers/arm/cci.h>
19 #include <drivers/console.h>
20 #include <lib/el3_runtime/context_mgmt.h>
21 #include <lib/mmio.h>
22 #include <lib/xlat_tables/xlat_tables_v2.h>
23 #include <plat/common/platform.h>
24
25 #include <imx8qm_pads.h>
26 #include <imx8_iomux.h>
27 #include <imx8_lpuart.h>
28 #include <plat_imx8.h>
29 #include <sci/sci.h>
30 #include <sec_rsrc.h>
31
32 static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
33 static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
34 static const unsigned long BL31_RO_START = BL_CODE_BASE;
35 static const unsigned long BL31_RO_END = BL_CODE_END;
36 static const unsigned long BL31_RW_END = BL_END;
37
38 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
39
40 static entry_point_info_t bl32_image_ep_info;
41 static entry_point_info_t bl33_image_ep_info;
42
43 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
44 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
45 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
46 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
47 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
48
49 #if defined(IMX_USE_UART0)
50 #define IMX_RES_UART SC_R_UART_0
51 #define IMX_PAD_UART_RX SC_P_UART0_RX
52 #define IMX_PAD_UART_TX SC_P_UART0_TX
53 #define IMX_PAD_UART_RTS_B SC_P_UART0_RTS_B
54 #define IMX_PAD_UART_CTS_B SC_P_UART0_CTS_B
55 #elif defined(IMX_USE_UART1)
56 #define IMX_RES_UART SC_R_UART_1
57 #define IMX_PAD_UART_RX SC_P_UART1_RX
58 #define IMX_PAD_UART_TX SC_P_UART1_TX
59 #define IMX_PAD_UART_RTS_B SC_P_UART1_RTS_B
60 #define IMX_PAD_UART_CTS_B SC_P_UART1_CTS_B
61 #else
62 #error "Provide proper UART number in IMX_DEBUG_UART"
63 #endif
64
65 static const int imx8qm_cci_map[] = {
66 CLUSTER0_CCI_SLVAE_IFACE,
67 CLUSTER1_CCI_SLVAE_IFACE
68 };
69
70 static const mmap_region_t imx_mmap[] = {
71 MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW),
72 {0}
73 };
74
get_spsr_for_bl33_entry(void)75 static uint32_t get_spsr_for_bl33_entry(void)
76 {
77 unsigned long el_status;
78 unsigned long mode;
79 uint32_t spsr;
80
81 /* figure out what mode we enter the non-secure world */
82 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
83 el_status &= ID_AA64PFR0_ELX_MASK;
84
85 mode = (el_status) ? MODE_EL2 : MODE_EL1;
86 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
87
88 return spsr;
89 }
90
91 #if DEBUG_CONSOLE_A53
lpuart32_serial_setbrg(unsigned int base,int baudrate)92 static void lpuart32_serial_setbrg(unsigned int base, int baudrate)
93 {
94 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr;
95 unsigned int diff1, diff2, tmp, rate;
96
97 if (baudrate == 0)
98 panic();
99
100 sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
101
102 baud_diff = baudrate;
103 osr = 0;
104 sbr = 0;
105 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
106 tmp_sbr = (rate / (baudrate * tmp_osr));
107 if (tmp_sbr == 0)
108 tmp_sbr = 1;
109
110 /* calculate difference in actual baud w/ current values */
111 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate;
112 diff2 = rate / (tmp_osr * (tmp_sbr + 1));
113
114 /* select best values between sbr and sbr+1 */
115 if (diff1 > (baudrate - diff2)) {
116 diff1 = baudrate - diff2;
117 tmp_sbr++;
118 }
119
120 if (diff1 <= baud_diff) {
121 baud_diff = diff1;
122 osr = tmp_osr;
123 sbr = tmp_sbr;
124 }
125 }
126
127 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD);
128
129 if ((osr > 3) && (osr < 8))
130 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
131
132 tmp &= ~LPUART_BAUD_OSR_MASK;
133 tmp |= LPUART_BAUD_OSR(osr - 1);
134 tmp &= ~LPUART_BAUD_SBR_MASK;
135 tmp |= LPUART_BAUD_SBR(sbr);
136
137 /* explicitly disable 10 bit mode & set 1 stop bit */
138 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
139
140 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp);
141 }
142
lpuart32_serial_init(unsigned int base)143 static int lpuart32_serial_init(unsigned int base)
144 {
145 unsigned int tmp;
146
147 /* disable TX & RX before enabling clocks */
148 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
149 tmp &= ~(CTRL_TE | CTRL_RE);
150 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
151
152 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0);
153 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE));
154
155 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0);
156
157 /* provide data bits, parity, stop bit, etc */
158 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE);
159
160 /* eight data bits no parity bit */
161 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
162 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
163 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
164
165 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE);
166
167 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
168 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
169 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A);
170
171 return 0;
172 }
173 #endif
174
mx8_partition_resources(void)175 void mx8_partition_resources(void)
176 {
177 sc_rm_pt_t secure_part, os_part;
178 sc_rm_mr_t mr, mr_record = 64;
179 sc_faddr_t start, end;
180 bool owned, owned2;
181 sc_err_t err;
182 int i;
183
184 err = sc_rm_get_partition(ipc_handle, &secure_part);
185
186 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false,
187 false, false, false);
188
189 err = sc_rm_set_parent(ipc_handle, os_part, secure_part);
190
191 /* set secure resources to NOT-movable */
192 for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) {
193 err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i],
194 secure_rsrcs[i], false);
195 if (err)
196 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
197 secure_rsrcs[i], err);
198 }
199
200 owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0);
201 if (owned) {
202 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,
203 SC_R_M4_0_PID0, false);
204 if (err)
205 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
206 SC_R_M4_0_PID0, err);
207 }
208
209 owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0);
210 if (owned2) {
211 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,
212 SC_R_M4_1_PID0, false);
213 if (err)
214 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
215 SC_R_M4_1_PID0, err);
216 }
217 /* move all movable resources and pins to non-secure partition */
218 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);
219 if (err)
220 ERROR("sc_rm_move_all: %u\n", err);
221
222 /* iterate through peripherals to give NS OS part access */
223 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) {
224 err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i],
225 os_part, SC_RM_PERM_FULL);
226 if (err)
227 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \
228 ret %u\n", ns_access_allowed[i], err);
229 }
230
231 if (owned) {
232 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,
233 SC_R_M4_0_PID0, true);
234 if (err)
235 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
236 SC_R_M4_0_PID0, err);
237 err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0);
238 if (err)
239 ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n",
240 SC_R_M4_0_PID0, err);
241 }
242 if (owned2) {
243 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,
244 SC_R_M4_1_PID0, true);
245 if (err)
246 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
247 SC_R_M4_1_PID0, err);
248 err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0);
249 if (err)
250 ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n",
251 SC_R_M4_1_PID0, err);
252 }
253
254 /*
255 * sc_rm_set_peripheral_permissions
256 * sc_rm_set_memreg_permissions
257 * sc_rm_set_pin_movable
258 */
259
260 for (mr = 0; mr < 64; mr++) {
261 owned = sc_rm_is_memreg_owned(ipc_handle, mr);
262 if (owned) {
263 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);
264 if (err)
265 ERROR("Memreg get info failed, %u\n", mr);
266 NOTICE("Memreg %u 0x%" PRIx64 " -- 0x%" PRIx64 "\n", mr, start, end);
267 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
268 mr_record = mr; /* Record the mr for ATF running */
269 } else {
270 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
271 if (err)
272 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 ", \
273 err %d\n", start, end, err);
274 }
275 }
276 }
277
278 if (mr_record != 64) {
279 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end);
280 if (err)
281 ERROR("Memreg get info failed, %u\n", mr_record);
282 if ((BL31_LIMIT - 1) < end) {
283 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
284 if (err)
285 ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
286 (sc_faddr_t)BL31_LIMIT, end);
287 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
288 if (err)
289 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
290 (sc_faddr_t)BL31_LIMIT, end);
291 }
292
293 if (start < (BL31_BASE - 1)) {
294 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
295 if (err)
296 ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
297 start, (sc_faddr_t)BL31_BASE - 1);
298 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
299 if (err)
300 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
301 start, (sc_faddr_t)BL31_BASE - 1);
302 }
303 }
304
305 if (err)
306 NOTICE("Partitioning Failed\n");
307 else
308 NOTICE("Non-secure Partitioning Succeeded\n");
309
310 }
311
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)312 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
313 u_register_t arg2, u_register_t arg3)
314 {
315 #if DEBUG_CONSOLE
316 static console_t console;
317 #endif
318 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
319 panic();
320
321 #if DEBUG_CONSOLE_A53
322 sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART,
323 SC_PM_PW_MODE_ON);
324 sc_pm_clock_rate_t rate = 80000000;
325 sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
326 sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false);
327
328 /* configure UART pads */
329 sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL);
330 sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL);
331 sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL);
332 sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL);
333 lpuart32_serial_init(IMX_BOOT_UART_BASE);
334 #endif
335
336 #if DEBUG_CONSOLE
337 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
338 IMX_CONSOLE_BAUDRATE, &console);
339 #endif
340
341 /* turn on MU1 for non-secure OS/Hypervisor */
342 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
343 /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */
344 sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
345 sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
346 mmio_write_32(IMX_GPT_LPCG_BASE, mmio_read_32(IMX_GPT_LPCG_BASE) | (1 << 25));
347
348 /*
349 * create new partition for non-secure OS/Hypervisor
350 * uses global structs defined in sec_rsrc.h
351 */
352 mx8_partition_resources();
353
354 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
355 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
356 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
357
358 /* init the first cluster's cci slave interface */
359 cci_init(PLAT_CCI_BASE, imx8qm_cci_map, PLATFORM_CLUSTER_COUNT);
360 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
361 }
362
bl31_plat_arch_setup(void)363 void bl31_plat_arch_setup(void)
364 {
365 unsigned long ro_start = BL31_RO_START;
366 unsigned long ro_size = BL31_RO_END - BL31_RO_START;
367 unsigned long rw_start = BL31_RW_START;
368 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
369 #if USE_COHERENT_MEM
370 unsigned long coh_start = BL31_COHERENT_RAM_START;
371 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START;
372 #endif
373
374 mmap_add_region(ro_start, ro_start, ro_size,
375 MT_RO | MT_MEMORY | MT_SECURE);
376 mmap_add_region(rw_start, rw_start, rw_size,
377 MT_RW | MT_MEMORY | MT_SECURE);
378 mmap_add(imx_mmap);
379
380 #if USE_COHERENT_MEM
381 mmap_add_region(coh_start, coh_start, coh_size,
382 MT_DEVICE | MT_RW | MT_SECURE);
383 #endif
384
385 /* setup xlat table */
386 init_xlat_tables();
387 /* enable the MMU */
388 enable_mmu_el3(0);
389 }
390
bl31_platform_setup(void)391 void bl31_platform_setup(void)
392 {
393 plat_gic_driver_init();
394 plat_gic_init();
395 }
396
bl31_plat_get_next_image_ep_info(unsigned int type)397 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
398 {
399 if (type == NON_SECURE)
400 return &bl33_image_ep_info;
401 if (type == SECURE)
402 return &bl32_image_ep_info;
403
404 return NULL;
405 }
406
plat_get_syscnt_freq2(void)407 unsigned int plat_get_syscnt_freq2(void)
408 {
409 return COUNTER_FREQUENCY;
410 }
411
bl31_plat_runtime_setup(void)412 void bl31_plat_runtime_setup(void)
413 {
414 return;
415 }
416
